drivers/mfd/intel_soc_pmic_crc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Device access for Crystal Cove PMIC
0004  *
0005  * Copyright (C) 2013, 2014 Intel Corporation. All rights reserved.
0006  *
0007  * Author: Yang, Bin <bin.yang@intel.com>
0008  * Author: Zhu, Lejun <lejun.zhu@linux.intel.com>
0009  */
0010
0011 #include <linux/interrupt.h>
0012 #include <linux/regmap.h>
0013 #include <linux/mfd/core.h>
0014 #include <linux/mfd/intel_soc_pmic.h>
0015
0016 #include "intel_soc_pmic_core.h"
0017
0018 #define CRYSTAL_COVE_MAX_REGISTER   0xC6
0019
0020 #define CRYSTAL_COVE_REG_IRQLVL1    0x02
0021 #define CRYSTAL_COVE_REG_MIRQLVL1   0x0E
0022
0023 #define CRYSTAL_COVE_IRQ_PWRSRC     0
0024 #define CRYSTAL_COVE_IRQ_THRM       1
0025 #define CRYSTAL_COVE_IRQ_BCU        2
0026 #define CRYSTAL_COVE_IRQ_ADC        3
0027 #define CRYSTAL_COVE_IRQ_CHGR       4
0028 #define CRYSTAL_COVE_IRQ_GPIO       5
0029 #define CRYSTAL_COVE_IRQ_VHDMIOCP   6
0030
0031 static const struct resource pwrsrc_resources[] = {
0032     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_PWRSRC, "PWRSRC"),
0033 };
0034
0035 static const struct resource thermal_resources[] = {
0036     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_THRM, "THERMAL"),
0037 };
0038
0039 static const struct resource bcu_resources[] = {
0040     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_BCU, "BCU"),
0041 };
0042
0043 static const struct resource adc_resources[] = {
0044     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_ADC, "ADC"),
0045 };
0046
0047 static const struct resource charger_resources[] = {
0048     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_CHGR, "CHGR"),
0049 };
0050
0051 static const struct resource gpio_resources[] = {
0052     DEFINE_RES_IRQ_NAMED(CRYSTAL_COVE_IRQ_GPIO, "GPIO"),
0053 };
0054
0055 static struct mfd_cell crystal_cove_byt_dev[] = {
0056     {
0057         .name = "crystal_cove_pwrsrc",
0058         .num_resources = ARRAY_SIZE(pwrsrc_resources),
0059         .resources = pwrsrc_resources,
0060     },
0061     {
0062         .name = "crystal_cove_thermal",
0063         .num_resources = ARRAY_SIZE(thermal_resources),
0064         .resources = thermal_resources,
0065     },
0066     {
0067         .name = "crystal_cove_bcu",
0068         .num_resources = ARRAY_SIZE(bcu_resources),
0069         .resources = bcu_resources,
0070     },
0071     {
0072         .name = "crystal_cove_adc",
0073         .num_resources = ARRAY_SIZE(adc_resources),
0074         .resources = adc_resources,
0075     },
0076     {
0077         .name = "crystal_cove_charger",
0078         .num_resources = ARRAY_SIZE(charger_resources),
0079         .resources = charger_resources,
0080     },
0081     {
0082         .name = "crystal_cove_gpio",
0083         .num_resources = ARRAY_SIZE(gpio_resources),
0084         .resources = gpio_resources,
0085     },
0086     {
0087         .name = "byt_crystal_cove_pmic",
0088     },
0089     {
0090         .name = "crystal_cove_pwm",
0091     },
0092 };
0093
0094 static struct mfd_cell crystal_cove_cht_dev[] = {
0095     {
0096         .name = "crystal_cove_gpio",
0097         .num_resources = ARRAY_SIZE(gpio_resources),
0098         .resources = gpio_resources,
0099     },
0100     {
0101         .name = "cht_crystal_cove_pmic",
0102     },
0103     {
0104         .name = "crystal_cove_pwm",
0105     },
0106 };
0107
0108 static const struct regmap_config crystal_cove_regmap_config = {
0109     .reg_bits = 8,
0110     .val_bits = 8,
0111
0112     .max_register = CRYSTAL_COVE_MAX_REGISTER,
0113     .cache_type = REGCACHE_NONE,
0114 };
0115
0116 static const struct regmap_irq crystal_cove_irqs[] = {
0117     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_PWRSRC, 0, BIT(CRYSTAL_COVE_IRQ_PWRSRC)),
0118     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_THRM, 0, BIT(CRYSTAL_COVE_IRQ_THRM)),
0119     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_BCU, 0, BIT(CRYSTAL_COVE_IRQ_BCU)),
0120     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_ADC, 0, BIT(CRYSTAL_COVE_IRQ_ADC)),
0121     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_CHGR, 0, BIT(CRYSTAL_COVE_IRQ_CHGR)),
0122     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_GPIO, 0, BIT(CRYSTAL_COVE_IRQ_GPIO)),
0123     REGMAP_IRQ_REG(CRYSTAL_COVE_IRQ_VHDMIOCP, 0, BIT(CRYSTAL_COVE_IRQ_VHDMIOCP)),
0124 };
0125
0126 static const struct regmap_irq_chip crystal_cove_irq_chip = {
0127     .name = "Crystal Cove",
0128     .irqs = crystal_cove_irqs,
0129     .num_irqs = ARRAY_SIZE(crystal_cove_irqs),
0130     .num_regs = 1,
0131     .status_base = CRYSTAL_COVE_REG_IRQLVL1,
0132     .mask_base = CRYSTAL_COVE_REG_MIRQLVL1,
0133 };
0134
0135 struct intel_soc_pmic_config intel_soc_pmic_config_byt_crc = {
0136     .irq_flags = IRQF_TRIGGER_RISING,
0137     .cell_dev = crystal_cove_byt_dev,
0138     .n_cell_devs = ARRAY_SIZE(crystal_cove_byt_dev),
0139     .regmap_config = &crystal_cove_regmap_config,
0140     .irq_chip = &crystal_cove_irq_chip,
0141 };
0142
0143 struct intel_soc_pmic_config intel_soc_pmic_config_cht_crc = {
0144     .irq_flags = IRQF_TRIGGER_RISING,
0145     .cell_dev = crystal_cove_cht_dev,
0146     .n_cell_devs = ARRAY_SIZE(crystal_cove_cht_dev),
0147     .regmap_config = &crystal_cove_regmap_config,
0148     .irq_chip = &crystal_cove_irq_chip,
0149 };