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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Intel Sunrisepoint LPSS core support.
0004  *
0005  * Copyright (C) 2015, Intel Corporation
0006  *
0007  * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
0008  *          Mika Westerberg <mika.westerberg@linux.intel.com>
0009  *          Heikki Krogerus <heikki.krogerus@linux.intel.com>
0010  *          Jarkko Nikula <jarkko.nikula@linux.intel.com>
0011  */
0012 
0013 #include <linux/clk.h>
0014 #include <linux/clkdev.h>
0015 #include <linux/clk-provider.h>
0016 #include <linux/debugfs.h>
0017 #include <linux/idr.h>
0018 #include <linux/io.h>
0019 #include <linux/ioport.h>
0020 #include <linux/kernel.h>
0021 #include <linux/module.h>
0022 #include <linux/mfd/core.h>
0023 #include <linux/pm_qos.h>
0024 #include <linux/pm_runtime.h>
0025 #include <linux/property.h>
0026 #include <linux/seq_file.h>
0027 #include <linux/io-64-nonatomic-lo-hi.h>
0028 
0029 #include <linux/dma/idma64.h>
0030 
0031 #include "intel-lpss.h"
0032 
0033 #define LPSS_DEV_OFFSET     0x000
0034 #define LPSS_DEV_SIZE       0x200
0035 #define LPSS_PRIV_OFFSET    0x200
0036 #define LPSS_PRIV_SIZE      0x100
0037 #define LPSS_PRIV_REG_COUNT (LPSS_PRIV_SIZE / 4)
0038 #define LPSS_IDMA64_OFFSET  0x800
0039 #define LPSS_IDMA64_SIZE    0x800
0040 
0041 /* Offsets from lpss->priv */
0042 #define LPSS_PRIV_RESETS        0x04
0043 #define LPSS_PRIV_RESETS_IDMA       BIT(2)
0044 #define LPSS_PRIV_RESETS_FUNC       0x3
0045 
0046 #define LPSS_PRIV_ACTIVELTR     0x10
0047 #define LPSS_PRIV_IDLELTR       0x14
0048 
0049 #define LPSS_PRIV_LTR_REQ       BIT(15)
0050 #define LPSS_PRIV_LTR_SCALE_MASK    GENMASK(11, 10)
0051 #define LPSS_PRIV_LTR_SCALE_1US     (2 << 10)
0052 #define LPSS_PRIV_LTR_SCALE_32US    (3 << 10)
0053 #define LPSS_PRIV_LTR_VALUE_MASK    GENMASK(9, 0)
0054 
0055 #define LPSS_PRIV_SSP_REG       0x20
0056 #define LPSS_PRIV_SSP_REG_DIS_DMA_FIN   BIT(0)
0057 
0058 #define LPSS_PRIV_REMAP_ADDR        0x40
0059 
0060 #define LPSS_PRIV_CAPS          0xfc
0061 #define LPSS_PRIV_CAPS_NO_IDMA      BIT(8)
0062 #define LPSS_PRIV_CAPS_TYPE_MASK    GENMASK(7, 4)
0063 #define LPSS_PRIV_CAPS_TYPE_SHIFT   4
0064 
0065 /* This matches the type field in CAPS register */
0066 enum intel_lpss_dev_type {
0067     LPSS_DEV_I2C = 0,
0068     LPSS_DEV_UART,
0069     LPSS_DEV_SPI,
0070 };
0071 
0072 struct intel_lpss {
0073     const struct intel_lpss_platform_info *info;
0074     enum intel_lpss_dev_type type;
0075     struct clk *clk;
0076     struct clk_lookup *clock;
0077     struct mfd_cell *cell;
0078     struct device *dev;
0079     void __iomem *priv;
0080     u32 priv_ctx[LPSS_PRIV_REG_COUNT];
0081     int devid;
0082     u32 caps;
0083     u32 active_ltr;
0084     u32 idle_ltr;
0085     struct dentry *debugfs;
0086 };
0087 
0088 static const struct resource intel_lpss_dev_resources[] = {
0089     DEFINE_RES_MEM_NAMED(LPSS_DEV_OFFSET, LPSS_DEV_SIZE, "lpss_dev"),
0090     DEFINE_RES_MEM_NAMED(LPSS_PRIV_OFFSET, LPSS_PRIV_SIZE, "lpss_priv"),
0091     DEFINE_RES_IRQ(0),
0092 };
0093 
0094 static const struct resource intel_lpss_idma64_resources[] = {
0095     DEFINE_RES_MEM(LPSS_IDMA64_OFFSET, LPSS_IDMA64_SIZE),
0096     DEFINE_RES_IRQ(0),
0097 };
0098 
0099 /*
0100  * Cells needs to be ordered so that the iDMA is created first. This is
0101  * because we need to be sure the DMA is available when the host controller
0102  * driver is probed.
0103  */
0104 static const struct mfd_cell intel_lpss_idma64_cell = {
0105     .name = LPSS_IDMA64_DRIVER_NAME,
0106     .num_resources = ARRAY_SIZE(intel_lpss_idma64_resources),
0107     .resources = intel_lpss_idma64_resources,
0108 };
0109 
0110 static const struct mfd_cell intel_lpss_i2c_cell = {
0111     .name = "i2c_designware",
0112     .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
0113     .resources = intel_lpss_dev_resources,
0114 };
0115 
0116 static const struct mfd_cell intel_lpss_uart_cell = {
0117     .name = "dw-apb-uart",
0118     .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
0119     .resources = intel_lpss_dev_resources,
0120 };
0121 
0122 static const struct mfd_cell intel_lpss_spi_cell = {
0123     .name = "pxa2xx-spi",
0124     .num_resources = ARRAY_SIZE(intel_lpss_dev_resources),
0125     .resources = intel_lpss_dev_resources,
0126 };
0127 
0128 static DEFINE_IDA(intel_lpss_devid_ida);
0129 static struct dentry *intel_lpss_debugfs;
0130 
0131 static void intel_lpss_cache_ltr(struct intel_lpss *lpss)
0132 {
0133     lpss->active_ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
0134     lpss->idle_ltr = readl(lpss->priv + LPSS_PRIV_IDLELTR);
0135 }
0136 
0137 static int intel_lpss_debugfs_add(struct intel_lpss *lpss)
0138 {
0139     struct dentry *dir;
0140 
0141     dir = debugfs_create_dir(dev_name(lpss->dev), intel_lpss_debugfs);
0142     if (IS_ERR(dir))
0143         return PTR_ERR(dir);
0144 
0145     /* Cache the values into lpss structure */
0146     intel_lpss_cache_ltr(lpss);
0147 
0148     debugfs_create_x32("capabilities", S_IRUGO, dir, &lpss->caps);
0149     debugfs_create_x32("active_ltr", S_IRUGO, dir, &lpss->active_ltr);
0150     debugfs_create_x32("idle_ltr", S_IRUGO, dir, &lpss->idle_ltr);
0151 
0152     lpss->debugfs = dir;
0153     return 0;
0154 }
0155 
0156 static void intel_lpss_debugfs_remove(struct intel_lpss *lpss)
0157 {
0158     debugfs_remove_recursive(lpss->debugfs);
0159 }
0160 
0161 static void intel_lpss_ltr_set(struct device *dev, s32 val)
0162 {
0163     struct intel_lpss *lpss = dev_get_drvdata(dev);
0164     u32 ltr;
0165 
0166     /*
0167      * Program latency tolerance (LTR) accordingly what has been asked
0168      * by the PM QoS layer or disable it in case we were passed
0169      * negative value or PM_QOS_LATENCY_ANY.
0170      */
0171     ltr = readl(lpss->priv + LPSS_PRIV_ACTIVELTR);
0172 
0173     if (val == PM_QOS_LATENCY_ANY || val < 0) {
0174         ltr &= ~LPSS_PRIV_LTR_REQ;
0175     } else {
0176         ltr |= LPSS_PRIV_LTR_REQ;
0177         ltr &= ~LPSS_PRIV_LTR_SCALE_MASK;
0178         ltr &= ~LPSS_PRIV_LTR_VALUE_MASK;
0179 
0180         if (val > LPSS_PRIV_LTR_VALUE_MASK)
0181             ltr |= LPSS_PRIV_LTR_SCALE_32US | val >> 5;
0182         else
0183             ltr |= LPSS_PRIV_LTR_SCALE_1US | val;
0184     }
0185 
0186     if (ltr == lpss->active_ltr)
0187         return;
0188 
0189     writel(ltr, lpss->priv + LPSS_PRIV_ACTIVELTR);
0190     writel(ltr, lpss->priv + LPSS_PRIV_IDLELTR);
0191 
0192     /* Cache the values into lpss structure */
0193     intel_lpss_cache_ltr(lpss);
0194 }
0195 
0196 static void intel_lpss_ltr_expose(struct intel_lpss *lpss)
0197 {
0198     lpss->dev->power.set_latency_tolerance = intel_lpss_ltr_set;
0199     dev_pm_qos_expose_latency_tolerance(lpss->dev);
0200 }
0201 
0202 static void intel_lpss_ltr_hide(struct intel_lpss *lpss)
0203 {
0204     dev_pm_qos_hide_latency_tolerance(lpss->dev);
0205     lpss->dev->power.set_latency_tolerance = NULL;
0206 }
0207 
0208 static int intel_lpss_assign_devs(struct intel_lpss *lpss)
0209 {
0210     const struct mfd_cell *cell;
0211     unsigned int type;
0212 
0213     type = lpss->caps & LPSS_PRIV_CAPS_TYPE_MASK;
0214     type >>= LPSS_PRIV_CAPS_TYPE_SHIFT;
0215 
0216     switch (type) {
0217     case LPSS_DEV_I2C:
0218         cell = &intel_lpss_i2c_cell;
0219         break;
0220     case LPSS_DEV_UART:
0221         cell = &intel_lpss_uart_cell;
0222         break;
0223     case LPSS_DEV_SPI:
0224         cell = &intel_lpss_spi_cell;
0225         break;
0226     default:
0227         return -ENODEV;
0228     }
0229 
0230     lpss->cell = devm_kmemdup(lpss->dev, cell, sizeof(*cell), GFP_KERNEL);
0231     if (!lpss->cell)
0232         return -ENOMEM;
0233 
0234     lpss->type = type;
0235 
0236     return 0;
0237 }
0238 
0239 static bool intel_lpss_has_idma(const struct intel_lpss *lpss)
0240 {
0241     return (lpss->caps & LPSS_PRIV_CAPS_NO_IDMA) == 0;
0242 }
0243 
0244 static void intel_lpss_set_remap_addr(const struct intel_lpss *lpss)
0245 {
0246     resource_size_t addr = lpss->info->mem->start;
0247 
0248     lo_hi_writeq(addr, lpss->priv + LPSS_PRIV_REMAP_ADDR);
0249 }
0250 
0251 static void intel_lpss_deassert_reset(const struct intel_lpss *lpss)
0252 {
0253     u32 value = LPSS_PRIV_RESETS_FUNC | LPSS_PRIV_RESETS_IDMA;
0254 
0255     /* Bring out the device from reset */
0256     writel(value, lpss->priv + LPSS_PRIV_RESETS);
0257 }
0258 
0259 static void intel_lpss_init_dev(const struct intel_lpss *lpss)
0260 {
0261     u32 value = LPSS_PRIV_SSP_REG_DIS_DMA_FIN;
0262 
0263     /* Set the device in reset state */
0264     writel(0, lpss->priv + LPSS_PRIV_RESETS);
0265 
0266     intel_lpss_deassert_reset(lpss);
0267 
0268     intel_lpss_set_remap_addr(lpss);
0269 
0270     if (!intel_lpss_has_idma(lpss))
0271         return;
0272 
0273     /* Make sure that SPI multiblock DMA transfers are re-enabled */
0274     if (lpss->type == LPSS_DEV_SPI)
0275         writel(value, lpss->priv + LPSS_PRIV_SSP_REG);
0276 }
0277 
0278 static void intel_lpss_unregister_clock_tree(struct clk *clk)
0279 {
0280     struct clk *parent;
0281 
0282     while (clk) {
0283         parent = clk_get_parent(clk);
0284         clk_unregister(clk);
0285         clk = parent;
0286     }
0287 }
0288 
0289 static int intel_lpss_register_clock_divider(struct intel_lpss *lpss,
0290                          const char *devname,
0291                          struct clk **clk)
0292 {
0293     char name[32];
0294     struct clk *tmp = *clk;
0295 
0296     snprintf(name, sizeof(name), "%s-enable", devname);
0297     tmp = clk_register_gate(NULL, name, __clk_get_name(tmp), 0,
0298                 lpss->priv, 0, 0, NULL);
0299     if (IS_ERR(tmp))
0300         return PTR_ERR(tmp);
0301 
0302     snprintf(name, sizeof(name), "%s-div", devname);
0303     tmp = clk_register_fractional_divider(NULL, name, __clk_get_name(tmp),
0304                           CLK_FRAC_DIVIDER_POWER_OF_TWO_PS,
0305                           lpss->priv, 1, 15, 16, 15, 0,
0306                           NULL);
0307     if (IS_ERR(tmp))
0308         return PTR_ERR(tmp);
0309     *clk = tmp;
0310 
0311     snprintf(name, sizeof(name), "%s-update", devname);
0312     tmp = clk_register_gate(NULL, name, __clk_get_name(tmp),
0313                 CLK_SET_RATE_PARENT, lpss->priv, 31, 0, NULL);
0314     if (IS_ERR(tmp))
0315         return PTR_ERR(tmp);
0316     *clk = tmp;
0317 
0318     return 0;
0319 }
0320 
0321 static int intel_lpss_register_clock(struct intel_lpss *lpss)
0322 {
0323     const struct mfd_cell *cell = lpss->cell;
0324     struct clk *clk;
0325     char devname[24];
0326     int ret;
0327 
0328     if (!lpss->info->clk_rate)
0329         return 0;
0330 
0331     /* Root clock */
0332     clk = clk_register_fixed_rate(NULL, dev_name(lpss->dev), NULL, 0,
0333                       lpss->info->clk_rate);
0334     if (IS_ERR(clk))
0335         return PTR_ERR(clk);
0336 
0337     snprintf(devname, sizeof(devname), "%s.%d", cell->name, lpss->devid);
0338 
0339     /*
0340      * Support for clock divider only if it has some preset value.
0341      * Otherwise we assume that the divider is not used.
0342      */
0343     if (lpss->type != LPSS_DEV_I2C) {
0344         ret = intel_lpss_register_clock_divider(lpss, devname, &clk);
0345         if (ret)
0346             goto err_clk_register;
0347     }
0348 
0349     ret = -ENOMEM;
0350 
0351     /* Clock for the host controller */
0352     lpss->clock = clkdev_create(clk, lpss->info->clk_con_id, "%s", devname);
0353     if (!lpss->clock)
0354         goto err_clk_register;
0355 
0356     lpss->clk = clk;
0357 
0358     return 0;
0359 
0360 err_clk_register:
0361     intel_lpss_unregister_clock_tree(clk);
0362 
0363     return ret;
0364 }
0365 
0366 static void intel_lpss_unregister_clock(struct intel_lpss *lpss)
0367 {
0368     if (IS_ERR_OR_NULL(lpss->clk))
0369         return;
0370 
0371     clkdev_drop(lpss->clock);
0372     intel_lpss_unregister_clock_tree(lpss->clk);
0373 }
0374 
0375 int intel_lpss_probe(struct device *dev,
0376              const struct intel_lpss_platform_info *info)
0377 {
0378     struct intel_lpss *lpss;
0379     int ret;
0380 
0381     if (!info || !info->mem || info->irq <= 0)
0382         return -EINVAL;
0383 
0384     lpss = devm_kzalloc(dev, sizeof(*lpss), GFP_KERNEL);
0385     if (!lpss)
0386         return -ENOMEM;
0387 
0388     lpss->priv = devm_ioremap_uc(dev, info->mem->start + LPSS_PRIV_OFFSET,
0389                   LPSS_PRIV_SIZE);
0390     if (!lpss->priv)
0391         return -ENOMEM;
0392 
0393     lpss->info = info;
0394     lpss->dev = dev;
0395     lpss->caps = readl(lpss->priv + LPSS_PRIV_CAPS);
0396 
0397     dev_set_drvdata(dev, lpss);
0398 
0399     ret = intel_lpss_assign_devs(lpss);
0400     if (ret)
0401         return ret;
0402 
0403     lpss->cell->swnode = info->swnode;
0404     lpss->cell->ignore_resource_conflicts = info->ignore_resource_conflicts;
0405 
0406     intel_lpss_init_dev(lpss);
0407 
0408     lpss->devid = ida_simple_get(&intel_lpss_devid_ida, 0, 0, GFP_KERNEL);
0409     if (lpss->devid < 0)
0410         return lpss->devid;
0411 
0412     ret = intel_lpss_register_clock(lpss);
0413     if (ret)
0414         goto err_clk_register;
0415 
0416     intel_lpss_ltr_expose(lpss);
0417 
0418     ret = intel_lpss_debugfs_add(lpss);
0419     if (ret)
0420         dev_warn(dev, "Failed to create debugfs entries\n");
0421 
0422     if (intel_lpss_has_idma(lpss)) {
0423         ret = mfd_add_devices(dev, lpss->devid, &intel_lpss_idma64_cell,
0424                       1, info->mem, info->irq, NULL);
0425         if (ret)
0426             dev_warn(dev, "Failed to add %s, fallback to PIO\n",
0427                  LPSS_IDMA64_DRIVER_NAME);
0428     }
0429 
0430     ret = mfd_add_devices(dev, lpss->devid, lpss->cell,
0431                   1, info->mem, info->irq, NULL);
0432     if (ret)
0433         goto err_remove_ltr;
0434 
0435     dev_pm_set_driver_flags(dev, DPM_FLAG_SMART_SUSPEND);
0436 
0437     return 0;
0438 
0439 err_remove_ltr:
0440     intel_lpss_debugfs_remove(lpss);
0441     intel_lpss_ltr_hide(lpss);
0442     intel_lpss_unregister_clock(lpss);
0443 
0444 err_clk_register:
0445     ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
0446 
0447     return ret;
0448 }
0449 EXPORT_SYMBOL_GPL(intel_lpss_probe);
0450 
0451 void intel_lpss_remove(struct device *dev)
0452 {
0453     struct intel_lpss *lpss = dev_get_drvdata(dev);
0454 
0455     mfd_remove_devices(dev);
0456     intel_lpss_debugfs_remove(lpss);
0457     intel_lpss_ltr_hide(lpss);
0458     intel_lpss_unregister_clock(lpss);
0459     ida_simple_remove(&intel_lpss_devid_ida, lpss->devid);
0460 }
0461 EXPORT_SYMBOL_GPL(intel_lpss_remove);
0462 
0463 static int resume_lpss_device(struct device *dev, void *data)
0464 {
0465     if (!dev_pm_test_driver_flags(dev, DPM_FLAG_SMART_SUSPEND))
0466         pm_runtime_resume(dev);
0467 
0468     return 0;
0469 }
0470 
0471 int intel_lpss_prepare(struct device *dev)
0472 {
0473     /*
0474      * Resume both child devices before entering system sleep. This
0475      * ensures that they are in proper state before they get suspended.
0476      */
0477     device_for_each_child_reverse(dev, NULL, resume_lpss_device);
0478     return 0;
0479 }
0480 EXPORT_SYMBOL_GPL(intel_lpss_prepare);
0481 
0482 int intel_lpss_suspend(struct device *dev)
0483 {
0484     struct intel_lpss *lpss = dev_get_drvdata(dev);
0485     unsigned int i;
0486 
0487     /* Save device context */
0488     for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
0489         lpss->priv_ctx[i] = readl(lpss->priv + i * 4);
0490 
0491     /*
0492      * If the device type is not UART, then put the controller into
0493      * reset. UART cannot be put into reset since S3/S0ix fail when
0494      * no_console_suspend flag is enabled.
0495      */
0496     if (lpss->type != LPSS_DEV_UART)
0497         writel(0, lpss->priv + LPSS_PRIV_RESETS);
0498 
0499     return 0;
0500 }
0501 EXPORT_SYMBOL_GPL(intel_lpss_suspend);
0502 
0503 int intel_lpss_resume(struct device *dev)
0504 {
0505     struct intel_lpss *lpss = dev_get_drvdata(dev);
0506     unsigned int i;
0507 
0508     intel_lpss_deassert_reset(lpss);
0509 
0510     /* Restore device context */
0511     for (i = 0; i < LPSS_PRIV_REG_COUNT; i++)
0512         writel(lpss->priv_ctx[i], lpss->priv + i * 4);
0513 
0514     return 0;
0515 }
0516 EXPORT_SYMBOL_GPL(intel_lpss_resume);
0517 
0518 static int __init intel_lpss_init(void)
0519 {
0520     intel_lpss_debugfs = debugfs_create_dir("intel_lpss", NULL);
0521     return 0;
0522 }
0523 module_init(intel_lpss_init);
0524 
0525 static void __exit intel_lpss_exit(void)
0526 {
0527     ida_destroy(&intel_lpss_devid_ida);
0528     debugfs_remove(intel_lpss_debugfs);
0529 }
0530 module_exit(intel_lpss_exit);
0531 
0532 MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
0533 MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
0534 MODULE_AUTHOR("Heikki Krogerus <heikki.krogerus@linux.intel.com>");
0535 MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
0536 MODULE_DESCRIPTION("Intel LPSS core driver");
0537 MODULE_LICENSE("GPL v2");
0538 /*
0539  * Ensure the DMA driver is loaded before the host controller device appears,
0540  * so that the host controller driver can request its DMA channels as early
0541  * as possible.
0542  *
0543  * If the DMA module is not there that's OK as well.
0544  */
0545 MODULE_SOFTDEP("pre: platform:" LPSS_IDMA64_DRIVER_NAME);
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