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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * driver/mfd/asic3.c
0004  *
0005  * Compaq ASIC3 support.
0006  *
0007  * Copyright 2001 Compaq Computer Corporation.
0008  * Copyright 2004-2005 Phil Blundell
0009  * Copyright 2007-2008 OpenedHand Ltd.
0010  *
0011  * Authors: Phil Blundell <pb@handhelds.org>,
0012  *      Samuel Ortiz <sameo@openedhand.com>
0013  */
0014 
0015 #include <linux/kernel.h>
0016 #include <linux/delay.h>
0017 #include <linux/irq.h>
0018 #include <linux/gpio/driver.h>
0019 #include <linux/export.h>
0020 #include <linux/io.h>
0021 #include <linux/slab.h>
0022 #include <linux/spinlock.h>
0023 #include <linux/platform_device.h>
0024 
0025 #include <linux/mfd/asic3.h>
0026 #include <linux/mfd/core.h>
0027 #include <linux/mfd/ds1wm.h>
0028 #include <linux/mfd/tmio.h>
0029 
0030 #include <linux/mmc/host.h>
0031 
0032 enum {
0033     ASIC3_CLOCK_SPI,
0034     ASIC3_CLOCK_OWM,
0035     ASIC3_CLOCK_PWM0,
0036     ASIC3_CLOCK_PWM1,
0037     ASIC3_CLOCK_LED0,
0038     ASIC3_CLOCK_LED1,
0039     ASIC3_CLOCK_LED2,
0040     ASIC3_CLOCK_SD_HOST,
0041     ASIC3_CLOCK_SD_BUS,
0042     ASIC3_CLOCK_SMBUS,
0043     ASIC3_CLOCK_EX0,
0044     ASIC3_CLOCK_EX1,
0045 };
0046 
0047 struct asic3_clk {
0048     int enabled;
0049     unsigned int cdex;
0050     unsigned long rate;
0051 };
0052 
0053 #define INIT_CDEX(_name, _rate) \
0054     [ASIC3_CLOCK_##_name] = {       \
0055         .cdex = CLOCK_CDEX_##_name, \
0056         .rate = _rate,          \
0057     }
0058 
0059 static struct asic3_clk asic3_clk_init[] __initdata = {
0060     INIT_CDEX(SPI, 0),
0061     INIT_CDEX(OWM, 5000000),
0062     INIT_CDEX(PWM0, 0),
0063     INIT_CDEX(PWM1, 0),
0064     INIT_CDEX(LED0, 0),
0065     INIT_CDEX(LED1, 0),
0066     INIT_CDEX(LED2, 0),
0067     INIT_CDEX(SD_HOST, 24576000),
0068     INIT_CDEX(SD_BUS, 12288000),
0069     INIT_CDEX(SMBUS, 0),
0070     INIT_CDEX(EX0, 32768),
0071     INIT_CDEX(EX1, 24576000),
0072 };
0073 
0074 struct asic3 {
0075     void __iomem *mapping;
0076     unsigned int bus_shift;
0077     unsigned int irq_nr;
0078     unsigned int irq_base;
0079     raw_spinlock_t lock;
0080     u16 irq_bothedge[4];
0081     struct gpio_chip gpio;
0082     struct device *dev;
0083     void __iomem *tmio_cnf;
0084 
0085     struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
0086 };
0087 
0088 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
0089 
0090 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
0091 {
0092     iowrite16(value, asic->mapping +
0093           (reg >> asic->bus_shift));
0094 }
0095 EXPORT_SYMBOL_GPL(asic3_write_register);
0096 
0097 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
0098 {
0099     return ioread16(asic->mapping +
0100             (reg >> asic->bus_shift));
0101 }
0102 EXPORT_SYMBOL_GPL(asic3_read_register);
0103 
0104 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
0105 {
0106     unsigned long flags;
0107     u32 val;
0108 
0109     raw_spin_lock_irqsave(&asic->lock, flags);
0110     val = asic3_read_register(asic, reg);
0111     if (set)
0112         val |= bits;
0113     else
0114         val &= ~bits;
0115     asic3_write_register(asic, reg, val);
0116     raw_spin_unlock_irqrestore(&asic->lock, flags);
0117 }
0118 
0119 /* IRQs */
0120 #define MAX_ASIC_ISR_LOOPS    20
0121 #define ASIC3_GPIO_BASE_INCR \
0122     (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
0123 
0124 static void asic3_irq_flip_edge(struct asic3 *asic,
0125                 u32 base, int bit)
0126 {
0127     u16 edge;
0128     unsigned long flags;
0129 
0130     raw_spin_lock_irqsave(&asic->lock, flags);
0131     edge = asic3_read_register(asic,
0132                    base + ASIC3_GPIO_EDGE_TRIGGER);
0133     edge ^= bit;
0134     asic3_write_register(asic,
0135                  base + ASIC3_GPIO_EDGE_TRIGGER, edge);
0136     raw_spin_unlock_irqrestore(&asic->lock, flags);
0137 }
0138 
0139 static void asic3_irq_demux(struct irq_desc *desc)
0140 {
0141     struct asic3 *asic = irq_desc_get_handler_data(desc);
0142     struct irq_data *data = irq_desc_get_irq_data(desc);
0143     int iter, i;
0144     unsigned long flags;
0145 
0146     data->chip->irq_ack(data);
0147 
0148     for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
0149         u32 status;
0150         int bank;
0151 
0152         raw_spin_lock_irqsave(&asic->lock, flags);
0153         status = asic3_read_register(asic,
0154                          ASIC3_OFFSET(INTR, P_INT_STAT));
0155         raw_spin_unlock_irqrestore(&asic->lock, flags);
0156 
0157         /* Check all ten register bits */
0158         if ((status & 0x3ff) == 0)
0159             break;
0160 
0161         /* Handle GPIO IRQs */
0162         for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
0163             if (status & (1 << bank)) {
0164                 unsigned long base, istat;
0165 
0166                 base = ASIC3_GPIO_A_BASE
0167                        + bank * ASIC3_GPIO_BASE_INCR;
0168                 raw_spin_lock_irqsave(&asic->lock, flags);
0169                 istat = asic3_read_register(asic,
0170                                 base +
0171                                 ASIC3_GPIO_INT_STATUS);
0172                 /* Clearing IntStatus */
0173                 asic3_write_register(asic,
0174                              base +
0175                              ASIC3_GPIO_INT_STATUS, 0);
0176                 raw_spin_unlock_irqrestore(&asic->lock, flags);
0177 
0178                 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
0179                     int bit = (1 << i);
0180                     unsigned int irqnr;
0181 
0182                     if (!(istat & bit))
0183                         continue;
0184 
0185                     irqnr = asic->irq_base +
0186                         (ASIC3_GPIOS_PER_BANK * bank)
0187                         + i;
0188                     generic_handle_irq(irqnr);
0189                     if (asic->irq_bothedge[bank] & bit)
0190                         asic3_irq_flip_edge(asic, base,
0191                                     bit);
0192                 }
0193             }
0194         }
0195 
0196         /* Handle remaining IRQs in the status register */
0197         for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
0198             /* They start at bit 4 and go up */
0199             if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
0200                 generic_handle_irq(asic->irq_base + i);
0201         }
0202     }
0203 
0204     if (iter >= MAX_ASIC_ISR_LOOPS)
0205         dev_err(asic->dev, "interrupt processing overrun\n");
0206 }
0207 
0208 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
0209 {
0210     int n;
0211 
0212     n = (irq - asic->irq_base) >> 4;
0213 
0214     return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
0215 }
0216 
0217 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
0218 {
0219     return (irq - asic->irq_base) & 0xf;
0220 }
0221 
0222 static void asic3_mask_gpio_irq(struct irq_data *data)
0223 {
0224     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0225     u32 val, bank, index;
0226     unsigned long flags;
0227 
0228     bank = asic3_irq_to_bank(asic, data->irq);
0229     index = asic3_irq_to_index(asic, data->irq);
0230 
0231     raw_spin_lock_irqsave(&asic->lock, flags);
0232     val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
0233     val |= 1 << index;
0234     asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
0235     raw_spin_unlock_irqrestore(&asic->lock, flags);
0236 }
0237 
0238 static void asic3_mask_irq(struct irq_data *data)
0239 {
0240     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0241     int regval;
0242     unsigned long flags;
0243 
0244     raw_spin_lock_irqsave(&asic->lock, flags);
0245     regval = asic3_read_register(asic,
0246                      ASIC3_INTR_BASE +
0247                      ASIC3_INTR_INT_MASK);
0248 
0249     regval &= ~(ASIC3_INTMASK_MASK0 <<
0250             (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
0251 
0252     asic3_write_register(asic,
0253                  ASIC3_INTR_BASE +
0254                  ASIC3_INTR_INT_MASK,
0255                  regval);
0256     raw_spin_unlock_irqrestore(&asic->lock, flags);
0257 }
0258 
0259 static void asic3_unmask_gpio_irq(struct irq_data *data)
0260 {
0261     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0262     u32 val, bank, index;
0263     unsigned long flags;
0264 
0265     bank = asic3_irq_to_bank(asic, data->irq);
0266     index = asic3_irq_to_index(asic, data->irq);
0267 
0268     raw_spin_lock_irqsave(&asic->lock, flags);
0269     val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
0270     val &= ~(1 << index);
0271     asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
0272     raw_spin_unlock_irqrestore(&asic->lock, flags);
0273 }
0274 
0275 static void asic3_unmask_irq(struct irq_data *data)
0276 {
0277     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0278     int regval;
0279     unsigned long flags;
0280 
0281     raw_spin_lock_irqsave(&asic->lock, flags);
0282     regval = asic3_read_register(asic,
0283                      ASIC3_INTR_BASE +
0284                      ASIC3_INTR_INT_MASK);
0285 
0286     regval |= (ASIC3_INTMASK_MASK0 <<
0287            (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
0288 
0289     asic3_write_register(asic,
0290                  ASIC3_INTR_BASE +
0291                  ASIC3_INTR_INT_MASK,
0292                  regval);
0293     raw_spin_unlock_irqrestore(&asic->lock, flags);
0294 }
0295 
0296 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
0297 {
0298     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0299     u32 bank, index;
0300     u16 trigger, level, edge, bit;
0301     unsigned long flags;
0302 
0303     bank = asic3_irq_to_bank(asic, data->irq);
0304     index = asic3_irq_to_index(asic, data->irq);
0305     bit = 1<<index;
0306 
0307     raw_spin_lock_irqsave(&asic->lock, flags);
0308     level = asic3_read_register(asic,
0309                     bank + ASIC3_GPIO_LEVEL_TRIGGER);
0310     edge = asic3_read_register(asic,
0311                    bank + ASIC3_GPIO_EDGE_TRIGGER);
0312     trigger = asic3_read_register(asic,
0313                       bank + ASIC3_GPIO_TRIGGER_TYPE);
0314     asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
0315 
0316     if (type == IRQ_TYPE_EDGE_RISING) {
0317         trigger |= bit;
0318         edge |= bit;
0319     } else if (type == IRQ_TYPE_EDGE_FALLING) {
0320         trigger |= bit;
0321         edge &= ~bit;
0322     } else if (type == IRQ_TYPE_EDGE_BOTH) {
0323         trigger |= bit;
0324         if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
0325             edge &= ~bit;
0326         else
0327             edge |= bit;
0328         asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
0329     } else if (type == IRQ_TYPE_LEVEL_LOW) {
0330         trigger &= ~bit;
0331         level &= ~bit;
0332     } else if (type == IRQ_TYPE_LEVEL_HIGH) {
0333         trigger &= ~bit;
0334         level |= bit;
0335     } else {
0336         /*
0337          * if type == IRQ_TYPE_NONE, we should mask interrupts, but
0338          * be careful to not unmask them if mask was also called.
0339          * Probably need internal state for mask.
0340          */
0341         dev_notice(asic->dev, "irq type not changed\n");
0342     }
0343     asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
0344                  level);
0345     asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
0346                  edge);
0347     asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
0348                  trigger);
0349     raw_spin_unlock_irqrestore(&asic->lock, flags);
0350     return 0;
0351 }
0352 
0353 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
0354 {
0355     struct asic3 *asic = irq_data_get_irq_chip_data(data);
0356     u32 bank, index;
0357     u16 bit;
0358 
0359     bank = asic3_irq_to_bank(asic, data->irq);
0360     index = asic3_irq_to_index(asic, data->irq);
0361     bit = 1<<index;
0362 
0363     asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
0364 
0365     return 0;
0366 }
0367 
0368 static struct irq_chip asic3_gpio_irq_chip = {
0369     .name       = "ASIC3-GPIO",
0370     .irq_ack    = asic3_mask_gpio_irq,
0371     .irq_mask   = asic3_mask_gpio_irq,
0372     .irq_unmask = asic3_unmask_gpio_irq,
0373     .irq_set_type   = asic3_gpio_irq_type,
0374     .irq_set_wake   = asic3_gpio_irq_set_wake,
0375 };
0376 
0377 static struct irq_chip asic3_irq_chip = {
0378     .name       = "ASIC3",
0379     .irq_ack    = asic3_mask_irq,
0380     .irq_mask   = asic3_mask_irq,
0381     .irq_unmask = asic3_unmask_irq,
0382 };
0383 
0384 static int __init asic3_irq_probe(struct platform_device *pdev)
0385 {
0386     struct asic3 *asic = platform_get_drvdata(pdev);
0387     unsigned long clksel = 0;
0388     unsigned int irq, irq_base;
0389     int ret;
0390 
0391     ret = platform_get_irq(pdev, 0);
0392     if (ret < 0)
0393         return ret;
0394     asic->irq_nr = ret;
0395 
0396     /* turn on clock to IRQ controller */
0397     clksel |= CLOCK_SEL_CX;
0398     asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
0399                  clksel);
0400 
0401     irq_base = asic->irq_base;
0402 
0403     for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
0404         if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
0405             irq_set_chip(irq, &asic3_gpio_irq_chip);
0406         else
0407             irq_set_chip(irq, &asic3_irq_chip);
0408 
0409         irq_set_chip_data(irq, asic);
0410         irq_set_handler(irq, handle_level_irq);
0411         irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
0412     }
0413 
0414     asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
0415                  ASIC3_INTMASK_GINTMASK);
0416 
0417     irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
0418     irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
0419 
0420     return 0;
0421 }
0422 
0423 static void asic3_irq_remove(struct platform_device *pdev)
0424 {
0425     struct asic3 *asic = platform_get_drvdata(pdev);
0426     unsigned int irq, irq_base;
0427 
0428     irq_base = asic->irq_base;
0429 
0430     for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
0431         irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
0432         irq_set_chip_and_handler(irq, NULL, NULL);
0433         irq_set_chip_data(irq, NULL);
0434     }
0435     irq_set_chained_handler(asic->irq_nr, NULL);
0436 }
0437 
0438 /* GPIOs */
0439 static int asic3_gpio_direction(struct gpio_chip *chip,
0440                 unsigned offset, int out)
0441 {
0442     u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
0443     unsigned int gpio_base;
0444     unsigned long flags;
0445     struct asic3 *asic;
0446 
0447     asic = gpiochip_get_data(chip);
0448     gpio_base = ASIC3_GPIO_TO_BASE(offset);
0449 
0450     if (gpio_base > ASIC3_GPIO_D_BASE) {
0451         dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
0452             gpio_base, offset);
0453         return -EINVAL;
0454     }
0455 
0456     raw_spin_lock_irqsave(&asic->lock, flags);
0457 
0458     out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
0459 
0460     /* Input is 0, Output is 1 */
0461     if (out)
0462         out_reg |= mask;
0463     else
0464         out_reg &= ~mask;
0465 
0466     asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
0467 
0468     raw_spin_unlock_irqrestore(&asic->lock, flags);
0469 
0470     return 0;
0471 
0472 }
0473 
0474 static int asic3_gpio_direction_input(struct gpio_chip *chip,
0475                       unsigned offset)
0476 {
0477     return asic3_gpio_direction(chip, offset, 0);
0478 }
0479 
0480 static int asic3_gpio_direction_output(struct gpio_chip *chip,
0481                        unsigned offset, int value)
0482 {
0483     return asic3_gpio_direction(chip, offset, 1);
0484 }
0485 
0486 static int asic3_gpio_get(struct gpio_chip *chip,
0487               unsigned offset)
0488 {
0489     unsigned int gpio_base;
0490     u32 mask = ASIC3_GPIO_TO_MASK(offset);
0491     struct asic3 *asic;
0492 
0493     asic = gpiochip_get_data(chip);
0494     gpio_base = ASIC3_GPIO_TO_BASE(offset);
0495 
0496     if (gpio_base > ASIC3_GPIO_D_BASE) {
0497         dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
0498             gpio_base, offset);
0499         return -EINVAL;
0500     }
0501 
0502     return !!(asic3_read_register(asic,
0503                       gpio_base + ASIC3_GPIO_STATUS) & mask);
0504 }
0505 
0506 static void asic3_gpio_set(struct gpio_chip *chip,
0507                unsigned offset, int value)
0508 {
0509     u32 mask, out_reg;
0510     unsigned int gpio_base;
0511     unsigned long flags;
0512     struct asic3 *asic;
0513 
0514     asic = gpiochip_get_data(chip);
0515     gpio_base = ASIC3_GPIO_TO_BASE(offset);
0516 
0517     if (gpio_base > ASIC3_GPIO_D_BASE) {
0518         dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
0519             gpio_base, offset);
0520         return;
0521     }
0522 
0523     mask = ASIC3_GPIO_TO_MASK(offset);
0524 
0525     raw_spin_lock_irqsave(&asic->lock, flags);
0526 
0527     out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
0528 
0529     if (value)
0530         out_reg |= mask;
0531     else
0532         out_reg &= ~mask;
0533 
0534     asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
0535 
0536     raw_spin_unlock_irqrestore(&asic->lock, flags);
0537 }
0538 
0539 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
0540 {
0541     struct asic3 *asic = gpiochip_get_data(chip);
0542 
0543     return asic->irq_base + offset;
0544 }
0545 
0546 static __init int asic3_gpio_probe(struct platform_device *pdev,
0547                    u16 *gpio_config, int num)
0548 {
0549     struct asic3 *asic = platform_get_drvdata(pdev);
0550     u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
0551     u16 out_reg[ASIC3_NUM_GPIO_BANKS];
0552     u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
0553     int i;
0554 
0555     memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
0556     memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
0557     memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
0558 
0559     /* Enable all GPIOs */
0560     asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
0561     asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
0562     asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
0563     asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
0564 
0565     for (i = 0; i < num; i++) {
0566         u8 alt, pin, dir, init, bank_num, bit_num;
0567         u16 config = gpio_config[i];
0568 
0569         pin = ASIC3_CONFIG_GPIO_PIN(config);
0570         alt = ASIC3_CONFIG_GPIO_ALT(config);
0571         dir = ASIC3_CONFIG_GPIO_DIR(config);
0572         init = ASIC3_CONFIG_GPIO_INIT(config);
0573 
0574         bank_num = ASIC3_GPIO_TO_BANK(pin);
0575         bit_num = ASIC3_GPIO_TO_BIT(pin);
0576 
0577         alt_reg[bank_num] |= (alt << bit_num);
0578         out_reg[bank_num] |= (init << bit_num);
0579         dir_reg[bank_num] |= (dir << bit_num);
0580     }
0581 
0582     for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
0583         asic3_write_register(asic,
0584                      ASIC3_BANK_TO_BASE(i) +
0585                      ASIC3_GPIO_DIRECTION,
0586                      dir_reg[i]);
0587         asic3_write_register(asic,
0588                      ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
0589                      out_reg[i]);
0590         asic3_write_register(asic,
0591                      ASIC3_BANK_TO_BASE(i) +
0592                      ASIC3_GPIO_ALT_FUNCTION,
0593                      alt_reg[i]);
0594     }
0595 
0596     return gpiochip_add_data(&asic->gpio, asic);
0597 }
0598 
0599 static void asic3_gpio_remove(struct platform_device *pdev)
0600 {
0601     struct asic3 *asic = platform_get_drvdata(pdev);
0602 
0603     gpiochip_remove(&asic->gpio);
0604 }
0605 
0606 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
0607 {
0608     unsigned long flags;
0609     u32 cdex;
0610 
0611     raw_spin_lock_irqsave(&asic->lock, flags);
0612     if (clk->enabled++ == 0) {
0613         cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
0614         cdex |= clk->cdex;
0615         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
0616     }
0617     raw_spin_unlock_irqrestore(&asic->lock, flags);
0618 }
0619 
0620 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
0621 {
0622     unsigned long flags;
0623     u32 cdex;
0624 
0625     WARN_ON(clk->enabled == 0);
0626 
0627     raw_spin_lock_irqsave(&asic->lock, flags);
0628     if (--clk->enabled == 0) {
0629         cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
0630         cdex &= ~clk->cdex;
0631         asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
0632     }
0633     raw_spin_unlock_irqrestore(&asic->lock, flags);
0634 }
0635 
0636 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
0637 static struct ds1wm_driver_data ds1wm_pdata = {
0638     .active_high = 1,
0639     .reset_recover_delay = 1,
0640 };
0641 
0642 static struct resource ds1wm_resources[] = {
0643     {
0644         .start = ASIC3_OWM_BASE,
0645         .end   = ASIC3_OWM_BASE + 0x13,
0646         .flags = IORESOURCE_MEM,
0647     },
0648     {
0649         .start = ASIC3_IRQ_OWM,
0650         .end   = ASIC3_IRQ_OWM,
0651         .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
0652     },
0653 };
0654 
0655 static int ds1wm_enable(struct platform_device *pdev)
0656 {
0657     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0658 
0659     /* Turn on external clocks and the OWM clock */
0660     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
0661     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
0662     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
0663     usleep_range(1000, 5000);
0664 
0665     /* Reset and enable DS1WM */
0666     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
0667                ASIC3_EXTCF_OWM_RESET, 1);
0668     usleep_range(1000, 5000);
0669     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
0670                ASIC3_EXTCF_OWM_RESET, 0);
0671     usleep_range(1000, 5000);
0672     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
0673                ASIC3_EXTCF_OWM_EN, 1);
0674     usleep_range(1000, 5000);
0675 
0676     return 0;
0677 }
0678 
0679 static int ds1wm_disable(struct platform_device *pdev)
0680 {
0681     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0682 
0683     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
0684                ASIC3_EXTCF_OWM_EN, 0);
0685 
0686     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
0687     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
0688     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
0689 
0690     return 0;
0691 }
0692 
0693 static const struct mfd_cell asic3_cell_ds1wm = {
0694     .name          = "ds1wm",
0695     .enable        = ds1wm_enable,
0696     .disable       = ds1wm_disable,
0697     .platform_data = &ds1wm_pdata,
0698     .pdata_size    = sizeof(ds1wm_pdata),
0699     .num_resources = ARRAY_SIZE(ds1wm_resources),
0700     .resources     = ds1wm_resources,
0701 };
0702 
0703 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
0704 {
0705     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0706 
0707     tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
0708 }
0709 
0710 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
0711 {
0712     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0713 
0714     tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
0715 }
0716 
0717 static struct tmio_mmc_data asic3_mmc_data = {
0718     .hclk           = 24576000,
0719     .ocr_mask   = MMC_VDD_32_33 | MMC_VDD_33_34,
0720     .set_pwr        = asic3_mmc_pwr,
0721     .set_clk_div    = asic3_mmc_clk_div,
0722 };
0723 
0724 static struct resource asic3_mmc_resources[] = {
0725     DEFINE_RES_MEM(ASIC3_SD_CTRL_BASE, 0x400),
0726     DEFINE_RES_IRQ(0)
0727 };
0728 
0729 static int asic3_mmc_enable(struct platform_device *pdev)
0730 {
0731     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0732 
0733     /* Not sure if it must be done bit by bit, but leaving as-is */
0734     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0735                ASIC3_SDHWCTRL_LEVCD, 1);
0736     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0737                ASIC3_SDHWCTRL_LEVWP, 1);
0738     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0739                ASIC3_SDHWCTRL_SUSPEND, 0);
0740     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0741                ASIC3_SDHWCTRL_PCLR, 0);
0742 
0743     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
0744     /* CLK32 used for card detection and for interruption detection
0745      * when HCLK is stopped.
0746      */
0747     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
0748     usleep_range(1000, 5000);
0749 
0750     /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
0751     asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
0752         CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
0753 
0754     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
0755     asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
0756     usleep_range(1000, 5000);
0757 
0758     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
0759                ASIC3_EXTCF_SD_MEM_ENABLE, 1);
0760 
0761     /* Enable SD card slot 3.3V power supply */
0762     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0763                ASIC3_SDHWCTRL_SDPWR, 1);
0764 
0765     /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
0766     tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
0767                  ASIC3_SD_CTRL_BASE >> 1);
0768 
0769     return 0;
0770 }
0771 
0772 static int asic3_mmc_disable(struct platform_device *pdev)
0773 {
0774     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0775 
0776     /* Put in suspend mode */
0777     asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
0778                ASIC3_SDHWCTRL_SUSPEND, 1);
0779 
0780     /* Disable clocks */
0781     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
0782     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
0783     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
0784     asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
0785     return 0;
0786 }
0787 
0788 static const struct mfd_cell asic3_cell_mmc = {
0789     .name          = "tmio-mmc",
0790     .enable        = asic3_mmc_enable,
0791     .disable       = asic3_mmc_disable,
0792     .suspend       = asic3_mmc_disable,
0793     .resume        = asic3_mmc_enable,
0794     .platform_data = &asic3_mmc_data,
0795     .pdata_size    = sizeof(asic3_mmc_data),
0796     .num_resources = ARRAY_SIZE(asic3_mmc_resources),
0797     .resources     = asic3_mmc_resources,
0798 };
0799 
0800 static const int clock_ledn[ASIC3_NUM_LEDS] = {
0801     [0] = ASIC3_CLOCK_LED0,
0802     [1] = ASIC3_CLOCK_LED1,
0803     [2] = ASIC3_CLOCK_LED2,
0804 };
0805 
0806 static int asic3_leds_enable(struct platform_device *pdev)
0807 {
0808     const struct mfd_cell *cell = mfd_get_cell(pdev);
0809     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0810 
0811     asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
0812 
0813     return 0;
0814 }
0815 
0816 static int asic3_leds_disable(struct platform_device *pdev)
0817 {
0818     const struct mfd_cell *cell = mfd_get_cell(pdev);
0819     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0820 
0821     asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
0822 
0823     return 0;
0824 }
0825 
0826 static int asic3_leds_suspend(struct platform_device *pdev)
0827 {
0828     const struct mfd_cell *cell = mfd_get_cell(pdev);
0829     struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
0830 
0831     while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
0832         usleep_range(1000, 5000);
0833 
0834     asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
0835 
0836     return 0;
0837 }
0838 
0839 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
0840     [0] = {
0841         .name          = "leds-asic3",
0842         .id            = 0,
0843         .enable        = asic3_leds_enable,
0844         .disable       = asic3_leds_disable,
0845         .suspend       = asic3_leds_suspend,
0846         .resume        = asic3_leds_enable,
0847     },
0848     [1] = {
0849         .name          = "leds-asic3",
0850         .id            = 1,
0851         .enable        = asic3_leds_enable,
0852         .disable       = asic3_leds_disable,
0853         .suspend       = asic3_leds_suspend,
0854         .resume        = asic3_leds_enable,
0855     },
0856     [2] = {
0857         .name          = "leds-asic3",
0858         .id            = 2,
0859         .enable        = asic3_leds_enable,
0860         .disable       = asic3_leds_disable,
0861         .suspend       = asic3_leds_suspend,
0862         .resume        = asic3_leds_enable,
0863     },
0864 };
0865 
0866 static int __init asic3_mfd_probe(struct platform_device *pdev,
0867                   struct asic3_platform_data *pdata,
0868                   struct resource *mem)
0869 {
0870     struct asic3 *asic = platform_get_drvdata(pdev);
0871     struct resource *mem_sdio;
0872     int irq, ret;
0873 
0874     mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
0875     if (!mem_sdio)
0876         dev_dbg(asic->dev, "no SDIO MEM resource\n");
0877 
0878     irq = platform_get_irq(pdev, 1);
0879     if (irq < 0)
0880         dev_dbg(asic->dev, "no SDIO IRQ resource\n");
0881 
0882     /* DS1WM */
0883     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
0884                ASIC3_EXTCF_OWM_SMB, 0);
0885 
0886     ds1wm_resources[0].start >>= asic->bus_shift;
0887     ds1wm_resources[0].end   >>= asic->bus_shift;
0888 
0889     /* MMC */
0890     if (mem_sdio) {
0891         asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
0892                       asic->bus_shift) + mem_sdio->start,
0893                  ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
0894         if (!asic->tmio_cnf) {
0895             ret = -ENOMEM;
0896             dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
0897             goto out;
0898         }
0899     }
0900     asic3_mmc_resources[0].start >>= asic->bus_shift;
0901     asic3_mmc_resources[0].end   >>= asic->bus_shift;
0902 
0903     if (pdata->clock_rate) {
0904         ds1wm_pdata.clock_rate = pdata->clock_rate;
0905         ret = mfd_add_devices(&pdev->dev, pdev->id,
0906             &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
0907         if (ret < 0)
0908             goto out_unmap;
0909     }
0910 
0911     if (mem_sdio && (irq >= 0)) {
0912         ret = mfd_add_devices(&pdev->dev, pdev->id,
0913             &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
0914         if (ret < 0)
0915             goto out_unmap;
0916     }
0917 
0918     ret = 0;
0919     if (pdata->leds) {
0920         int i;
0921 
0922         for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
0923             asic3_cell_leds[i].platform_data = &pdata->leds[i];
0924             asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
0925         }
0926         ret = mfd_add_devices(&pdev->dev, 0,
0927             asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
0928     }
0929     return ret;
0930 
0931 out_unmap:
0932     if (asic->tmio_cnf)
0933         iounmap(asic->tmio_cnf);
0934 out:
0935     return ret;
0936 }
0937 
0938 static void asic3_mfd_remove(struct platform_device *pdev)
0939 {
0940     struct asic3 *asic = platform_get_drvdata(pdev);
0941 
0942     mfd_remove_devices(&pdev->dev);
0943     iounmap(asic->tmio_cnf);
0944 }
0945 
0946 /* Core */
0947 static int __init asic3_probe(struct platform_device *pdev)
0948 {
0949     struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
0950     struct asic3 *asic;
0951     struct resource *mem;
0952     unsigned long clksel;
0953     int ret = 0;
0954 
0955     asic = devm_kzalloc(&pdev->dev,
0956                 sizeof(struct asic3), GFP_KERNEL);
0957     if (!asic)
0958         return -ENOMEM;
0959 
0960     raw_spin_lock_init(&asic->lock);
0961     platform_set_drvdata(pdev, asic);
0962     asic->dev = &pdev->dev;
0963 
0964     mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0965     if (!mem) {
0966         dev_err(asic->dev, "no MEM resource\n");
0967         return -ENOMEM;
0968     }
0969 
0970     asic->mapping = ioremap(mem->start, resource_size(mem));
0971     if (!asic->mapping) {
0972         dev_err(asic->dev, "Couldn't ioremap\n");
0973         return -ENOMEM;
0974     }
0975 
0976     asic->irq_base = pdata->irq_base;
0977 
0978     /* calculate bus shift from mem resource */
0979     asic->bus_shift = 2 - (resource_size(mem) >> 12);
0980 
0981     clksel = 0;
0982     asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
0983 
0984     ret = asic3_irq_probe(pdev);
0985     if (ret < 0) {
0986         dev_err(asic->dev, "Couldn't probe IRQs\n");
0987         goto out_unmap;
0988     }
0989 
0990     asic->gpio.label = "asic3";
0991     asic->gpio.base = pdata->gpio_base;
0992     asic->gpio.ngpio = ASIC3_NUM_GPIOS;
0993     asic->gpio.get = asic3_gpio_get;
0994     asic->gpio.set = asic3_gpio_set;
0995     asic->gpio.direction_input = asic3_gpio_direction_input;
0996     asic->gpio.direction_output = asic3_gpio_direction_output;
0997     asic->gpio.to_irq = asic3_gpio_to_irq;
0998 
0999     ret = asic3_gpio_probe(pdev,
1000                    pdata->gpio_config,
1001                    pdata->gpio_config_num);
1002     if (ret < 0) {
1003         dev_err(asic->dev, "GPIO probe failed\n");
1004         goto out_irq;
1005     }
1006 
1007     /* Making a per-device copy is only needed for the
1008      * theoretical case of multiple ASIC3s on one board:
1009      */
1010     memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1011 
1012     asic3_mfd_probe(pdev, pdata, mem);
1013 
1014     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1015         (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1016 
1017     dev_info(asic->dev, "ASIC3 Core driver\n");
1018 
1019     return 0;
1020 
1021  out_irq:
1022     asic3_irq_remove(pdev);
1023 
1024  out_unmap:
1025     iounmap(asic->mapping);
1026 
1027     return ret;
1028 }
1029 
1030 static int asic3_remove(struct platform_device *pdev)
1031 {
1032     struct asic3 *asic = platform_get_drvdata(pdev);
1033 
1034     asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1035         (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1036 
1037     asic3_mfd_remove(pdev);
1038 
1039     asic3_gpio_remove(pdev);
1040 
1041     asic3_irq_remove(pdev);
1042 
1043     asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1044 
1045     iounmap(asic->mapping);
1046 
1047     return 0;
1048 }
1049 
1050 static void asic3_shutdown(struct platform_device *pdev)
1051 {
1052 }
1053 
1054 static struct platform_driver asic3_device_driver = {
1055     .driver     = {
1056         .name   = "asic3",
1057     },
1058     .remove     = asic3_remove,
1059     .shutdown   = asic3_shutdown,
1060 };
1061 
1062 static int __init asic3_init(void)
1063 {
1064     int retval = 0;
1065 
1066     retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1067 
1068     return retval;
1069 }
1070 
1071 subsys_initcall(asic3_init);
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