memstick/host/r592.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2010 - Maxim Levitsky
0004  * driver for Ricoh memstick readers
0005  */
0006
0007 #ifndef R592_H
0008
0009 #include <linux/memstick.h>
0010 #include <linux/spinlock.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/workqueue.h>
0013 #include <linux/kfifo.h>
0014 #include <linux/ctype.h>
0015
0016 /* write to this reg (number,len) triggers TPC execution */
0017 #define R592_TPC_EXEC           0x00
0018 #define R592_TPC_EXEC_LEN_SHIFT     16      /* Bits 16..25 are TPC len */
0019 #define R592_TPC_EXEC_BIG_FIFO      (1 << 26)   /* If bit 26 is set, large fifo is used (reg 48) */
0020 #define R592_TPC_EXEC_TPC_SHIFT     28      /* Bits 28..31 are the TPC number */
0021
0022
0023 /* Window for small TPC fifo (big endian)*/
0024 /* reads and writes always are done in  8 byte chunks */
0025 /* Not used in driver, because large fifo does better job */
0026 #define R592_SFIFO          0x08
0027
0028
0029 /* Status register (ms int, small fifo, IO)*/
0030 #define R592_STATUS         0x10
0031                             /* Parallel INT bits */
0032 #define R592_STATUS_P_CMDNACK       (1 << 16)   /* INT reg: NACK (parallel mode) */
0033 #define R592_STATUS_P_BREQ      (1 << 17)   /* INT reg: card ready (parallel mode)*/
0034 #define R592_STATUS_P_INTERR        (1 << 18)   /* INT reg: int error (parallel mode)*/
0035 #define R592_STATUS_P_CED       (1 << 19)   /* INT reg: command done (parallel mode) */
0036
0037                             /* Fifo status */
0038 #define R592_STATUS_SFIFO_FULL      (1 << 20)   /* Small Fifo almost full (last chunk is written) */
0039 #define R592_STATUS_SFIFO_EMPTY     (1 << 21)   /* Small Fifo empty */
0040
0041                             /* Error detection via CRC */
0042 #define R592_STATUS_SEND_ERR        (1 << 24)   /* Send failed */
0043 #define R592_STATUS_RECV_ERR        (1 << 25)   /* Receive failed */
0044
0045                             /* Card state */
0046 #define R592_STATUS_RDY         (1 << 28)   /* RDY signal received */
0047 #define R592_STATUS_CED         (1 << 29)   /* INT: Command done (serial mode)*/
0048 #define R592_STATUS_SFIFO_INPUT     (1 << 30)   /* Small fifo received data*/
0049
0050 #define R592_SFIFO_SIZE         32      /* total size of small fifo is 32 bytes */
0051 #define R592_SFIFO_PACKET       8       /* packet size of small fifo */
0052
0053 /* IO control */
0054 #define R592_IO             0x18
0055 #define R592_IO_16          (1 << 16)   /* Set by default, can be cleared */
0056 #define R592_IO_18          (1 << 18)   /* Set by default, can be cleared */
0057 #define R592_IO_SERIAL1         (1 << 20)   /* Set by default, can be cleared, (cleared on parallel) */
0058 #define R592_IO_22          (1 << 22)   /* Set by default, can be cleared */
0059 #define R592_IO_DIRECTION       (1 << 24)   /* TPC direction (1 write 0 read) */
0060 #define R592_IO_26          (1 << 26)   /* Set by default, can be cleared */
0061 #define R592_IO_SERIAL2         (1 << 30)   /* Set by default, can be cleared (cleared on parallel), serial doesn't work if unset */
0062 #define R592_IO_RESET           (1 << 31)   /* Reset, sets defaults*/
0063
0064
0065 /* Turns hardware on/off */
0066 #define R592_POWER          0x20        /* bits 0-7 writeable */
0067 #define R592_POWER_0            (1 << 0)    /* set on start, cleared on stop - must be set*/
0068 #define R592_POWER_1            (1 << 1)    /* set on start, cleared on stop - must be set*/
0069 #define R592_POWER_3            (1 << 3)    /* must be clear */
0070 #define R592_POWER_20           (1 << 5)    /* set before switch to parallel */
0071
0072 /* IO mode*/
0073 #define R592_IO_MODE            0x24
0074 #define R592_IO_MODE_SERIAL     1
0075 #define R592_IO_MODE_PARALLEL       3
0076
0077
0078 /* IRQ,card detection,large fifo (first word irq status, second enable) */
0079 /* IRQs are ACKed by clearing the bits */
0080 #define R592_REG_MSC            0x28
0081 #define R592_REG_MSC_PRSNT      (1 << 1)    /* card present (only status)*/
0082 #define R592_REG_MSC_IRQ_INSERT     (1 << 8)    /* detect insert / card insered */
0083 #define R592_REG_MSC_IRQ_REMOVE     (1 << 9)    /* detect removal / card removed */
0084 #define R592_REG_MSC_FIFO_EMPTY     (1 << 10)   /* fifo is empty */
0085 #define R592_REG_MSC_FIFO_DMA_DONE  (1 << 11)   /* dma enable / dma done */
0086
0087 #define R592_REG_MSC_FIFO_USER_ORN  (1 << 12)   /* set if software reads empty fifo (if R592_REG_MSC_FIFO_EMPTY is set) */
0088 #define R592_REG_MSC_FIFO_MISMATH   (1 << 13)   /* set if amount of data in fifo doesn't match amount in TPC */
0089 #define R592_REG_MSC_FIFO_DMA_ERR   (1 << 14)   /* IO failure */
0090 #define R592_REG_MSC_LED        (1 << 15)   /* clear to turn led off (only status)*/
0091
0092 #define DMA_IRQ_ACK_MASK \
0093     (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)
0094
0095 #define DMA_IRQ_EN_MASK (DMA_IRQ_ACK_MASK << 16)
0096
0097 #define IRQ_ALL_ACK_MASK 0x00007F00
0098 #define IRQ_ALL_EN_MASK (IRQ_ALL_ACK_MASK << 16)
0099
0100 /* DMA address for large FIFO read/writes*/
0101 #define R592_FIFO_DMA           0x2C
0102
0103 /* PIO access to large FIFO (512 bytes) (big endian)*/
0104 #define R592_FIFO_PIO           0x30
0105 #define R592_LFIFO_SIZE         512     /* large fifo size */
0106
0107
0108 /* large FIFO DMA settings */
0109 #define R592_FIFO_DMA_SETTINGS      0x34
0110 #define R592_FIFO_DMA_SETTINGS_EN   (1 << 0)    /* DMA enabled */
0111 #define R592_FIFO_DMA_SETTINGS_DIR  (1 << 1)    /* Dma direction (1 read, 0 write) */
0112 #define R592_FIFO_DMA_SETTINGS_CAP  (1 << 24)   /* Dma is aviable */
0113
0114 /* Maybe just an delay */
0115 /* Bits 17..19 are just number */
0116 /* bit 16 is set, then bit 20 is waited */
0117 /* time to wait is about 50 spins * 2 ^ (bits 17..19) */
0118 /* seems to be possible just to ignore */
0119 /* Probably debug register */
0120 #define R592_REG38          0x38
0121 #define R592_REG38_CHANGE       (1 << 16)   /* Start bit */
0122 #define R592_REG38_DONE         (1 << 20)   /* HW set this after the delay */
0123 #define R592_REG38_SHIFT        17
0124
0125 /* Debug register, written (0xABCDEF00) when error happens - not used*/
0126 #define R592_REG_3C         0x3C
0127
0128 struct r592_device {
0129     struct pci_dev *pci_dev;
0130     struct memstick_host    *host;      /* host backpointer */
0131     struct memstick_request *req;       /* current request */
0132
0133     /* Registers, IRQ */
0134     void __iomem *mmio;
0135     int irq;
0136     spinlock_t irq_lock;
0137     spinlock_t io_thread_lock;
0138     struct timer_list detect_timer;
0139
0140     struct task_struct *io_thread;
0141     bool parallel_mode;
0142
0143     DECLARE_KFIFO(pio_fifo, u8, sizeof(u32));
0144
0145     /* DMA area */
0146     int dma_capable;
0147     int dma_error;
0148     struct completion dma_done;
0149     void *dummy_dma_page;
0150     dma_addr_t dummy_dma_page_physical_address;
0151
0152 };
0153
0154 #define DRV_NAME "r592"
0155
0156
0157 #define message(format, ...) \
0158     printk(KERN_INFO DRV_NAME ": " format "\n", ## __VA_ARGS__)
0159
0160 #define __dbg(level, format, ...) \
0161     do { \
0162         if (debug >= level) \
0163             printk(KERN_DEBUG DRV_NAME \
0164                 ": " format "\n", ## __VA_ARGS__); \
0165     } while (0)
0166
0167
0168 #define dbg(format, ...)        __dbg(1, format, ## __VA_ARGS__)
0169 #define dbg_verbose(format, ...)    __dbg(2, format, ## __VA_ARGS__)
0170 #define dbg_reg(format, ...)        __dbg(3, format, ## __VA_ARGS__)
0171
0172 #endif