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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 - Maxim Levitsky
0004  * driver for Ricoh memstick readers
0005  */
0006 
0007 #include <linux/kernel.h>
0008 #include <linux/module.h>
0009 #include <linux/freezer.h>
0010 #include <linux/jiffies.h>
0011 #include <linux/interrupt.h>
0012 #include <linux/pci.h>
0013 #include <linux/pci_ids.h>
0014 #include <linux/delay.h>
0015 #include <linux/slab.h>
0016 #include <linux/kthread.h>
0017 #include <linux/sched.h>
0018 #include <linux/highmem.h>
0019 #include <asm/byteorder.h>
0020 #include <linux/swab.h>
0021 #include "r592.h"
0022 
0023 static bool r592_enable_dma = 1;
0024 static int debug;
0025 
0026 static const char *tpc_names[] = {
0027     "MS_TPC_READ_MG_STATUS",
0028     "MS_TPC_READ_LONG_DATA",
0029     "MS_TPC_READ_SHORT_DATA",
0030     "MS_TPC_READ_REG",
0031     "MS_TPC_READ_QUAD_DATA",
0032     "INVALID",
0033     "MS_TPC_GET_INT",
0034     "MS_TPC_SET_RW_REG_ADRS",
0035     "MS_TPC_EX_SET_CMD",
0036     "MS_TPC_WRITE_QUAD_DATA",
0037     "MS_TPC_WRITE_REG",
0038     "MS_TPC_WRITE_SHORT_DATA",
0039     "MS_TPC_WRITE_LONG_DATA",
0040     "MS_TPC_SET_CMD",
0041 };
0042 
0043 /**
0044  * memstick_debug_get_tpc_name - debug helper that returns string for
0045  * a TPC number
0046  */
0047 const char *memstick_debug_get_tpc_name(int tpc)
0048 {
0049     return tpc_names[tpc-1];
0050 }
0051 EXPORT_SYMBOL(memstick_debug_get_tpc_name);
0052 
0053 
0054 /* Read a register*/
0055 static inline u32 r592_read_reg(struct r592_device *dev, int address)
0056 {
0057     u32 value = readl(dev->mmio + address);
0058     dbg_reg("reg #%02d == 0x%08x", address, value);
0059     return value;
0060 }
0061 
0062 /* Write a register */
0063 static inline void r592_write_reg(struct r592_device *dev,
0064                             int address, u32 value)
0065 {
0066     dbg_reg("reg #%02d <- 0x%08x", address, value);
0067     writel(value, dev->mmio + address);
0068 }
0069 
0070 /* Reads a big endian DWORD register */
0071 static inline u32 r592_read_reg_raw_be(struct r592_device *dev, int address)
0072 {
0073     u32 value = __raw_readl(dev->mmio + address);
0074     dbg_reg("reg #%02d == 0x%08x", address, value);
0075     return be32_to_cpu(value);
0076 }
0077 
0078 /* Writes a big endian DWORD register */
0079 static inline void r592_write_reg_raw_be(struct r592_device *dev,
0080                             int address, u32 value)
0081 {
0082     dbg_reg("reg #%02d <- 0x%08x", address, value);
0083     __raw_writel(cpu_to_be32(value), dev->mmio + address);
0084 }
0085 
0086 /* Set specific bits in a register (little endian) */
0087 static inline void r592_set_reg_mask(struct r592_device *dev,
0088                             int address, u32 mask)
0089 {
0090     u32 reg = readl(dev->mmio + address);
0091     dbg_reg("reg #%02d |= 0x%08x (old =0x%08x)", address, mask, reg);
0092     writel(reg | mask , dev->mmio + address);
0093 }
0094 
0095 /* Clear specific bits in a register (little endian) */
0096 static inline void r592_clear_reg_mask(struct r592_device *dev,
0097                         int address, u32 mask)
0098 {
0099     u32 reg = readl(dev->mmio + address);
0100     dbg_reg("reg #%02d &= 0x%08x (old = 0x%08x, mask = 0x%08x)",
0101                         address, ~mask, reg, mask);
0102     writel(reg & ~mask, dev->mmio + address);
0103 }
0104 
0105 
0106 /* Wait for status bits while checking for errors */
0107 static int r592_wait_status(struct r592_device *dev, u32 mask, u32 wanted_mask)
0108 {
0109     unsigned long timeout = jiffies + msecs_to_jiffies(1000);
0110     u32 reg = r592_read_reg(dev, R592_STATUS);
0111 
0112     if ((reg & mask) == wanted_mask)
0113         return 0;
0114 
0115     while (time_before(jiffies, timeout)) {
0116 
0117         reg = r592_read_reg(dev, R592_STATUS);
0118 
0119         if ((reg & mask) == wanted_mask)
0120             return 0;
0121 
0122         if (reg & (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR))
0123             return -EIO;
0124 
0125         cpu_relax();
0126     }
0127     return -ETIME;
0128 }
0129 
0130 
0131 /* Enable/disable device */
0132 static int r592_enable_device(struct r592_device *dev, bool enable)
0133 {
0134     dbg("%sabling the device", enable ? "en" : "dis");
0135 
0136     if (enable) {
0137 
0138         /* Power up the card */
0139         r592_write_reg(dev, R592_POWER, R592_POWER_0 | R592_POWER_1);
0140 
0141         /* Perform a reset */
0142         r592_set_reg_mask(dev, R592_IO, R592_IO_RESET);
0143 
0144         msleep(100);
0145     } else
0146         /* Power down the card */
0147         r592_write_reg(dev, R592_POWER, 0);
0148 
0149     return 0;
0150 }
0151 
0152 /* Set serial/parallel mode */
0153 static int r592_set_mode(struct r592_device *dev, bool parallel_mode)
0154 {
0155     if (!parallel_mode) {
0156         dbg("switching to serial mode");
0157 
0158         /* Set serial mode */
0159         r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_SERIAL);
0160 
0161         r592_clear_reg_mask(dev, R592_POWER, R592_POWER_20);
0162 
0163     } else {
0164         dbg("switching to parallel mode");
0165 
0166         /* This setting should be set _before_ switch TPC */
0167         r592_set_reg_mask(dev, R592_POWER, R592_POWER_20);
0168 
0169         r592_clear_reg_mask(dev, R592_IO,
0170             R592_IO_SERIAL1 | R592_IO_SERIAL2);
0171 
0172         /* Set the parallel mode now */
0173         r592_write_reg(dev, R592_IO_MODE, R592_IO_MODE_PARALLEL);
0174     }
0175 
0176     dev->parallel_mode = parallel_mode;
0177     return 0;
0178 }
0179 
0180 /* Perform a controller reset without powering down the card */
0181 static void r592_host_reset(struct r592_device *dev)
0182 {
0183     r592_set_reg_mask(dev, R592_IO, R592_IO_RESET);
0184     msleep(100);
0185     r592_set_mode(dev, dev->parallel_mode);
0186 }
0187 
0188 #ifdef CONFIG_PM_SLEEP
0189 /* Disable all hardware interrupts */
0190 static void r592_clear_interrupts(struct r592_device *dev)
0191 {
0192     /* Disable & ACK all interrupts */
0193     r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_ACK_MASK);
0194     r592_clear_reg_mask(dev, R592_REG_MSC, IRQ_ALL_EN_MASK);
0195 }
0196 #endif
0197 
0198 /* Tests if there is an CRC error */
0199 static int r592_test_io_error(struct r592_device *dev)
0200 {
0201     if (!(r592_read_reg(dev, R592_STATUS) &
0202         (R592_STATUS_SEND_ERR | R592_STATUS_RECV_ERR)))
0203         return 0;
0204 
0205     return -EIO;
0206 }
0207 
0208 /* Ensure that FIFO is ready for use */
0209 static int r592_test_fifo_empty(struct r592_device *dev)
0210 {
0211     if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY)
0212         return 0;
0213 
0214     dbg("FIFO not ready, trying to reset the device");
0215     r592_host_reset(dev);
0216 
0217     if (r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_FIFO_EMPTY)
0218         return 0;
0219 
0220     message("FIFO still not ready, giving up");
0221     return -EIO;
0222 }
0223 
0224 /* Activates the DMA transfer from to FIFO */
0225 static void r592_start_dma(struct r592_device *dev, bool is_write)
0226 {
0227     unsigned long flags;
0228     u32 reg;
0229     spin_lock_irqsave(&dev->irq_lock, flags);
0230 
0231     /* Ack interrupts (just in case) + enable them */
0232     r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK);
0233     r592_set_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK);
0234 
0235     /* Set DMA address */
0236     r592_write_reg(dev, R592_FIFO_DMA, sg_dma_address(&dev->req->sg));
0237 
0238     /* Enable the DMA */
0239     reg = r592_read_reg(dev, R592_FIFO_DMA_SETTINGS);
0240     reg |= R592_FIFO_DMA_SETTINGS_EN;
0241 
0242     if (!is_write)
0243         reg |= R592_FIFO_DMA_SETTINGS_DIR;
0244     else
0245         reg &= ~R592_FIFO_DMA_SETTINGS_DIR;
0246     r592_write_reg(dev, R592_FIFO_DMA_SETTINGS, reg);
0247 
0248     spin_unlock_irqrestore(&dev->irq_lock, flags);
0249 }
0250 
0251 /* Cleanups DMA related settings */
0252 static void r592_stop_dma(struct r592_device *dev, int error)
0253 {
0254     r592_clear_reg_mask(dev, R592_FIFO_DMA_SETTINGS,
0255         R592_FIFO_DMA_SETTINGS_EN);
0256 
0257     /* This is only a precation */
0258     r592_write_reg(dev, R592_FIFO_DMA,
0259             dev->dummy_dma_page_physical_address);
0260 
0261     r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_EN_MASK);
0262     r592_clear_reg_mask(dev, R592_REG_MSC, DMA_IRQ_ACK_MASK);
0263     dev->dma_error = error;
0264 }
0265 
0266 /* Test if hardware supports DMA */
0267 static void r592_check_dma(struct r592_device *dev)
0268 {
0269     dev->dma_capable = r592_enable_dma &&
0270         (r592_read_reg(dev, R592_FIFO_DMA_SETTINGS) &
0271             R592_FIFO_DMA_SETTINGS_CAP);
0272 }
0273 
0274 /* Transfers fifo contents in/out using DMA */
0275 static int r592_transfer_fifo_dma(struct r592_device *dev)
0276 {
0277     int len, sg_count;
0278     bool is_write;
0279 
0280     if (!dev->dma_capable || !dev->req->long_data)
0281         return -EINVAL;
0282 
0283     len = dev->req->sg.length;
0284     is_write = dev->req->data_dir == WRITE;
0285 
0286     if (len != R592_LFIFO_SIZE)
0287         return -EINVAL;
0288 
0289     dbg_verbose("doing dma transfer");
0290 
0291     dev->dma_error = 0;
0292     reinit_completion(&dev->dma_done);
0293 
0294     /* TODO: hidden assumption about nenth beeing always 1 */
0295     sg_count = dma_map_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ?
0296                   DMA_TO_DEVICE : DMA_FROM_DEVICE);
0297 
0298     if (sg_count != 1 || sg_dma_len(&dev->req->sg) < R592_LFIFO_SIZE) {
0299         message("problem in dma_map_sg");
0300         return -EIO;
0301     }
0302 
0303     r592_start_dma(dev, is_write);
0304 
0305     /* Wait for DMA completion */
0306     if (!wait_for_completion_timeout(
0307             &dev->dma_done, msecs_to_jiffies(1000))) {
0308         message("DMA timeout");
0309         r592_stop_dma(dev, -ETIMEDOUT);
0310     }
0311 
0312     dma_unmap_sg(&dev->pci_dev->dev, &dev->req->sg, 1, is_write ?
0313              DMA_TO_DEVICE : DMA_FROM_DEVICE);
0314 
0315     return dev->dma_error;
0316 }
0317 
0318 /*
0319  * Writes the FIFO in 4 byte chunks.
0320  * If length isn't 4 byte aligned, rest of the data if put to a fifo
0321  * to be written later
0322  * Use r592_flush_fifo_write to flush that fifo when writing for the
0323  * last time
0324  */
0325 static void r592_write_fifo_pio(struct r592_device *dev,
0326                     unsigned char *buffer, int len)
0327 {
0328     /* flush spill from former write */
0329     if (!kfifo_is_empty(&dev->pio_fifo)) {
0330 
0331         u8 tmp[4] = {0};
0332         int copy_len = kfifo_in(&dev->pio_fifo, buffer, len);
0333 
0334         if (!kfifo_is_full(&dev->pio_fifo))
0335             return;
0336         len -= copy_len;
0337         buffer += copy_len;
0338 
0339         copy_len = kfifo_out(&dev->pio_fifo, tmp, 4);
0340         WARN_ON(copy_len != 4);
0341         r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)tmp);
0342     }
0343 
0344     WARN_ON(!kfifo_is_empty(&dev->pio_fifo));
0345 
0346     /* write full dwords */
0347     while (len >= 4) {
0348         r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer);
0349         buffer += 4;
0350         len -= 4;
0351     }
0352 
0353     /* put remaining bytes to the spill */
0354     if (len)
0355         kfifo_in(&dev->pio_fifo, buffer, len);
0356 }
0357 
0358 /* Flushes the temporary FIFO used to make aligned DWORD writes */
0359 static void r592_flush_fifo_write(struct r592_device *dev)
0360 {
0361     int ret;
0362     u8 buffer[4] = { 0 };
0363 
0364     if (kfifo_is_empty(&dev->pio_fifo))
0365         return;
0366 
0367     ret = kfifo_out(&dev->pio_fifo, buffer, 4);
0368     /* intentionally ignore __must_check return code */
0369     (void)ret;
0370     r592_write_reg_raw_be(dev, R592_FIFO_PIO, *(u32 *)buffer);
0371 }
0372 
0373 /*
0374  * Read a fifo in 4 bytes chunks.
0375  * If input doesn't fit the buffer, it places bytes of last dword in spill
0376  * buffer, so that they don't get lost on last read, just throw these away.
0377  */
0378 static void r592_read_fifo_pio(struct r592_device *dev,
0379                         unsigned char *buffer, int len)
0380 {
0381     u8 tmp[4];
0382 
0383     /* Read from last spill */
0384     if (!kfifo_is_empty(&dev->pio_fifo)) {
0385         int bytes_copied =
0386             kfifo_out(&dev->pio_fifo, buffer, min(4, len));
0387         buffer += bytes_copied;
0388         len -= bytes_copied;
0389 
0390         if (!kfifo_is_empty(&dev->pio_fifo))
0391             return;
0392     }
0393 
0394     /* Reads dwords from FIFO */
0395     while (len >= 4) {
0396         *(u32 *)buffer = r592_read_reg_raw_be(dev, R592_FIFO_PIO);
0397         buffer += 4;
0398         len -= 4;
0399     }
0400 
0401     if (len) {
0402         *(u32 *)tmp = r592_read_reg_raw_be(dev, R592_FIFO_PIO);
0403         kfifo_in(&dev->pio_fifo, tmp, 4);
0404         len -= kfifo_out(&dev->pio_fifo, buffer, len);
0405     }
0406 
0407     WARN_ON(len);
0408     return;
0409 }
0410 
0411 /* Transfers actual data using PIO. */
0412 static int r592_transfer_fifo_pio(struct r592_device *dev)
0413 {
0414     unsigned long flags;
0415 
0416     bool is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS;
0417     struct sg_mapping_iter miter;
0418 
0419     kfifo_reset(&dev->pio_fifo);
0420 
0421     if (!dev->req->long_data) {
0422         if (is_write) {
0423             r592_write_fifo_pio(dev, dev->req->data,
0424                             dev->req->data_len);
0425             r592_flush_fifo_write(dev);
0426         } else
0427             r592_read_fifo_pio(dev, dev->req->data,
0428                             dev->req->data_len);
0429         return 0;
0430     }
0431 
0432     local_irq_save(flags);
0433     sg_miter_start(&miter, &dev->req->sg, 1, SG_MITER_ATOMIC |
0434         (is_write ? SG_MITER_FROM_SG : SG_MITER_TO_SG));
0435 
0436     /* Do the transfer fifo<->memory*/
0437     while (sg_miter_next(&miter))
0438         if (is_write)
0439             r592_write_fifo_pio(dev, miter.addr, miter.length);
0440         else
0441             r592_read_fifo_pio(dev, miter.addr, miter.length);
0442 
0443 
0444     /* Write last few non aligned bytes*/
0445     if (is_write)
0446         r592_flush_fifo_write(dev);
0447 
0448     sg_miter_stop(&miter);
0449     local_irq_restore(flags);
0450     return 0;
0451 }
0452 
0453 /* Executes one TPC (data is read/written from small or large fifo) */
0454 static void r592_execute_tpc(struct r592_device *dev)
0455 {
0456     bool is_write;
0457     int len, error;
0458     u32 status, reg;
0459 
0460     if (!dev->req) {
0461         message("BUG: tpc execution without request!");
0462         return;
0463     }
0464 
0465     is_write = dev->req->tpc >= MS_TPC_SET_RW_REG_ADRS;
0466     len = dev->req->long_data ?
0467         dev->req->sg.length : dev->req->data_len;
0468 
0469     /* Ensure that FIFO can hold the input data */
0470     if (len > R592_LFIFO_SIZE) {
0471         message("IO: hardware doesn't support TPCs longer that 512");
0472         error = -ENOSYS;
0473         goto out;
0474     }
0475 
0476     if (!(r592_read_reg(dev, R592_REG_MSC) & R592_REG_MSC_PRSNT)) {
0477         dbg("IO: refusing to send TPC because card is absent");
0478         error = -ENODEV;
0479         goto out;
0480     }
0481 
0482     dbg("IO: executing %s LEN=%d",
0483             memstick_debug_get_tpc_name(dev->req->tpc), len);
0484 
0485     /* Set IO direction */
0486     if (is_write)
0487         r592_set_reg_mask(dev, R592_IO, R592_IO_DIRECTION);
0488     else
0489         r592_clear_reg_mask(dev, R592_IO, R592_IO_DIRECTION);
0490 
0491 
0492     error = r592_test_fifo_empty(dev);
0493     if (error)
0494         goto out;
0495 
0496     /* Transfer write data */
0497     if (is_write) {
0498         error = r592_transfer_fifo_dma(dev);
0499         if (error == -EINVAL)
0500             error = r592_transfer_fifo_pio(dev);
0501     }
0502 
0503     if (error)
0504         goto out;
0505 
0506     /* Trigger the TPC */
0507     reg = (len << R592_TPC_EXEC_LEN_SHIFT) |
0508         (dev->req->tpc << R592_TPC_EXEC_TPC_SHIFT) |
0509             R592_TPC_EXEC_BIG_FIFO;
0510 
0511     r592_write_reg(dev, R592_TPC_EXEC, reg);
0512 
0513     /* Wait for TPC completion */
0514     status = R592_STATUS_RDY;
0515     if (dev->req->need_card_int)
0516         status |= R592_STATUS_CED;
0517 
0518     error = r592_wait_status(dev, status, status);
0519     if (error) {
0520         message("card didn't respond");
0521         goto out;
0522     }
0523 
0524     /* Test IO errors */
0525     error = r592_test_io_error(dev);
0526     if (error) {
0527         dbg("IO error");
0528         goto out;
0529     }
0530 
0531     /* Read data from FIFO */
0532     if (!is_write) {
0533         error = r592_transfer_fifo_dma(dev);
0534         if (error == -EINVAL)
0535             error = r592_transfer_fifo_pio(dev);
0536     }
0537 
0538     /* read INT reg. This can be shortened with shifts, but that way
0539         its more readable */
0540     if (dev->parallel_mode && dev->req->need_card_int) {
0541 
0542         dev->req->int_reg = 0;
0543         status = r592_read_reg(dev, R592_STATUS);
0544 
0545         if (status & R592_STATUS_P_CMDNACK)
0546             dev->req->int_reg |= MEMSTICK_INT_CMDNAK;
0547         if (status & R592_STATUS_P_BREQ)
0548             dev->req->int_reg |= MEMSTICK_INT_BREQ;
0549         if (status & R592_STATUS_P_INTERR)
0550             dev->req->int_reg |= MEMSTICK_INT_ERR;
0551         if (status & R592_STATUS_P_CED)
0552             dev->req->int_reg |= MEMSTICK_INT_CED;
0553     }
0554 
0555     if (error)
0556         dbg("FIFO read error");
0557 out:
0558     dev->req->error = error;
0559     r592_clear_reg_mask(dev, R592_REG_MSC, R592_REG_MSC_LED);
0560     return;
0561 }
0562 
0563 /* Main request processing thread */
0564 static int r592_process_thread(void *data)
0565 {
0566     int error;
0567     struct r592_device *dev = (struct r592_device *)data;
0568     unsigned long flags;
0569 
0570     while (!kthread_should_stop()) {
0571         spin_lock_irqsave(&dev->io_thread_lock, flags);
0572         set_current_state(TASK_INTERRUPTIBLE);
0573         error = memstick_next_req(dev->host, &dev->req);
0574         spin_unlock_irqrestore(&dev->io_thread_lock, flags);
0575 
0576         if (error) {
0577             if (error == -ENXIO || error == -EAGAIN) {
0578                 dbg_verbose("IO: done IO, sleeping");
0579             } else {
0580                 dbg("IO: unknown error from "
0581                     "memstick_next_req %d", error);
0582             }
0583 
0584             if (kthread_should_stop())
0585                 set_current_state(TASK_RUNNING);
0586 
0587             schedule();
0588         } else {
0589             set_current_state(TASK_RUNNING);
0590             r592_execute_tpc(dev);
0591         }
0592     }
0593     return 0;
0594 }
0595 
0596 /* Reprogram chip to detect change in card state */
0597 /* eg, if card is detected, arm it to detect removal, and vice versa */
0598 static void r592_update_card_detect(struct r592_device *dev)
0599 {
0600     u32 reg = r592_read_reg(dev, R592_REG_MSC);
0601     bool card_detected = reg & R592_REG_MSC_PRSNT;
0602 
0603     dbg("update card detect. card state: %s", card_detected ?
0604         "present" : "absent");
0605 
0606     reg &= ~((R592_REG_MSC_IRQ_REMOVE | R592_REG_MSC_IRQ_INSERT) << 16);
0607 
0608     if (card_detected)
0609         reg |= (R592_REG_MSC_IRQ_REMOVE << 16);
0610     else
0611         reg |= (R592_REG_MSC_IRQ_INSERT << 16);
0612 
0613     r592_write_reg(dev, R592_REG_MSC, reg);
0614 }
0615 
0616 /* Timer routine that fires 1 second after last card detection event, */
0617 static void r592_detect_timer(struct timer_list *t)
0618 {
0619     struct r592_device *dev = from_timer(dev, t, detect_timer);
0620     r592_update_card_detect(dev);
0621     memstick_detect_change(dev->host);
0622 }
0623 
0624 /* Interrupt handler */
0625 static irqreturn_t r592_irq(int irq, void *data)
0626 {
0627     struct r592_device *dev = (struct r592_device *)data;
0628     irqreturn_t ret = IRQ_NONE;
0629     u32 reg;
0630     u16 irq_enable, irq_status;
0631     unsigned long flags;
0632     int error;
0633 
0634     spin_lock_irqsave(&dev->irq_lock, flags);
0635 
0636     reg = r592_read_reg(dev, R592_REG_MSC);
0637     irq_enable = reg >> 16;
0638     irq_status = reg & 0xFFFF;
0639 
0640     /* Ack the interrupts */
0641     reg &= ~irq_status;
0642     r592_write_reg(dev, R592_REG_MSC, reg);
0643 
0644     /* Get the IRQ status minus bits that aren't enabled */
0645     irq_status &= (irq_enable);
0646 
0647     /* Due to limitation of memstick core, we don't look at bits that
0648         indicate that card was removed/inserted and/or present */
0649     if (irq_status & (R592_REG_MSC_IRQ_INSERT | R592_REG_MSC_IRQ_REMOVE)) {
0650 
0651         bool card_was_added = irq_status & R592_REG_MSC_IRQ_INSERT;
0652         ret = IRQ_HANDLED;
0653 
0654         message("IRQ: card %s", card_was_added ? "added" : "removed");
0655 
0656         mod_timer(&dev->detect_timer,
0657             jiffies + msecs_to_jiffies(card_was_added ? 500 : 50));
0658     }
0659 
0660     if (irq_status &
0661         (R592_REG_MSC_FIFO_DMA_DONE | R592_REG_MSC_FIFO_DMA_ERR)) {
0662         ret = IRQ_HANDLED;
0663 
0664         if (irq_status & R592_REG_MSC_FIFO_DMA_ERR) {
0665             message("IRQ: DMA error");
0666             error = -EIO;
0667         } else {
0668             dbg_verbose("IRQ: dma done");
0669             error = 0;
0670         }
0671 
0672         r592_stop_dma(dev, error);
0673         complete(&dev->dma_done);
0674     }
0675 
0676     spin_unlock_irqrestore(&dev->irq_lock, flags);
0677     return ret;
0678 }
0679 
0680 /* External inteface: set settings */
0681 static int r592_set_param(struct memstick_host *host,
0682             enum memstick_param param, int value)
0683 {
0684     struct r592_device *dev = memstick_priv(host);
0685 
0686     switch (param) {
0687     case MEMSTICK_POWER:
0688         switch (value) {
0689         case MEMSTICK_POWER_ON:
0690             return r592_enable_device(dev, true);
0691         case MEMSTICK_POWER_OFF:
0692             return r592_enable_device(dev, false);
0693         default:
0694             return -EINVAL;
0695         }
0696     case MEMSTICK_INTERFACE:
0697         switch (value) {
0698         case MEMSTICK_SERIAL:
0699             return r592_set_mode(dev, 0);
0700         case MEMSTICK_PAR4:
0701             return r592_set_mode(dev, 1);
0702         default:
0703             return -EINVAL;
0704         }
0705     default:
0706         return -EINVAL;
0707     }
0708 }
0709 
0710 /* External interface: submit requests */
0711 static void r592_submit_req(struct memstick_host *host)
0712 {
0713     struct r592_device *dev = memstick_priv(host);
0714     unsigned long flags;
0715 
0716     if (dev->req)
0717         return;
0718 
0719     spin_lock_irqsave(&dev->io_thread_lock, flags);
0720     if (wake_up_process(dev->io_thread))
0721         dbg_verbose("IO thread woken to process requests");
0722     spin_unlock_irqrestore(&dev->io_thread_lock, flags);
0723 }
0724 
0725 static const struct pci_device_id r592_pci_id_tbl[] = {
0726 
0727     { PCI_VDEVICE(RICOH, 0x0592), },
0728     { },
0729 };
0730 
0731 /* Main entry */
0732 static int r592_probe(struct pci_dev *pdev, const struct pci_device_id *id)
0733 {
0734     int error = -ENOMEM;
0735     struct memstick_host *host;
0736     struct r592_device *dev;
0737 
0738     /* Allocate memory */
0739     host = memstick_alloc_host(sizeof(struct r592_device), &pdev->dev);
0740     if (!host)
0741         goto error1;
0742 
0743     dev = memstick_priv(host);
0744     dev->host = host;
0745     dev->pci_dev = pdev;
0746     pci_set_drvdata(pdev, dev);
0747 
0748     /* pci initialization */
0749     error = pci_enable_device(pdev);
0750     if (error)
0751         goto error2;
0752 
0753     pci_set_master(pdev);
0754     error = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
0755     if (error)
0756         goto error3;
0757 
0758     error = pci_request_regions(pdev, DRV_NAME);
0759     if (error)
0760         goto error3;
0761 
0762     dev->mmio = pci_ioremap_bar(pdev, 0);
0763     if (!dev->mmio) {
0764         error = -ENOMEM;
0765         goto error4;
0766     }
0767 
0768     dev->irq = pdev->irq;
0769     spin_lock_init(&dev->irq_lock);
0770     spin_lock_init(&dev->io_thread_lock);
0771     init_completion(&dev->dma_done);
0772     INIT_KFIFO(dev->pio_fifo);
0773     timer_setup(&dev->detect_timer, r592_detect_timer, 0);
0774 
0775     /* Host initialization */
0776     host->caps = MEMSTICK_CAP_PAR4;
0777     host->request = r592_submit_req;
0778     host->set_param = r592_set_param;
0779     r592_check_dma(dev);
0780 
0781     dev->io_thread = kthread_run(r592_process_thread, dev, "r592_io");
0782     if (IS_ERR(dev->io_thread)) {
0783         error = PTR_ERR(dev->io_thread);
0784         goto error5;
0785     }
0786 
0787     /* This is just a precation, so don't fail */
0788     dev->dummy_dma_page = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
0789         &dev->dummy_dma_page_physical_address, GFP_KERNEL);
0790     r592_stop_dma(dev , 0);
0791 
0792     error = request_irq(dev->irq, &r592_irq, IRQF_SHARED,
0793               DRV_NAME, dev);
0794     if (error)
0795         goto error6;
0796 
0797     r592_update_card_detect(dev);
0798     error = memstick_add_host(host);
0799     if (error)
0800         goto error7;
0801 
0802     message("driver successfully loaded");
0803     return 0;
0804 error7:
0805     free_irq(dev->irq, dev);
0806 error6:
0807     if (dev->dummy_dma_page)
0808         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->dummy_dma_page,
0809             dev->dummy_dma_page_physical_address);
0810 
0811     kthread_stop(dev->io_thread);
0812 error5:
0813     iounmap(dev->mmio);
0814 error4:
0815     pci_release_regions(pdev);
0816 error3:
0817     pci_disable_device(pdev);
0818 error2:
0819     memstick_free_host(host);
0820 error1:
0821     return error;
0822 }
0823 
0824 static void r592_remove(struct pci_dev *pdev)
0825 {
0826     int error = 0;
0827     struct r592_device *dev = pci_get_drvdata(pdev);
0828 
0829     /* Stop the processing thread.
0830     That ensures that we won't take any more requests */
0831     kthread_stop(dev->io_thread);
0832 
0833     r592_enable_device(dev, false);
0834 
0835     while (!error && dev->req) {
0836         dev->req->error = -ETIME;
0837         error = memstick_next_req(dev->host, &dev->req);
0838     }
0839     memstick_remove_host(dev->host);
0840 
0841     if (dev->dummy_dma_page)
0842         dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->dummy_dma_page,
0843             dev->dummy_dma_page_physical_address);
0844 
0845     free_irq(dev->irq, dev);
0846     iounmap(dev->mmio);
0847     pci_release_regions(pdev);
0848     pci_disable_device(pdev);
0849     memstick_free_host(dev->host);
0850 }
0851 
0852 #ifdef CONFIG_PM_SLEEP
0853 static int r592_suspend(struct device *core_dev)
0854 {
0855     struct r592_device *dev = dev_get_drvdata(core_dev);
0856 
0857     r592_clear_interrupts(dev);
0858     memstick_suspend_host(dev->host);
0859     del_timer_sync(&dev->detect_timer);
0860     return 0;
0861 }
0862 
0863 static int r592_resume(struct device *core_dev)
0864 {
0865     struct r592_device *dev = dev_get_drvdata(core_dev);
0866 
0867     r592_clear_interrupts(dev);
0868     r592_enable_device(dev, false);
0869     memstick_resume_host(dev->host);
0870     r592_update_card_detect(dev);
0871     return 0;
0872 }
0873 #endif
0874 
0875 static SIMPLE_DEV_PM_OPS(r592_pm_ops, r592_suspend, r592_resume);
0876 
0877 MODULE_DEVICE_TABLE(pci, r592_pci_id_tbl);
0878 
0879 static struct pci_driver r592_pci_driver = {
0880     .name       = DRV_NAME,
0881     .id_table   = r592_pci_id_tbl,
0882     .probe      = r592_probe,
0883     .remove     = r592_remove,
0884     .driver.pm  = &r592_pm_ops,
0885 };
0886 
0887 module_pci_driver(r592_pci_driver);
0888 
0889 module_param_named(enable_dma, r592_enable_dma, bool, S_IRUGO);
0890 MODULE_PARM_DESC(enable_dma, "Enable usage of the DMA (default)");
0891 module_param(debug, int, S_IRUGO | S_IWUSR);
0892 MODULE_PARM_DESC(debug, "Debug level (0-3)");
0893 
0894 MODULE_LICENSE("GPL");
0895 MODULE_AUTHOR("Maxim Levitsky <maximlevitsky@gmail.com>");
0896 MODULE_DESCRIPTION("Ricoh R5C592 Memstick/Memstick PRO card reader driver");
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