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0006 #include <dt-bindings/memory/tegra210-mc.h>
0007
0008 #include "mc.h"
0009
0010 static const struct tegra_mc_client tegra210_mc_clients[] = {
0011 {
0012 .id = 0x00,
0013 .name = "ptcr",
0014 .swgroup = TEGRA_SWGROUP_PTC,
0015 }, {
0016 .id = 0x01,
0017 .name = "display0a",
0018 .swgroup = TEGRA_SWGROUP_DC,
0019 .regs = {
0020 .smmu = {
0021 .reg = 0x228,
0022 .bit = 1,
0023 },
0024 .la = {
0025 .reg = 0x2e8,
0026 .shift = 0,
0027 .mask = 0xff,
0028 .def = 0x1e,
0029 },
0030 },
0031 }, {
0032 .id = 0x02,
0033 .name = "display0ab",
0034 .swgroup = TEGRA_SWGROUP_DCB,
0035 .regs = {
0036 .smmu = {
0037 .reg = 0x228,
0038 .bit = 2,
0039 },
0040 .la = {
0041 .reg = 0x2f4,
0042 .shift = 0,
0043 .mask = 0xff,
0044 .def = 0x1e,
0045 },
0046 },
0047 }, {
0048 .id = 0x03,
0049 .name = "display0b",
0050 .swgroup = TEGRA_SWGROUP_DC,
0051 .regs = {
0052 .smmu = {
0053 .reg = 0x228,
0054 .bit = 3,
0055 },
0056 .la = {
0057 .reg = 0x2e8,
0058 .shift = 16,
0059 .mask = 0xff,
0060 .def = 0x1e,
0061 },
0062 },
0063 }, {
0064 .id = 0x04,
0065 .name = "display0bb",
0066 .swgroup = TEGRA_SWGROUP_DCB,
0067 .regs = {
0068 .smmu = {
0069 .reg = 0x228,
0070 .bit = 4,
0071 },
0072 .la = {
0073 .reg = 0x2f4,
0074 .shift = 16,
0075 .mask = 0xff,
0076 .def = 0x1e,
0077 },
0078 },
0079 }, {
0080 .id = 0x05,
0081 .name = "display0c",
0082 .swgroup = TEGRA_SWGROUP_DC,
0083 .regs = {
0084 .smmu = {
0085 .reg = 0x228,
0086 .bit = 5,
0087 },
0088 .la = {
0089 .reg = 0x2ec,
0090 .shift = 0,
0091 .mask = 0xff,
0092 .def = 0x1e,
0093 },
0094 },
0095 }, {
0096 .id = 0x06,
0097 .name = "display0cb",
0098 .swgroup = TEGRA_SWGROUP_DCB,
0099 .regs = {
0100 .smmu = {
0101 .reg = 0x228,
0102 .bit = 6,
0103 },
0104 .la = {
0105 .reg = 0x2f8,
0106 .shift = 0,
0107 .mask = 0xff,
0108 .def = 0x1e,
0109 },
0110 },
0111 }, {
0112 .id = 0x0e,
0113 .name = "afir",
0114 .swgroup = TEGRA_SWGROUP_AFI,
0115 .regs = {
0116 .smmu = {
0117 .reg = 0x228,
0118 .bit = 14,
0119 },
0120 .la = {
0121 .reg = 0x2e0,
0122 .shift = 0,
0123 .mask = 0xff,
0124 .def = 0x2e,
0125 },
0126 },
0127 }, {
0128 .id = 0x0f,
0129 .name = "avpcarm7r",
0130 .swgroup = TEGRA_SWGROUP_AVPC,
0131 .regs = {
0132 .smmu = {
0133 .reg = 0x228,
0134 .bit = 15,
0135 },
0136 .la = {
0137 .reg = 0x2e4,
0138 .shift = 0,
0139 .mask = 0xff,
0140 .def = 0x04,
0141 },
0142 },
0143 }, {
0144 .id = 0x10,
0145 .name = "displayhc",
0146 .swgroup = TEGRA_SWGROUP_DC,
0147 .regs = {
0148 .smmu = {
0149 .reg = 0x228,
0150 .bit = 16,
0151 },
0152 .la = {
0153 .reg = 0x2f0,
0154 .shift = 0,
0155 .mask = 0xff,
0156 .def = 0x1e,
0157 },
0158 },
0159 }, {
0160 .id = 0x11,
0161 .name = "displayhcb",
0162 .swgroup = TEGRA_SWGROUP_DCB,
0163 .regs = {
0164 .smmu = {
0165 .reg = 0x228,
0166 .bit = 17,
0167 },
0168 .la = {
0169 .reg = 0x2fc,
0170 .shift = 0,
0171 .mask = 0xff,
0172 .def = 0x1e,
0173 },
0174 },
0175 }, {
0176 .id = 0x15,
0177 .name = "hdar",
0178 .swgroup = TEGRA_SWGROUP_HDA,
0179 .regs = {
0180 .smmu = {
0181 .reg = 0x228,
0182 .bit = 21,
0183 },
0184 .la = {
0185 .reg = 0x318,
0186 .shift = 0,
0187 .mask = 0xff,
0188 .def = 0x24,
0189 },
0190 },
0191 }, {
0192 .id = 0x16,
0193 .name = "host1xdmar",
0194 .swgroup = TEGRA_SWGROUP_HC,
0195 .regs = {
0196 .smmu = {
0197 .reg = 0x228,
0198 .bit = 22,
0199 },
0200 .la = {
0201 .reg = 0x310,
0202 .shift = 0,
0203 .mask = 0xff,
0204 .def = 0x1e,
0205 },
0206 },
0207 }, {
0208 .id = 0x17,
0209 .name = "host1xr",
0210 .swgroup = TEGRA_SWGROUP_HC,
0211 .regs = {
0212 .smmu = {
0213 .reg = 0x228,
0214 .bit = 23,
0215 },
0216 .la = {
0217 .reg = 0x310,
0218 .shift = 16,
0219 .mask = 0xff,
0220 .def = 0x50,
0221 },
0222 },
0223 }, {
0224 .id = 0x1c,
0225 .name = "nvencsrd",
0226 .swgroup = TEGRA_SWGROUP_NVENC,
0227 .regs = {
0228 .smmu = {
0229 .reg = 0x228,
0230 .bit = 28,
0231 },
0232 .la = {
0233 .reg = 0x328,
0234 .shift = 0,
0235 .mask = 0xff,
0236 .def = 0x23,
0237 },
0238 },
0239 }, {
0240 .id = 0x1d,
0241 .name = "ppcsahbdmar",
0242 .swgroup = TEGRA_SWGROUP_PPCS,
0243 .regs = {
0244 .smmu = {
0245 .reg = 0x228,
0246 .bit = 29,
0247 },
0248 .la = {
0249 .reg = 0x344,
0250 .shift = 0,
0251 .mask = 0xff,
0252 .def = 0x49,
0253 },
0254 },
0255 }, {
0256 .id = 0x1e,
0257 .name = "ppcsahbslvr",
0258 .swgroup = TEGRA_SWGROUP_PPCS,
0259 .regs = {
0260 .smmu = {
0261 .reg = 0x228,
0262 .bit = 30,
0263 },
0264 .la = {
0265 .reg = 0x344,
0266 .shift = 16,
0267 .mask = 0xff,
0268 .def = 0x1a,
0269 },
0270 },
0271 }, {
0272 .id = 0x1f,
0273 .name = "satar",
0274 .swgroup = TEGRA_SWGROUP_SATA,
0275 .regs = {
0276 .smmu = {
0277 .reg = 0x228,
0278 .bit = 31,
0279 },
0280 .la = {
0281 .reg = 0x350,
0282 .shift = 0,
0283 .mask = 0xff,
0284 .def = 0x65,
0285 },
0286 },
0287 }, {
0288 .id = 0x27,
0289 .name = "mpcorer",
0290 .swgroup = TEGRA_SWGROUP_MPCORE,
0291 .regs = {
0292 .la = {
0293 .reg = 0x320,
0294 .shift = 0,
0295 .mask = 0xff,
0296 .def = 0x04,
0297 },
0298 },
0299 }, {
0300 .id = 0x2b,
0301 .name = "nvencswr",
0302 .swgroup = TEGRA_SWGROUP_NVENC,
0303 .regs = {
0304 .smmu = {
0305 .reg = 0x22c,
0306 .bit = 11,
0307 },
0308 .la = {
0309 .reg = 0x328,
0310 .shift = 16,
0311 .mask = 0xff,
0312 .def = 0x80,
0313 },
0314 },
0315 }, {
0316 .id = 0x31,
0317 .name = "afiw",
0318 .swgroup = TEGRA_SWGROUP_AFI,
0319 .regs = {
0320 .smmu = {
0321 .reg = 0x22c,
0322 .bit = 17,
0323 },
0324 .la = {
0325 .reg = 0x2e0,
0326 .shift = 16,
0327 .mask = 0xff,
0328 .def = 0x80,
0329 },
0330 },
0331 }, {
0332 .id = 0x32,
0333 .name = "avpcarm7w",
0334 .swgroup = TEGRA_SWGROUP_AVPC,
0335 .regs = {
0336 .smmu = {
0337 .reg = 0x22c,
0338 .bit = 18,
0339 },
0340 .la = {
0341 .reg = 0x2e4,
0342 .shift = 16,
0343 .mask = 0xff,
0344 .def = 0x80,
0345 },
0346 },
0347 }, {
0348 .id = 0x35,
0349 .name = "hdaw",
0350 .swgroup = TEGRA_SWGROUP_HDA,
0351 .regs = {
0352 .smmu = {
0353 .reg = 0x22c,
0354 .bit = 21,
0355 },
0356 .la = {
0357 .reg = 0x318,
0358 .shift = 16,
0359 .mask = 0xff,
0360 .def = 0x80,
0361 },
0362 },
0363 }, {
0364 .id = 0x36,
0365 .name = "host1xw",
0366 .swgroup = TEGRA_SWGROUP_HC,
0367 .regs = {
0368 .smmu = {
0369 .reg = 0x22c,
0370 .bit = 22,
0371 },
0372 .la = {
0373 .reg = 0x314,
0374 .shift = 0,
0375 .mask = 0xff,
0376 .def = 0x80,
0377 },
0378 },
0379 }, {
0380 .id = 0x39,
0381 .name = "mpcorew",
0382 .swgroup = TEGRA_SWGROUP_MPCORE,
0383 .regs = {
0384 .la = {
0385 .reg = 0x320,
0386 .shift = 16,
0387 .mask = 0xff,
0388 .def = 0x80,
0389 },
0390 },
0391 }, {
0392 .id = 0x3b,
0393 .name = "ppcsahbdmaw",
0394 .swgroup = TEGRA_SWGROUP_PPCS,
0395 .regs = {
0396 .smmu = {
0397 .reg = 0x22c,
0398 .bit = 27,
0399 },
0400 .la = {
0401 .reg = 0x348,
0402 .shift = 0,
0403 .mask = 0xff,
0404 .def = 0x80,
0405 },
0406 },
0407 }, {
0408 .id = 0x3c,
0409 .name = "ppcsahbslvw",
0410 .swgroup = TEGRA_SWGROUP_PPCS,
0411 .regs = {
0412 .smmu = {
0413 .reg = 0x22c,
0414 .bit = 28,
0415 },
0416 .la = {
0417 .reg = 0x348,
0418 .shift = 16,
0419 .mask = 0xff,
0420 .def = 0x80,
0421 },
0422 },
0423 }, {
0424 .id = 0x3d,
0425 .name = "sataw",
0426 .swgroup = TEGRA_SWGROUP_SATA,
0427 .regs = {
0428 .smmu = {
0429 .reg = 0x22c,
0430 .bit = 29,
0431 },
0432 .la = {
0433 .reg = 0x350,
0434 .shift = 16,
0435 .mask = 0xff,
0436 .def = 0x80,
0437 },
0438 },
0439 }, {
0440 .id = 0x44,
0441 .name = "ispra",
0442 .swgroup = TEGRA_SWGROUP_ISP2,
0443 .regs = {
0444 .smmu = {
0445 .reg = 0x230,
0446 .bit = 4,
0447 },
0448 .la = {
0449 .reg = 0x370,
0450 .shift = 0,
0451 .mask = 0xff,
0452 .def = 0x18,
0453 },
0454 },
0455 }, {
0456 .id = 0x46,
0457 .name = "ispwa",
0458 .swgroup = TEGRA_SWGROUP_ISP2,
0459 .regs = {
0460 .smmu = {
0461 .reg = 0x230,
0462 .bit = 6,
0463 },
0464 .la = {
0465 .reg = 0x374,
0466 .shift = 0,
0467 .mask = 0xff,
0468 .def = 0x80,
0469 },
0470 },
0471 }, {
0472 .id = 0x47,
0473 .name = "ispwb",
0474 .swgroup = TEGRA_SWGROUP_ISP2,
0475 .regs = {
0476 .smmu = {
0477 .reg = 0x230,
0478 .bit = 7,
0479 },
0480 .la = {
0481 .reg = 0x374,
0482 .shift = 16,
0483 .mask = 0xff,
0484 .def = 0x80,
0485 },
0486 },
0487 }, {
0488 .id = 0x4a,
0489 .name = "xusb_hostr",
0490 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0491 .regs = {
0492 .smmu = {
0493 .reg = 0x230,
0494 .bit = 10,
0495 },
0496 .la = {
0497 .reg = 0x37c,
0498 .shift = 0,
0499 .mask = 0xff,
0500 .def = 0x7a,
0501 },
0502 },
0503 }, {
0504 .id = 0x4b,
0505 .name = "xusb_hostw",
0506 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0507 .regs = {
0508 .smmu = {
0509 .reg = 0x230,
0510 .bit = 11,
0511 },
0512 .la = {
0513 .reg = 0x37c,
0514 .shift = 16,
0515 .mask = 0xff,
0516 .def = 0x80,
0517 },
0518 },
0519 }, {
0520 .id = 0x4c,
0521 .name = "xusb_devr",
0522 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0523 .regs = {
0524 .smmu = {
0525 .reg = 0x230,
0526 .bit = 12,
0527 },
0528 .la = {
0529 .reg = 0x380,
0530 .shift = 0,
0531 .mask = 0xff,
0532 .def = 0x39,
0533 },
0534 },
0535 }, {
0536 .id = 0x4d,
0537 .name = "xusb_devw",
0538 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0539 .regs = {
0540 .smmu = {
0541 .reg = 0x230,
0542 .bit = 13,
0543 },
0544 .la = {
0545 .reg = 0x380,
0546 .shift = 16,
0547 .mask = 0xff,
0548 .def = 0x80,
0549 },
0550 },
0551 }, {
0552 .id = 0x4e,
0553 .name = "isprab",
0554 .swgroup = TEGRA_SWGROUP_ISP2B,
0555 .regs = {
0556 .smmu = {
0557 .reg = 0x230,
0558 .bit = 14,
0559 },
0560 .la = {
0561 .reg = 0x384,
0562 .shift = 0,
0563 .mask = 0xff,
0564 .def = 0x18,
0565 },
0566 },
0567 }, {
0568 .id = 0x50,
0569 .name = "ispwab",
0570 .swgroup = TEGRA_SWGROUP_ISP2B,
0571 .regs = {
0572 .smmu = {
0573 .reg = 0x230,
0574 .bit = 16,
0575 },
0576 .la = {
0577 .reg = 0x388,
0578 .shift = 0,
0579 .mask = 0xff,
0580 .def = 0x80,
0581 },
0582 },
0583 }, {
0584 .id = 0x51,
0585 .name = "ispwbb",
0586 .swgroup = TEGRA_SWGROUP_ISP2B,
0587 .regs = {
0588 .smmu = {
0589 .reg = 0x230,
0590 .bit = 17,
0591 },
0592 .la = {
0593 .reg = 0x388,
0594 .shift = 16,
0595 .mask = 0xff,
0596 .def = 0x80,
0597 },
0598 },
0599 }, {
0600 .id = 0x54,
0601 .name = "tsecsrd",
0602 .swgroup = TEGRA_SWGROUP_TSEC,
0603 .regs = {
0604 .smmu = {
0605 .reg = 0x230,
0606 .bit = 20,
0607 },
0608 .la = {
0609 .reg = 0x390,
0610 .shift = 0,
0611 .mask = 0xff,
0612 .def = 0x9b,
0613 },
0614 },
0615 }, {
0616 .id = 0x55,
0617 .name = "tsecswr",
0618 .swgroup = TEGRA_SWGROUP_TSEC,
0619 .regs = {
0620 .smmu = {
0621 .reg = 0x230,
0622 .bit = 21,
0623 },
0624 .la = {
0625 .reg = 0x390,
0626 .shift = 16,
0627 .mask = 0xff,
0628 .def = 0x80,
0629 },
0630 },
0631 }, {
0632 .id = 0x56,
0633 .name = "a9avpscr",
0634 .swgroup = TEGRA_SWGROUP_A9AVP,
0635 .regs = {
0636 .smmu = {
0637 .reg = 0x230,
0638 .bit = 22,
0639 },
0640 .la = {
0641 .reg = 0x3a4,
0642 .shift = 0,
0643 .mask = 0xff,
0644 .def = 0x04,
0645 },
0646 },
0647 }, {
0648 .id = 0x57,
0649 .name = "a9avpscw",
0650 .swgroup = TEGRA_SWGROUP_A9AVP,
0651 .regs = {
0652 .smmu = {
0653 .reg = 0x230,
0654 .bit = 23,
0655 },
0656 .la = {
0657 .reg = 0x3a4,
0658 .shift = 16,
0659 .mask = 0xff,
0660 .def = 0x80,
0661 },
0662 },
0663 }, {
0664 .id = 0x58,
0665 .name = "gpusrd",
0666 .swgroup = TEGRA_SWGROUP_GPU,
0667 .regs = {
0668 .smmu = {
0669
0670 .reg = 0x230,
0671 .bit = 24,
0672 },
0673 .la = {
0674 .reg = 0x3c8,
0675 .shift = 0,
0676 .mask = 0xff,
0677 .def = 0x1a,
0678 },
0679 },
0680 }, {
0681 .id = 0x59,
0682 .name = "gpuswr",
0683 .swgroup = TEGRA_SWGROUP_GPU,
0684 .regs = {
0685 .smmu = {
0686
0687 .reg = 0x230,
0688 .bit = 25,
0689 },
0690 .la = {
0691 .reg = 0x3c8,
0692 .shift = 16,
0693 .mask = 0xff,
0694 .def = 0x80,
0695 },
0696 },
0697 }, {
0698 .id = 0x5a,
0699 .name = "displayt",
0700 .swgroup = TEGRA_SWGROUP_DC,
0701 .regs = {
0702 .smmu = {
0703 .reg = 0x230,
0704 .bit = 26,
0705 },
0706 .la = {
0707 .reg = 0x2f0,
0708 .shift = 16,
0709 .mask = 0xff,
0710 .def = 0x1e,
0711 },
0712 },
0713 }, {
0714 .id = 0x60,
0715 .name = "sdmmcra",
0716 .swgroup = TEGRA_SWGROUP_SDMMC1A,
0717 .regs = {
0718 .smmu = {
0719 .reg = 0x234,
0720 .bit = 0,
0721 },
0722 .la = {
0723 .reg = 0x3b8,
0724 .shift = 0,
0725 .mask = 0xff,
0726 .def = 0x49,
0727 },
0728 },
0729 }, {
0730 .id = 0x61,
0731 .name = "sdmmcraa",
0732 .swgroup = TEGRA_SWGROUP_SDMMC2A,
0733 .regs = {
0734 .smmu = {
0735 .reg = 0x234,
0736 .bit = 1,
0737 },
0738 .la = {
0739 .reg = 0x3bc,
0740 .shift = 0,
0741 .mask = 0xff,
0742 .def = 0x5a,
0743 },
0744 },
0745 }, {
0746 .id = 0x62,
0747 .name = "sdmmcr",
0748 .swgroup = TEGRA_SWGROUP_SDMMC3A,
0749 .regs = {
0750 .smmu = {
0751 .reg = 0x234,
0752 .bit = 2,
0753 },
0754 .la = {
0755 .reg = 0x3c0,
0756 .shift = 0,
0757 .mask = 0xff,
0758 .def = 0x49,
0759 },
0760 },
0761 }, {
0762 .id = 0x63,
0763 .swgroup = TEGRA_SWGROUP_SDMMC4A,
0764 .name = "sdmmcrab",
0765 .regs = {
0766 .smmu = {
0767 .reg = 0x234,
0768 .bit = 3,
0769 },
0770 .la = {
0771 .reg = 0x3c4,
0772 .shift = 0,
0773 .mask = 0xff,
0774 .def = 0x5a,
0775 },
0776 },
0777 }, {
0778 .id = 0x64,
0779 .name = "sdmmcwa",
0780 .swgroup = TEGRA_SWGROUP_SDMMC1A,
0781 .regs = {
0782 .smmu = {
0783 .reg = 0x234,
0784 .bit = 4,
0785 },
0786 .la = {
0787 .reg = 0x3b8,
0788 .shift = 16,
0789 .mask = 0xff,
0790 .def = 0x80,
0791 },
0792 },
0793 }, {
0794 .id = 0x65,
0795 .name = "sdmmcwaa",
0796 .swgroup = TEGRA_SWGROUP_SDMMC2A,
0797 .regs = {
0798 .smmu = {
0799 .reg = 0x234,
0800 .bit = 5,
0801 },
0802 .la = {
0803 .reg = 0x3bc,
0804 .shift = 16,
0805 .mask = 0xff,
0806 .def = 0x80,
0807 },
0808 },
0809 }, {
0810 .id = 0x66,
0811 .name = "sdmmcw",
0812 .swgroup = TEGRA_SWGROUP_SDMMC3A,
0813 .regs = {
0814 .smmu = {
0815 .reg = 0x234,
0816 .bit = 6,
0817 },
0818 .la = {
0819 .reg = 0x3c0,
0820 .shift = 16,
0821 .mask = 0xff,
0822 .def = 0x80,
0823 },
0824 },
0825 }, {
0826 .id = 0x67,
0827 .name = "sdmmcwab",
0828 .swgroup = TEGRA_SWGROUP_SDMMC4A,
0829 .regs = {
0830 .smmu = {
0831 .reg = 0x234,
0832 .bit = 7,
0833 },
0834 .la = {
0835 .reg = 0x3c4,
0836 .shift = 16,
0837 .mask = 0xff,
0838 .def = 0x80,
0839 },
0840 },
0841 }, {
0842 .id = 0x6c,
0843 .name = "vicsrd",
0844 .swgroup = TEGRA_SWGROUP_VIC,
0845 .regs = {
0846 .smmu = {
0847 .reg = 0x234,
0848 .bit = 12,
0849 },
0850 .la = {
0851 .reg = 0x394,
0852 .shift = 0,
0853 .mask = 0xff,
0854 .def = 0x1a,
0855 },
0856 },
0857 }, {
0858 .id = 0x6d,
0859 .name = "vicswr",
0860 .swgroup = TEGRA_SWGROUP_VIC,
0861 .regs = {
0862 .smmu = {
0863 .reg = 0x234,
0864 .bit = 13,
0865 },
0866 .la = {
0867 .reg = 0x394,
0868 .shift = 16,
0869 .mask = 0xff,
0870 .def = 0x80,
0871 },
0872 },
0873 }, {
0874 .id = 0x72,
0875 .name = "viw",
0876 .swgroup = TEGRA_SWGROUP_VI,
0877 .regs = {
0878 .smmu = {
0879 .reg = 0x234,
0880 .bit = 18,
0881 },
0882 .la = {
0883 .reg = 0x398,
0884 .shift = 0,
0885 .mask = 0xff,
0886 .def = 0x80,
0887 },
0888 },
0889 }, {
0890 .id = 0x73,
0891 .name = "displayd",
0892 .swgroup = TEGRA_SWGROUP_DC,
0893 .regs = {
0894 .smmu = {
0895 .reg = 0x234,
0896 .bit = 19,
0897 },
0898 .la = {
0899 .reg = 0x3c8,
0900 .shift = 0,
0901 .mask = 0xff,
0902 .def = 0x50,
0903 },
0904 },
0905 }, {
0906 .id = 0x78,
0907 .name = "nvdecsrd",
0908 .swgroup = TEGRA_SWGROUP_NVDEC,
0909 .regs = {
0910 .smmu = {
0911 .reg = 0x234,
0912 .bit = 24,
0913 },
0914 .la = {
0915 .reg = 0x3d8,
0916 .shift = 0,
0917 .mask = 0xff,
0918 .def = 0x23,
0919 },
0920 },
0921 }, {
0922 .id = 0x79,
0923 .name = "nvdecswr",
0924 .swgroup = TEGRA_SWGROUP_NVDEC,
0925 .regs = {
0926 .smmu = {
0927 .reg = 0x234,
0928 .bit = 25,
0929 },
0930 .la = {
0931 .reg = 0x3d8,
0932 .shift = 16,
0933 .mask = 0xff,
0934 .def = 0x80,
0935 },
0936 },
0937 }, {
0938 .id = 0x7a,
0939 .name = "aper",
0940 .swgroup = TEGRA_SWGROUP_APE,
0941 .regs = {
0942 .smmu = {
0943 .reg = 0x234,
0944 .bit = 26,
0945 },
0946 .la = {
0947 .reg = 0x3dc,
0948 .shift = 0,
0949 .mask = 0xff,
0950 .def = 0xff,
0951 },
0952 },
0953 }, {
0954 .id = 0x7b,
0955 .name = "apew",
0956 .swgroup = TEGRA_SWGROUP_APE,
0957 .regs = {
0958 .smmu = {
0959 .reg = 0x234,
0960 .bit = 27,
0961 },
0962 .la = {
0963 .reg = 0x3dc,
0964 .shift = 16,
0965 .mask = 0xff,
0966 .def = 0x80,
0967 },
0968 },
0969 }, {
0970 .id = 0x7e,
0971 .name = "nvjpgsrd",
0972 .swgroup = TEGRA_SWGROUP_NVJPG,
0973 .regs = {
0974 .smmu = {
0975 .reg = 0x234,
0976 .bit = 30,
0977 },
0978 .la = {
0979 .reg = 0x3e4,
0980 .shift = 0,
0981 .mask = 0xff,
0982 .def = 0x23,
0983 },
0984 },
0985 }, {
0986 .id = 0x7f,
0987 .name = "nvjpgswr",
0988 .swgroup = TEGRA_SWGROUP_NVJPG,
0989 .regs = {
0990 .smmu = {
0991 .reg = 0x234,
0992 .bit = 31,
0993 },
0994 .la = {
0995 .reg = 0x3e4,
0996 .shift = 16,
0997 .mask = 0xff,
0998 .def = 0x80,
0999 },
1000 },
1001 }, {
1002 .id = 0x80,
1003 .name = "sesrd",
1004 .swgroup = TEGRA_SWGROUP_SE,
1005 .regs = {
1006 .smmu = {
1007 .reg = 0xb98,
1008 .bit = 0,
1009 },
1010 .la = {
1011 .reg = 0x3e0,
1012 .shift = 0,
1013 .mask = 0xff,
1014 .def = 0x2e,
1015 },
1016 },
1017 }, {
1018 .id = 0x81,
1019 .name = "seswr",
1020 .swgroup = TEGRA_SWGROUP_SE,
1021 .regs = {
1022 .smmu = {
1023 .reg = 0xb98,
1024 .bit = 1,
1025 },
1026 .la = {
1027 .reg = 0x3e0,
1028 .shift = 16,
1029 .mask = 0xff,
1030 .def = 0x80,
1031 },
1032 },
1033 }, {
1034 .id = 0x82,
1035 .name = "axiapr",
1036 .swgroup = TEGRA_SWGROUP_AXIAP,
1037 .regs = {
1038 .smmu = {
1039 .reg = 0xb98,
1040 .bit = 2,
1041 },
1042 .la = {
1043 .reg = 0x3a0,
1044 .shift = 0,
1045 .mask = 0xff,
1046 .def = 0xff,
1047 },
1048 },
1049 }, {
1050 .id = 0x83,
1051 .name = "axiapw",
1052 .swgroup = TEGRA_SWGROUP_AXIAP,
1053 .regs = {
1054 .smmu = {
1055 .reg = 0xb98,
1056 .bit = 3,
1057 },
1058 .la = {
1059 .reg = 0x3a0,
1060 .shift = 16,
1061 .mask = 0xff,
1062 .def = 0x80,
1063 },
1064 },
1065 }, {
1066 .id = 0x84,
1067 .name = "etrr",
1068 .swgroup = TEGRA_SWGROUP_ETR,
1069 .regs = {
1070 .smmu = {
1071 .reg = 0xb98,
1072 .bit = 4,
1073 },
1074 .la = {
1075 .reg = 0x3ec,
1076 .shift = 0,
1077 .mask = 0xff,
1078 .def = 0xff,
1079 },
1080 },
1081 }, {
1082 .id = 0x85,
1083 .name = "etrw",
1084 .swgroup = TEGRA_SWGROUP_ETR,
1085 .regs = {
1086 .smmu = {
1087 .reg = 0xb98,
1088 .bit = 5,
1089 },
1090 .la = {
1091 .reg = 0x3ec,
1092 .shift = 16,
1093 .mask = 0xff,
1094 .def = 0x80,
1095 },
1096 },
1097 }, {
1098 .id = 0x86,
1099 .name = "tsecsrdb",
1100 .swgroup = TEGRA_SWGROUP_TSECB,
1101 .regs = {
1102 .smmu = {
1103 .reg = 0xb98,
1104 .bit = 6,
1105 },
1106 .la = {
1107 .reg = 0x3f0,
1108 .shift = 0,
1109 .mask = 0xff,
1110 .def = 0x9b,
1111 },
1112 },
1113 }, {
1114 .id = 0x87,
1115 .name = "tsecswrb",
1116 .swgroup = TEGRA_SWGROUP_TSECB,
1117 .regs = {
1118 .smmu = {
1119 .reg = 0xb98,
1120 .bit = 7,
1121 },
1122 .la = {
1123 .reg = 0x3f0,
1124 .shift = 16,
1125 .mask = 0xff,
1126 .def = 0x80,
1127 },
1128 },
1129 }, {
1130 .id = 0x88,
1131 .name = "gpusrd2",
1132 .swgroup = TEGRA_SWGROUP_GPU,
1133 .regs = {
1134 .smmu = {
1135
1136 .reg = 0xb98,
1137 .bit = 8,
1138 },
1139 .la = {
1140 .reg = 0x3e8,
1141 .shift = 0,
1142 .mask = 0xff,
1143 .def = 0x1a,
1144 },
1145 },
1146 }, {
1147 .id = 0x89,
1148 .name = "gpuswr2",
1149 .swgroup = TEGRA_SWGROUP_GPU,
1150 .regs = {
1151 .smmu = {
1152
1153 .reg = 0xb98,
1154 .bit = 9,
1155 },
1156 .la = {
1157 .reg = 0x3e8,
1158 .shift = 16,
1159 .mask = 0xff,
1160 .def = 0x80,
1161 },
1162 },
1163 },
1164 };
1165
1166 static const struct tegra_smmu_swgroup tegra210_swgroups[] = {
1167 { .name = "afi", .swgroup = TEGRA_SWGROUP_AFI, .reg = 0x238 },
1168 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1169 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1170 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1171 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1172 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1173 { .name = "isp2", .swgroup = TEGRA_SWGROUP_ISP2, .reg = 0x258 },
1174 { .name = "nvenc", .swgroup = TEGRA_SWGROUP_NVENC, .reg = 0x264 },
1175 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1176 { .name = "nv2", .swgroup = TEGRA_SWGROUP_NV2, .reg = 0x26c },
1177 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1178 { .name = "sata", .swgroup = TEGRA_SWGROUP_SATA, .reg = 0x274 },
1179 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1180 { .name = "vic", .swgroup = TEGRA_SWGROUP_VIC, .reg = 0x284 },
1181 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1182 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1183 { .name = "a9avp", .swgroup = TEGRA_SWGROUP_A9AVP, .reg = 0x290 },
1184 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1185 { .name = "ppcs1", .swgroup = TEGRA_SWGROUP_PPCS1, .reg = 0x298 },
1186 { .name = "dc1", .swgroup = TEGRA_SWGROUP_DC1, .reg = 0xa88 },
1187 { .name = "sdmmc1a", .swgroup = TEGRA_SWGROUP_SDMMC1A, .reg = 0xa94 },
1188 { .name = "sdmmc2a", .swgroup = TEGRA_SWGROUP_SDMMC2A, .reg = 0xa98 },
1189 { .name = "sdmmc3a", .swgroup = TEGRA_SWGROUP_SDMMC3A, .reg = 0xa9c },
1190 { .name = "sdmmc4a", .swgroup = TEGRA_SWGROUP_SDMMC4A, .reg = 0xaa0 },
1191 { .name = "isp2b", .swgroup = TEGRA_SWGROUP_ISP2B, .reg = 0xaa4 },
1192 { .name = "gpu", .swgroup = TEGRA_SWGROUP_GPU, .reg = 0xaac },
1193 { .name = "ppcs2", .swgroup = TEGRA_SWGROUP_PPCS2, .reg = 0xab0 },
1194 { .name = "nvdec", .swgroup = TEGRA_SWGROUP_NVDEC, .reg = 0xab4 },
1195 { .name = "ape", .swgroup = TEGRA_SWGROUP_APE, .reg = 0xab8 },
1196 { .name = "se", .swgroup = TEGRA_SWGROUP_SE, .reg = 0xabc },
1197 { .name = "nvjpg", .swgroup = TEGRA_SWGROUP_NVJPG, .reg = 0xac0 },
1198 { .name = "hc1", .swgroup = TEGRA_SWGROUP_HC1, .reg = 0xac4 },
1199 { .name = "se1", .swgroup = TEGRA_SWGROUP_SE1, .reg = 0xac8 },
1200 { .name = "axiap", .swgroup = TEGRA_SWGROUP_AXIAP, .reg = 0xacc },
1201 { .name = "etr", .swgroup = TEGRA_SWGROUP_ETR, .reg = 0xad0 },
1202 { .name = "tsecb", .swgroup = TEGRA_SWGROUP_TSECB, .reg = 0xad4 },
1203 { .name = "tsec1", .swgroup = TEGRA_SWGROUP_TSEC1, .reg = 0xad8 },
1204 { .name = "tsecb1", .swgroup = TEGRA_SWGROUP_TSECB1, .reg = 0xadc },
1205 { .name = "nvdec1", .swgroup = TEGRA_SWGROUP_NVDEC1, .reg = 0xae0 },
1206 };
1207
1208 static const unsigned int tegra210_group_display[] = {
1209 TEGRA_SWGROUP_DC,
1210 TEGRA_SWGROUP_DCB,
1211 };
1212
1213 static const struct tegra_smmu_group_soc tegra210_groups[] = {
1214 {
1215 .name = "display",
1216 .swgroups = tegra210_group_display,
1217 .num_swgroups = ARRAY_SIZE(tegra210_group_display),
1218 },
1219 };
1220
1221 static const struct tegra_smmu_soc tegra210_smmu_soc = {
1222 .clients = tegra210_mc_clients,
1223 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1224 .swgroups = tegra210_swgroups,
1225 .num_swgroups = ARRAY_SIZE(tegra210_swgroups),
1226 .groups = tegra210_groups,
1227 .num_groups = ARRAY_SIZE(tegra210_groups),
1228 .supports_round_robin_arbitration = true,
1229 .supports_request_limit = true,
1230 .num_tlb_lines = 48,
1231 .num_asids = 128,
1232 };
1233
1234 #define TEGRA210_MC_RESET(_name, _control, _status, _bit) \
1235 { \
1236 .name = #_name, \
1237 .id = TEGRA210_MC_RESET_##_name, \
1238 .control = _control, \
1239 .status = _status, \
1240 .bit = _bit, \
1241 }
1242
1243 static const struct tegra_mc_reset tegra210_mc_resets[] = {
1244 TEGRA210_MC_RESET(AFI, 0x200, 0x204, 0),
1245 TEGRA210_MC_RESET(AVPC, 0x200, 0x204, 1),
1246 TEGRA210_MC_RESET(DC, 0x200, 0x204, 2),
1247 TEGRA210_MC_RESET(DCB, 0x200, 0x204, 3),
1248 TEGRA210_MC_RESET(HC, 0x200, 0x204, 6),
1249 TEGRA210_MC_RESET(HDA, 0x200, 0x204, 7),
1250 TEGRA210_MC_RESET(ISP2, 0x200, 0x204, 8),
1251 TEGRA210_MC_RESET(MPCORE, 0x200, 0x204, 9),
1252 TEGRA210_MC_RESET(NVENC, 0x200, 0x204, 11),
1253 TEGRA210_MC_RESET(PPCS, 0x200, 0x204, 14),
1254 TEGRA210_MC_RESET(SATA, 0x200, 0x204, 15),
1255 TEGRA210_MC_RESET(VI, 0x200, 0x204, 17),
1256 TEGRA210_MC_RESET(VIC, 0x200, 0x204, 18),
1257 TEGRA210_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1258 TEGRA210_MC_RESET(XUSB_DEV, 0x200, 0x204, 20),
1259 TEGRA210_MC_RESET(A9AVP, 0x200, 0x204, 21),
1260 TEGRA210_MC_RESET(TSEC, 0x200, 0x204, 22),
1261 TEGRA210_MC_RESET(SDMMC1, 0x200, 0x204, 29),
1262 TEGRA210_MC_RESET(SDMMC2, 0x200, 0x204, 30),
1263 TEGRA210_MC_RESET(SDMMC3, 0x200, 0x204, 31),
1264 TEGRA210_MC_RESET(SDMMC4, 0x970, 0x974, 0),
1265 TEGRA210_MC_RESET(ISP2B, 0x970, 0x974, 1),
1266 TEGRA210_MC_RESET(GPU, 0x970, 0x974, 2),
1267 TEGRA210_MC_RESET(NVDEC, 0x970, 0x974, 5),
1268 TEGRA210_MC_RESET(APE, 0x970, 0x974, 6),
1269 TEGRA210_MC_RESET(SE, 0x970, 0x974, 7),
1270 TEGRA210_MC_RESET(NVJPG, 0x970, 0x974, 8),
1271 TEGRA210_MC_RESET(AXIAP, 0x970, 0x974, 11),
1272 TEGRA210_MC_RESET(ETR, 0x970, 0x974, 12),
1273 TEGRA210_MC_RESET(TSECB, 0x970, 0x974, 13),
1274 };
1275
1276 const struct tegra_mc_soc tegra210_mc_soc = {
1277 .clients = tegra210_mc_clients,
1278 .num_clients = ARRAY_SIZE(tegra210_mc_clients),
1279 .num_address_bits = 34,
1280 .atom_size = 64,
1281 .client_id_mask = 0xff,
1282 .smmu = &tegra210_smmu_soc,
1283 .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1284 MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1285 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1286 .reset_ops = &tegra_mc_reset_ops_common,
1287 .resets = tegra210_mc_resets,
1288 .num_resets = ARRAY_SIZE(tegra210_mc_resets),
1289 .ops = &tegra30_mc_ops,
1290 };
