memory/tegra/tegra210-mc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015-2020, NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef TEGRA210_MC_H
0007 #define TEGRA210_MC_H
0008
0009 #include "mc.h"
0010
0011 /* register definitions */
0012 #define MC_LATENCY_ALLOWANCE_AVPC_0             0x2e4
0013 #define MC_LATENCY_ALLOWANCE_HC_0               0x310
0014 #define MC_LATENCY_ALLOWANCE_HC_1               0x314
0015 #define MC_LATENCY_ALLOWANCE_MPCORE_0               0x320
0016 #define MC_LATENCY_ALLOWANCE_NVENC_0                0x328
0017 #define MC_LATENCY_ALLOWANCE_PPCS_0             0x344
0018 #define MC_LATENCY_ALLOWANCE_PPCS_1             0x348
0019 #define MC_LATENCY_ALLOWANCE_ISP2_0             0x370
0020 #define MC_LATENCY_ALLOWANCE_ISP2_1             0x374
0021 #define MC_LATENCY_ALLOWANCE_XUSB_0             0x37c
0022 #define MC_LATENCY_ALLOWANCE_XUSB_1             0x380
0023 #define MC_LATENCY_ALLOWANCE_TSEC_0             0x390
0024 #define MC_LATENCY_ALLOWANCE_VIC_0              0x394
0025 #define MC_LATENCY_ALLOWANCE_VI2_0              0x398
0026 #define MC_LATENCY_ALLOWANCE_GPU_0              0x3ac
0027 #define MC_LATENCY_ALLOWANCE_SDMMCA_0               0x3b8
0028 #define MC_LATENCY_ALLOWANCE_SDMMCAA_0              0x3bc
0029 #define MC_LATENCY_ALLOWANCE_SDMMC_0                0x3c0
0030 #define MC_LATENCY_ALLOWANCE_SDMMCAB_0              0x3c4
0031 #define MC_LATENCY_ALLOWANCE_GPU2_0             0x3e8
0032 #define MC_LATENCY_ALLOWANCE_NVDEC_0                0x3d8
0033 #define MC_MLL_MPCORER_PTSA_RATE                0x44c
0034 #define MC_FTOP_PTSA_RATE                   0x50c
0035 #define MC_EMEM_ARB_TIMING_RFCPB                0x6c0
0036 #define MC_EMEM_ARB_TIMING_CCDMW                0x6c4
0037 #define MC_EMEM_ARB_REFPB_HP_CTRL               0x6f0
0038 #define MC_EMEM_ARB_REFPB_BANK_CTRL             0x6f4
0039 #define MC_PTSA_GRANT_DECREMENT                 0x960
0040 #define MC_EMEM_ARB_DHYST_CTRL                  0xbcc
0041 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_0            0xbd0
0042 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_1            0xbd4
0043 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_2            0xbd8
0044 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_3            0xbdc
0045 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_4            0xbe0
0046 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_5            0xbe4
0047 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_6            0xbe8
0048 #define MC_EMEM_ARB_DHYST_TIMEOUT_UTIL_7            0xbec
0049
0050 #endif