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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Tegra20 External Memory Controller driver
0004  *
0005  * Author: Dmitry Osipenko <digetx@gmail.com>
0006  */
0007 
0008 #include <linux/bitfield.h>
0009 #include <linux/clk.h>
0010 #include <linux/clk/tegra.h>
0011 #include <linux/debugfs.h>
0012 #include <linux/devfreq.h>
0013 #include <linux/err.h>
0014 #include <linux/interconnect-provider.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/io.h>
0017 #include <linux/iopoll.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/mutex.h>
0021 #include <linux/of.h>
0022 #include <linux/platform_device.h>
0023 #include <linux/pm_opp.h>
0024 #include <linux/slab.h>
0025 #include <linux/sort.h>
0026 #include <linux/types.h>
0027 
0028 #include <soc/tegra/common.h>
0029 #include <soc/tegra/fuse.h>
0030 
0031 #include "../jedec_ddr.h"
0032 #include "../of_memory.h"
0033 
0034 #include "mc.h"
0035 
0036 #define EMC_INTSTATUS               0x000
0037 #define EMC_INTMASK             0x004
0038 #define EMC_DBG                 0x008
0039 #define EMC_ADR_CFG_0               0x010
0040 #define EMC_TIMING_CONTROL          0x028
0041 #define EMC_RC                  0x02c
0042 #define EMC_RFC                 0x030
0043 #define EMC_RAS                 0x034
0044 #define EMC_RP                  0x038
0045 #define EMC_R2W                 0x03c
0046 #define EMC_W2R                 0x040
0047 #define EMC_R2P                 0x044
0048 #define EMC_W2P                 0x048
0049 #define EMC_RD_RCD              0x04c
0050 #define EMC_WR_RCD              0x050
0051 #define EMC_RRD                 0x054
0052 #define EMC_REXT                0x058
0053 #define EMC_WDV                 0x05c
0054 #define EMC_QUSE                0x060
0055 #define EMC_QRST                0x064
0056 #define EMC_QSAFE               0x068
0057 #define EMC_RDV                 0x06c
0058 #define EMC_REFRESH             0x070
0059 #define EMC_BURST_REFRESH_NUM           0x074
0060 #define EMC_PDEX2WR             0x078
0061 #define EMC_PDEX2RD             0x07c
0062 #define EMC_PCHG2PDEN               0x080
0063 #define EMC_ACT2PDEN                0x084
0064 #define EMC_AR2PDEN             0x088
0065 #define EMC_RW2PDEN             0x08c
0066 #define EMC_TXSR                0x090
0067 #define EMC_TCKE                0x094
0068 #define EMC_TFAW                0x098
0069 #define EMC_TRPAB               0x09c
0070 #define EMC_TCLKSTABLE              0x0a0
0071 #define EMC_TCLKSTOP                0x0a4
0072 #define EMC_TREFBW              0x0a8
0073 #define EMC_QUSE_EXTRA              0x0ac
0074 #define EMC_ODT_WRITE               0x0b0
0075 #define EMC_ODT_READ                0x0b4
0076 #define EMC_MRR                 0x0ec
0077 #define EMC_FBIO_CFG5               0x104
0078 #define EMC_FBIO_CFG6               0x114
0079 #define EMC_STAT_CONTROL            0x160
0080 #define EMC_STAT_LLMC_CONTROL           0x178
0081 #define EMC_STAT_PWR_CLOCK_LIMIT        0x198
0082 #define EMC_STAT_PWR_CLOCKS         0x19c
0083 #define EMC_STAT_PWR_COUNT          0x1a0
0084 #define EMC_AUTO_CAL_INTERVAL           0x2a8
0085 #define EMC_CFG_2               0x2b8
0086 #define EMC_CFG_DIG_DLL             0x2bc
0087 #define EMC_DLL_XFORM_DQS           0x2c0
0088 #define EMC_DLL_XFORM_QUSE          0x2c4
0089 #define EMC_ZCAL_REF_CNT            0x2e0
0090 #define EMC_ZCAL_WAIT_CNT           0x2e4
0091 #define EMC_CFG_CLKTRIM_0           0x2d0
0092 #define EMC_CFG_CLKTRIM_1           0x2d4
0093 #define EMC_CFG_CLKTRIM_2           0x2d8
0094 
0095 #define EMC_CLKCHANGE_REQ_ENABLE        BIT(0)
0096 #define EMC_CLKCHANGE_PD_ENABLE         BIT(1)
0097 #define EMC_CLKCHANGE_SR_ENABLE         BIT(2)
0098 
0099 #define EMC_TIMING_UPDATE           BIT(0)
0100 
0101 #define EMC_REFRESH_OVERFLOW_INT        BIT(3)
0102 #define EMC_CLKCHANGE_COMPLETE_INT      BIT(4)
0103 #define EMC_MRR_DIVLD_INT           BIT(5)
0104 
0105 #define EMC_DBG_READ_MUX_ASSEMBLY       BIT(0)
0106 #define EMC_DBG_WRITE_MUX_ACTIVE        BIT(1)
0107 #define EMC_DBG_FORCE_UPDATE            BIT(2)
0108 #define EMC_DBG_READ_DQM_CTRL           BIT(9)
0109 #define EMC_DBG_CFG_PRIORITY            BIT(24)
0110 
0111 #define EMC_FBIO_CFG5_DRAM_WIDTH_X16        BIT(4)
0112 #define EMC_FBIO_CFG5_DRAM_TYPE         GENMASK(1, 0)
0113 
0114 #define EMC_MRR_DEV_SELECTN         GENMASK(31, 30)
0115 #define EMC_MRR_MRR_MA              GENMASK(23, 16)
0116 #define EMC_MRR_MRR_DATA            GENMASK(15, 0)
0117 
0118 #define EMC_ADR_CFG_0_EMEM_NUMDEV       GENMASK(25, 24)
0119 
0120 #define EMC_PWR_GATHER_CLEAR            (1 << 8)
0121 #define EMC_PWR_GATHER_DISABLE          (2 << 8)
0122 #define EMC_PWR_GATHER_ENABLE           (3 << 8)
0123 
0124 enum emc_dram_type {
0125     DRAM_TYPE_RESERVED,
0126     DRAM_TYPE_DDR1,
0127     DRAM_TYPE_LPDDR2,
0128     DRAM_TYPE_DDR2,
0129 };
0130 
0131 static const u16 emc_timing_registers[] = {
0132     EMC_RC,
0133     EMC_RFC,
0134     EMC_RAS,
0135     EMC_RP,
0136     EMC_R2W,
0137     EMC_W2R,
0138     EMC_R2P,
0139     EMC_W2P,
0140     EMC_RD_RCD,
0141     EMC_WR_RCD,
0142     EMC_RRD,
0143     EMC_REXT,
0144     EMC_WDV,
0145     EMC_QUSE,
0146     EMC_QRST,
0147     EMC_QSAFE,
0148     EMC_RDV,
0149     EMC_REFRESH,
0150     EMC_BURST_REFRESH_NUM,
0151     EMC_PDEX2WR,
0152     EMC_PDEX2RD,
0153     EMC_PCHG2PDEN,
0154     EMC_ACT2PDEN,
0155     EMC_AR2PDEN,
0156     EMC_RW2PDEN,
0157     EMC_TXSR,
0158     EMC_TCKE,
0159     EMC_TFAW,
0160     EMC_TRPAB,
0161     EMC_TCLKSTABLE,
0162     EMC_TCLKSTOP,
0163     EMC_TREFBW,
0164     EMC_QUSE_EXTRA,
0165     EMC_FBIO_CFG6,
0166     EMC_ODT_WRITE,
0167     EMC_ODT_READ,
0168     EMC_FBIO_CFG5,
0169     EMC_CFG_DIG_DLL,
0170     EMC_DLL_XFORM_DQS,
0171     EMC_DLL_XFORM_QUSE,
0172     EMC_ZCAL_REF_CNT,
0173     EMC_ZCAL_WAIT_CNT,
0174     EMC_AUTO_CAL_INTERVAL,
0175     EMC_CFG_CLKTRIM_0,
0176     EMC_CFG_CLKTRIM_1,
0177     EMC_CFG_CLKTRIM_2,
0178 };
0179 
0180 struct emc_timing {
0181     unsigned long rate;
0182     u32 data[ARRAY_SIZE(emc_timing_registers)];
0183 };
0184 
0185 enum emc_rate_request_type {
0186     EMC_RATE_DEVFREQ,
0187     EMC_RATE_DEBUG,
0188     EMC_RATE_ICC,
0189     EMC_RATE_TYPE_MAX,
0190 };
0191 
0192 struct emc_rate_request {
0193     unsigned long min_rate;
0194     unsigned long max_rate;
0195 };
0196 
0197 struct tegra_emc {
0198     struct device *dev;
0199     struct tegra_mc *mc;
0200     struct icc_provider provider;
0201     struct notifier_block clk_nb;
0202     struct clk *clk;
0203     void __iomem *regs;
0204     unsigned int dram_bus_width;
0205 
0206     struct emc_timing *timings;
0207     unsigned int num_timings;
0208 
0209     struct {
0210         struct dentry *root;
0211         unsigned long min_rate;
0212         unsigned long max_rate;
0213     } debugfs;
0214 
0215     /*
0216      * There are multiple sources in the EMC driver which could request
0217      * a min/max clock rate, these rates are contained in this array.
0218      */
0219     struct emc_rate_request requested_rate[EMC_RATE_TYPE_MAX];
0220 
0221     /* protect shared rate-change code path */
0222     struct mutex rate_lock;
0223 
0224     struct devfreq_simple_ondemand_data ondemand_data;
0225 
0226     /* memory chip identity information */
0227     union lpddr2_basic_config4 basic_conf4;
0228     unsigned int manufacturer_id;
0229     unsigned int revision_id1;
0230     unsigned int revision_id2;
0231 
0232     bool mrr_error;
0233 };
0234 
0235 static irqreturn_t tegra_emc_isr(int irq, void *data)
0236 {
0237     struct tegra_emc *emc = data;
0238     u32 intmask = EMC_REFRESH_OVERFLOW_INT;
0239     u32 status;
0240 
0241     status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask;
0242     if (!status)
0243         return IRQ_NONE;
0244 
0245     /* notify about HW problem */
0246     if (status & EMC_REFRESH_OVERFLOW_INT)
0247         dev_err_ratelimited(emc->dev,
0248                     "refresh request overflow timeout\n");
0249 
0250     /* clear interrupts */
0251     writel_relaxed(status, emc->regs + EMC_INTSTATUS);
0252 
0253     return IRQ_HANDLED;
0254 }
0255 
0256 static struct emc_timing *tegra_emc_find_timing(struct tegra_emc *emc,
0257                         unsigned long rate)
0258 {
0259     struct emc_timing *timing = NULL;
0260     unsigned int i;
0261 
0262     for (i = 0; i < emc->num_timings; i++) {
0263         if (emc->timings[i].rate >= rate) {
0264             timing = &emc->timings[i];
0265             break;
0266         }
0267     }
0268 
0269     if (!timing) {
0270         dev_err(emc->dev, "no timing for rate %lu\n", rate);
0271         return NULL;
0272     }
0273 
0274     return timing;
0275 }
0276 
0277 static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)
0278 {
0279     struct emc_timing *timing = tegra_emc_find_timing(emc, rate);
0280     unsigned int i;
0281 
0282     if (!timing)
0283         return -EINVAL;
0284 
0285     dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n",
0286         __func__, timing->rate, rate);
0287 
0288     /* program shadow registers */
0289     for (i = 0; i < ARRAY_SIZE(timing->data); i++)
0290         writel_relaxed(timing->data[i],
0291                    emc->regs + emc_timing_registers[i]);
0292 
0293     /* wait until programming has settled */
0294     readl_relaxed(emc->regs + emc_timing_registers[i - 1]);
0295 
0296     return 0;
0297 }
0298 
0299 static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)
0300 {
0301     int err;
0302     u32 v;
0303 
0304     dev_dbg(emc->dev, "%s: flush %d\n", __func__, flush);
0305 
0306     if (flush) {
0307         /* manually initiate memory timing update */
0308         writel_relaxed(EMC_TIMING_UPDATE,
0309                    emc->regs + EMC_TIMING_CONTROL);
0310         return 0;
0311     }
0312 
0313     err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v,
0314                         v & EMC_CLKCHANGE_COMPLETE_INT,
0315                         1, 100);
0316     if (err) {
0317         dev_err(emc->dev, "emc-car handshake timeout: %d\n", err);
0318         return err;
0319     }
0320 
0321     return 0;
0322 }
0323 
0324 static int tegra_emc_clk_change_notify(struct notifier_block *nb,
0325                        unsigned long msg, void *data)
0326 {
0327     struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb);
0328     struct clk_notifier_data *cnd = data;
0329     int err;
0330 
0331     switch (msg) {
0332     case PRE_RATE_CHANGE:
0333         err = emc_prepare_timing_change(emc, cnd->new_rate);
0334         break;
0335 
0336     case ABORT_RATE_CHANGE:
0337         err = emc_prepare_timing_change(emc, cnd->old_rate);
0338         if (err)
0339             break;
0340 
0341         err = emc_complete_timing_change(emc, true);
0342         break;
0343 
0344     case POST_RATE_CHANGE:
0345         err = emc_complete_timing_change(emc, false);
0346         break;
0347 
0348     default:
0349         return NOTIFY_DONE;
0350     }
0351 
0352     return notifier_from_errno(err);
0353 }
0354 
0355 static int load_one_timing_from_dt(struct tegra_emc *emc,
0356                    struct emc_timing *timing,
0357                    struct device_node *node)
0358 {
0359     u32 rate;
0360     int err;
0361 
0362     if (!of_device_is_compatible(node, "nvidia,tegra20-emc-table")) {
0363         dev_err(emc->dev, "incompatible DT node: %pOF\n", node);
0364         return -EINVAL;
0365     }
0366 
0367     err = of_property_read_u32(node, "clock-frequency", &rate);
0368     if (err) {
0369         dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n",
0370             node, err);
0371         return err;
0372     }
0373 
0374     err = of_property_read_u32_array(node, "nvidia,emc-registers",
0375                      timing->data,
0376                      ARRAY_SIZE(emc_timing_registers));
0377     if (err) {
0378         dev_err(emc->dev,
0379             "timing %pOF: failed to read emc timing data: %d\n",
0380             node, err);
0381         return err;
0382     }
0383 
0384     /*
0385      * The EMC clock rate is twice the bus rate, and the bus rate is
0386      * measured in kHz.
0387      */
0388     timing->rate = rate * 2 * 1000;
0389 
0390     dev_dbg(emc->dev, "%s: %pOF: EMC rate %lu\n",
0391         __func__, node, timing->rate);
0392 
0393     return 0;
0394 }
0395 
0396 static int cmp_timings(const void *_a, const void *_b)
0397 {
0398     const struct emc_timing *a = _a;
0399     const struct emc_timing *b = _b;
0400 
0401     if (a->rate < b->rate)
0402         return -1;
0403 
0404     if (a->rate > b->rate)
0405         return 1;
0406 
0407     return 0;
0408 }
0409 
0410 static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,
0411                       struct device_node *node)
0412 {
0413     struct device_node *child;
0414     struct emc_timing *timing;
0415     int child_count;
0416     int err;
0417 
0418     child_count = of_get_child_count(node);
0419     if (!child_count) {
0420         dev_err(emc->dev, "no memory timings in DT node: %pOF\n", node);
0421         return -EINVAL;
0422     }
0423 
0424     emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing),
0425                     GFP_KERNEL);
0426     if (!emc->timings)
0427         return -ENOMEM;
0428 
0429     timing = emc->timings;
0430 
0431     for_each_child_of_node(node, child) {
0432         if (of_node_name_eq(child, "lpddr2"))
0433             continue;
0434 
0435         err = load_one_timing_from_dt(emc, timing++, child);
0436         if (err) {
0437             of_node_put(child);
0438             return err;
0439         }
0440 
0441         emc->num_timings++;
0442     }
0443 
0444     sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings,
0445          NULL);
0446 
0447     dev_info_once(emc->dev,
0448               "got %u timings for RAM code %u (min %luMHz max %luMHz)\n",
0449               emc->num_timings,
0450               tegra_read_ram_code(),
0451               emc->timings[0].rate / 1000000,
0452               emc->timings[emc->num_timings - 1].rate / 1000000);
0453 
0454     return 0;
0455 }
0456 
0457 static struct device_node *
0458 tegra_emc_find_node_by_ram_code(struct tegra_emc *emc)
0459 {
0460     struct device *dev = emc->dev;
0461     struct device_node *np;
0462     u32 value, ram_code;
0463     int err;
0464 
0465     if (emc->mrr_error) {
0466         dev_warn(dev, "memory timings skipped due to MRR error\n");
0467         return NULL;
0468     }
0469 
0470     if (of_get_child_count(dev->of_node) == 0) {
0471         dev_info_once(dev, "device-tree doesn't have memory timings\n");
0472         return NULL;
0473     }
0474 
0475     if (!of_property_read_bool(dev->of_node, "nvidia,use-ram-code"))
0476         return of_node_get(dev->of_node);
0477 
0478     ram_code = tegra_read_ram_code();
0479 
0480     for (np = of_find_node_by_name(dev->of_node, "emc-tables"); np;
0481          np = of_find_node_by_name(np, "emc-tables")) {
0482         err = of_property_read_u32(np, "nvidia,ram-code", &value);
0483         if (err || value != ram_code) {
0484             struct device_node *lpddr2_np;
0485             bool cfg_mismatches = false;
0486 
0487             lpddr2_np = of_find_node_by_name(np, "lpddr2");
0488             if (lpddr2_np) {
0489                 const struct lpddr2_info *info;
0490 
0491                 info = of_lpddr2_get_info(lpddr2_np, dev);
0492                 if (info) {
0493                     if (info->manufacturer_id >= 0 &&
0494                         info->manufacturer_id != emc->manufacturer_id)
0495                         cfg_mismatches = true;
0496 
0497                     if (info->revision_id1 >= 0 &&
0498                         info->revision_id1 != emc->revision_id1)
0499                         cfg_mismatches = true;
0500 
0501                     if (info->revision_id2 >= 0 &&
0502                         info->revision_id2 != emc->revision_id2)
0503                         cfg_mismatches = true;
0504 
0505                     if (info->density != emc->basic_conf4.density)
0506                         cfg_mismatches = true;
0507 
0508                     if (info->io_width != emc->basic_conf4.io_width)
0509                         cfg_mismatches = true;
0510 
0511                     if (info->arch_type != emc->basic_conf4.arch_type)
0512                         cfg_mismatches = true;
0513                 } else {
0514                     dev_err(dev, "failed to parse %pOF\n", lpddr2_np);
0515                     cfg_mismatches = true;
0516                 }
0517 
0518                 of_node_put(lpddr2_np);
0519             } else {
0520                 cfg_mismatches = true;
0521             }
0522 
0523             if (cfg_mismatches) {
0524                 of_node_put(np);
0525                 continue;
0526             }
0527         }
0528 
0529         return np;
0530     }
0531 
0532     dev_err(dev, "no memory timings for RAM code %u found in device tree\n",
0533         ram_code);
0534 
0535     return NULL;
0536 }
0537 
0538 static int emc_read_lpddr_mode_register(struct tegra_emc *emc,
0539                     unsigned int emem_dev,
0540                     unsigned int register_addr,
0541                     unsigned int *register_data)
0542 {
0543     u32 memory_dev = emem_dev ? 1 : 2;
0544     u32 val, mr_mask = 0xff;
0545     int err;
0546 
0547     /* clear data-valid interrupt status */
0548     writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS);
0549 
0550     /* issue mode register read request */
0551     val  = FIELD_PREP(EMC_MRR_DEV_SELECTN, memory_dev);
0552     val |= FIELD_PREP(EMC_MRR_MRR_MA, register_addr);
0553 
0554     writel_relaxed(val, emc->regs + EMC_MRR);
0555 
0556     /* wait for the LPDDR2 data-valid interrupt */
0557     err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val,
0558                         val & EMC_MRR_DIVLD_INT,
0559                         1, 100);
0560     if (err) {
0561         dev_err(emc->dev, "mode register %u read failed: %d\n",
0562             register_addr, err);
0563         emc->mrr_error = true;
0564         return err;
0565     }
0566 
0567     /* read out mode register data */
0568     val = readl_relaxed(emc->regs + EMC_MRR);
0569     *register_data = FIELD_GET(EMC_MRR_MRR_DATA, val) & mr_mask;
0570 
0571     return 0;
0572 }
0573 
0574 static void emc_read_lpddr_sdram_info(struct tegra_emc *emc,
0575                       unsigned int emem_dev,
0576                       bool print_out)
0577 {
0578     /* these registers are standard for all LPDDR JEDEC memory chips */
0579     emc_read_lpddr_mode_register(emc, emem_dev, 5, &emc->manufacturer_id);
0580     emc_read_lpddr_mode_register(emc, emem_dev, 6, &emc->revision_id1);
0581     emc_read_lpddr_mode_register(emc, emem_dev, 7, &emc->revision_id2);
0582     emc_read_lpddr_mode_register(emc, emem_dev, 8, &emc->basic_conf4.value);
0583 
0584     if (!print_out)
0585         return;
0586 
0587     dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u density: %uMbit iowidth: %ubit\n",
0588          emem_dev, emc->manufacturer_id,
0589          lpddr2_jedec_manufacturer(emc->manufacturer_id),
0590          emc->revision_id1, emc->revision_id2,
0591          4 >> emc->basic_conf4.arch_type,
0592          64 << emc->basic_conf4.density,
0593          32 >> emc->basic_conf4.io_width);
0594 }
0595 
0596 static int emc_setup_hw(struct tegra_emc *emc)
0597 {
0598     u32 emc_cfg, emc_dbg, emc_fbio, emc_adr_cfg;
0599     u32 intmask = EMC_REFRESH_OVERFLOW_INT;
0600     static bool print_sdram_info_once;
0601     enum emc_dram_type dram_type;
0602     const char *dram_type_str;
0603     unsigned int emem_numdev;
0604 
0605     emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2);
0606 
0607     /*
0608      * Depending on a memory type, DRAM should enter either self-refresh
0609      * or power-down state on EMC clock change.
0610      */
0611     if (!(emc_cfg & EMC_CLKCHANGE_PD_ENABLE) &&
0612         !(emc_cfg & EMC_CLKCHANGE_SR_ENABLE)) {
0613         dev_err(emc->dev,
0614             "bootloader didn't specify DRAM auto-suspend mode\n");
0615         return -EINVAL;
0616     }
0617 
0618     /* enable EMC and CAR to handshake on PLL divider/source changes */
0619     emc_cfg |= EMC_CLKCHANGE_REQ_ENABLE;
0620     writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2);
0621 
0622     /* initialize interrupt */
0623     writel_relaxed(intmask, emc->regs + EMC_INTMASK);
0624     writel_relaxed(intmask, emc->regs + EMC_INTSTATUS);
0625 
0626     /* ensure that unwanted debug features are disabled */
0627     emc_dbg = readl_relaxed(emc->regs + EMC_DBG);
0628     emc_dbg |= EMC_DBG_CFG_PRIORITY;
0629     emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY;
0630     emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE;
0631     emc_dbg &= ~EMC_DBG_FORCE_UPDATE;
0632     writel_relaxed(emc_dbg, emc->regs + EMC_DBG);
0633 
0634     emc_fbio = readl_relaxed(emc->regs + EMC_FBIO_CFG5);
0635 
0636     if (emc_fbio & EMC_FBIO_CFG5_DRAM_WIDTH_X16)
0637         emc->dram_bus_width = 16;
0638     else
0639         emc->dram_bus_width = 32;
0640 
0641     dram_type = FIELD_GET(EMC_FBIO_CFG5_DRAM_TYPE, emc_fbio);
0642 
0643     switch (dram_type) {
0644     case DRAM_TYPE_RESERVED:
0645         dram_type_str = "INVALID";
0646         break;
0647     case DRAM_TYPE_DDR1:
0648         dram_type_str = "DDR1";
0649         break;
0650     case DRAM_TYPE_LPDDR2:
0651         dram_type_str = "LPDDR2";
0652         break;
0653     case DRAM_TYPE_DDR2:
0654         dram_type_str = "DDR2";
0655         break;
0656     }
0657 
0658     emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG_0);
0659     emem_numdev = FIELD_GET(EMC_ADR_CFG_0_EMEM_NUMDEV, emc_adr_cfg) + 1;
0660 
0661     dev_info_once(emc->dev, "%ubit DRAM bus, %u %s %s attached\n",
0662               emc->dram_bus_width, emem_numdev, dram_type_str,
0663               emem_numdev == 2 ? "devices" : "device");
0664 
0665     if (dram_type == DRAM_TYPE_LPDDR2) {
0666         while (emem_numdev--)
0667             emc_read_lpddr_sdram_info(emc, emem_numdev,
0668                           !print_sdram_info_once);
0669         print_sdram_info_once = true;
0670     }
0671 
0672     return 0;
0673 }
0674 
0675 static long emc_round_rate(unsigned long rate,
0676                unsigned long min_rate,
0677                unsigned long max_rate,
0678                void *arg)
0679 {
0680     struct emc_timing *timing = NULL;
0681     struct tegra_emc *emc = arg;
0682     unsigned int i;
0683 
0684     if (!emc->num_timings)
0685         return clk_get_rate(emc->clk);
0686 
0687     min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate);
0688 
0689     for (i = 0; i < emc->num_timings; i++) {
0690         if (emc->timings[i].rate < rate && i != emc->num_timings - 1)
0691             continue;
0692 
0693         if (emc->timings[i].rate > max_rate) {
0694             i = max(i, 1u) - 1;
0695 
0696             if (emc->timings[i].rate < min_rate)
0697                 break;
0698         }
0699 
0700         if (emc->timings[i].rate < min_rate)
0701             continue;
0702 
0703         timing = &emc->timings[i];
0704         break;
0705     }
0706 
0707     if (!timing) {
0708         dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n",
0709             rate, min_rate, max_rate);
0710         return -EINVAL;
0711     }
0712 
0713     return timing->rate;
0714 }
0715 
0716 static void tegra_emc_rate_requests_init(struct tegra_emc *emc)
0717 {
0718     unsigned int i;
0719 
0720     for (i = 0; i < EMC_RATE_TYPE_MAX; i++) {
0721         emc->requested_rate[i].min_rate = 0;
0722         emc->requested_rate[i].max_rate = ULONG_MAX;
0723     }
0724 }
0725 
0726 static int emc_request_rate(struct tegra_emc *emc,
0727                 unsigned long new_min_rate,
0728                 unsigned long new_max_rate,
0729                 enum emc_rate_request_type type)
0730 {
0731     struct emc_rate_request *req = emc->requested_rate;
0732     unsigned long min_rate = 0, max_rate = ULONG_MAX;
0733     unsigned int i;
0734     int err;
0735 
0736     /* select minimum and maximum rates among the requested rates */
0737     for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) {
0738         if (i == type) {
0739             min_rate = max(new_min_rate, min_rate);
0740             max_rate = min(new_max_rate, max_rate);
0741         } else {
0742             min_rate = max(req->min_rate, min_rate);
0743             max_rate = min(req->max_rate, max_rate);
0744         }
0745     }
0746 
0747     if (min_rate > max_rate) {
0748         dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n",
0749                     __func__, type, min_rate, max_rate);
0750         return -ERANGE;
0751     }
0752 
0753     /*
0754      * EMC rate-changes should go via OPP API because it manages voltage
0755      * changes.
0756      */
0757     err = dev_pm_opp_set_rate(emc->dev, min_rate);
0758     if (err)
0759         return err;
0760 
0761     emc->requested_rate[type].min_rate = new_min_rate;
0762     emc->requested_rate[type].max_rate = new_max_rate;
0763 
0764     return 0;
0765 }
0766 
0767 static int emc_set_min_rate(struct tegra_emc *emc, unsigned long rate,
0768                 enum emc_rate_request_type type)
0769 {
0770     struct emc_rate_request *req = &emc->requested_rate[type];
0771     int ret;
0772 
0773     mutex_lock(&emc->rate_lock);
0774     ret = emc_request_rate(emc, rate, req->max_rate, type);
0775     mutex_unlock(&emc->rate_lock);
0776 
0777     return ret;
0778 }
0779 
0780 static int emc_set_max_rate(struct tegra_emc *emc, unsigned long rate,
0781                 enum emc_rate_request_type type)
0782 {
0783     struct emc_rate_request *req = &emc->requested_rate[type];
0784     int ret;
0785 
0786     mutex_lock(&emc->rate_lock);
0787     ret = emc_request_rate(emc, req->min_rate, rate, type);
0788     mutex_unlock(&emc->rate_lock);
0789 
0790     return ret;
0791 }
0792 
0793 /*
0794  * debugfs interface
0795  *
0796  * The memory controller driver exposes some files in debugfs that can be used
0797  * to control the EMC frequency. The top-level directory can be found here:
0798  *
0799  *   /sys/kernel/debug/emc
0800  *
0801  * It contains the following files:
0802  *
0803  *   - available_rates: This file contains a list of valid, space-separated
0804  *     EMC frequencies.
0805  *
0806  *   - min_rate: Writing a value to this file sets the given frequency as the
0807  *       floor of the permitted range. If this is higher than the currently
0808  *       configured EMC frequency, this will cause the frequency to be
0809  *       increased so that it stays within the valid range.
0810  *
0811  *   - max_rate: Similarily to the min_rate file, writing a value to this file
0812  *       sets the given frequency as the ceiling of the permitted range. If
0813  *       the value is lower than the currently configured EMC frequency, this
0814  *       will cause the frequency to be decreased so that it stays within the
0815  *       valid range.
0816  */
0817 
0818 static bool tegra_emc_validate_rate(struct tegra_emc *emc, unsigned long rate)
0819 {
0820     unsigned int i;
0821 
0822     for (i = 0; i < emc->num_timings; i++)
0823         if (rate == emc->timings[i].rate)
0824             return true;
0825 
0826     return false;
0827 }
0828 
0829 static int tegra_emc_debug_available_rates_show(struct seq_file *s, void *data)
0830 {
0831     struct tegra_emc *emc = s->private;
0832     const char *prefix = "";
0833     unsigned int i;
0834 
0835     for (i = 0; i < emc->num_timings; i++) {
0836         seq_printf(s, "%s%lu", prefix, emc->timings[i].rate);
0837         prefix = " ";
0838     }
0839 
0840     seq_puts(s, "\n");
0841 
0842     return 0;
0843 }
0844 
0845 static int tegra_emc_debug_available_rates_open(struct inode *inode,
0846                         struct file *file)
0847 {
0848     return single_open(file, tegra_emc_debug_available_rates_show,
0849                inode->i_private);
0850 }
0851 
0852 static const struct file_operations tegra_emc_debug_available_rates_fops = {
0853     .open = tegra_emc_debug_available_rates_open,
0854     .read = seq_read,
0855     .llseek = seq_lseek,
0856     .release = single_release,
0857 };
0858 
0859 static int tegra_emc_debug_min_rate_get(void *data, u64 *rate)
0860 {
0861     struct tegra_emc *emc = data;
0862 
0863     *rate = emc->debugfs.min_rate;
0864 
0865     return 0;
0866 }
0867 
0868 static int tegra_emc_debug_min_rate_set(void *data, u64 rate)
0869 {
0870     struct tegra_emc *emc = data;
0871     int err;
0872 
0873     if (!tegra_emc_validate_rate(emc, rate))
0874         return -EINVAL;
0875 
0876     err = emc_set_min_rate(emc, rate, EMC_RATE_DEBUG);
0877     if (err < 0)
0878         return err;
0879 
0880     emc->debugfs.min_rate = rate;
0881 
0882     return 0;
0883 }
0884 
0885 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_min_rate_fops,
0886             tegra_emc_debug_min_rate_get,
0887             tegra_emc_debug_min_rate_set, "%llu\n");
0888 
0889 static int tegra_emc_debug_max_rate_get(void *data, u64 *rate)
0890 {
0891     struct tegra_emc *emc = data;
0892 
0893     *rate = emc->debugfs.max_rate;
0894 
0895     return 0;
0896 }
0897 
0898 static int tegra_emc_debug_max_rate_set(void *data, u64 rate)
0899 {
0900     struct tegra_emc *emc = data;
0901     int err;
0902 
0903     if (!tegra_emc_validate_rate(emc, rate))
0904         return -EINVAL;
0905 
0906     err = emc_set_max_rate(emc, rate, EMC_RATE_DEBUG);
0907     if (err < 0)
0908         return err;
0909 
0910     emc->debugfs.max_rate = rate;
0911 
0912     return 0;
0913 }
0914 
0915 DEFINE_SIMPLE_ATTRIBUTE(tegra_emc_debug_max_rate_fops,
0916             tegra_emc_debug_max_rate_get,
0917             tegra_emc_debug_max_rate_set, "%llu\n");
0918 
0919 static void tegra_emc_debugfs_init(struct tegra_emc *emc)
0920 {
0921     struct device *dev = emc->dev;
0922     unsigned int i;
0923     int err;
0924 
0925     emc->debugfs.min_rate = ULONG_MAX;
0926     emc->debugfs.max_rate = 0;
0927 
0928     for (i = 0; i < emc->num_timings; i++) {
0929         if (emc->timings[i].rate < emc->debugfs.min_rate)
0930             emc->debugfs.min_rate = emc->timings[i].rate;
0931 
0932         if (emc->timings[i].rate > emc->debugfs.max_rate)
0933             emc->debugfs.max_rate = emc->timings[i].rate;
0934     }
0935 
0936     if (!emc->num_timings) {
0937         emc->debugfs.min_rate = clk_get_rate(emc->clk);
0938         emc->debugfs.max_rate = emc->debugfs.min_rate;
0939     }
0940 
0941     err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate,
0942                  emc->debugfs.max_rate);
0943     if (err < 0) {
0944         dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n",
0945             emc->debugfs.min_rate, emc->debugfs.max_rate,
0946             emc->clk);
0947     }
0948 
0949     emc->debugfs.root = debugfs_create_dir("emc", NULL);
0950 
0951     debugfs_create_file("available_rates", 0444, emc->debugfs.root,
0952                 emc, &tegra_emc_debug_available_rates_fops);
0953     debugfs_create_file("min_rate", 0644, emc->debugfs.root,
0954                 emc, &tegra_emc_debug_min_rate_fops);
0955     debugfs_create_file("max_rate", 0644, emc->debugfs.root,
0956                 emc, &tegra_emc_debug_max_rate_fops);
0957 }
0958 
0959 static inline struct tegra_emc *
0960 to_tegra_emc_provider(struct icc_provider *provider)
0961 {
0962     return container_of(provider, struct tegra_emc, provider);
0963 }
0964 
0965 static struct icc_node_data *
0966 emc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
0967 {
0968     struct icc_provider *provider = data;
0969     struct icc_node_data *ndata;
0970     struct icc_node *node;
0971 
0972     /* External Memory is the only possible ICC route */
0973     list_for_each_entry(node, &provider->nodes, node_list) {
0974         if (node->id != TEGRA_ICC_EMEM)
0975             continue;
0976 
0977         ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
0978         if (!ndata)
0979             return ERR_PTR(-ENOMEM);
0980 
0981         /*
0982          * SRC and DST nodes should have matching TAG in order to have
0983          * it set by default for a requested path.
0984          */
0985         ndata->tag = TEGRA_MC_ICC_TAG_ISO;
0986         ndata->node = node;
0987 
0988         return ndata;
0989     }
0990 
0991     return ERR_PTR(-EPROBE_DEFER);
0992 }
0993 
0994 static int emc_icc_set(struct icc_node *src, struct icc_node *dst)
0995 {
0996     struct tegra_emc *emc = to_tegra_emc_provider(dst->provider);
0997     unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw);
0998     unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw);
0999     unsigned long long rate = max(avg_bw, peak_bw);
1000     unsigned int dram_data_bus_width_bytes;
1001     int err;
1002 
1003     /*
1004      * Tegra20 EMC runs on x2 clock rate of SDRAM bus because DDR data
1005      * is sampled on both clock edges.  This means that EMC clock rate
1006      * equals to the peak data-rate.
1007      */
1008     dram_data_bus_width_bytes = emc->dram_bus_width / 8;
1009     do_div(rate, dram_data_bus_width_bytes);
1010     rate = min_t(u64, rate, U32_MAX);
1011 
1012     err = emc_set_min_rate(emc, rate, EMC_RATE_ICC);
1013     if (err)
1014         return err;
1015 
1016     return 0;
1017 }
1018 
1019 static int tegra_emc_interconnect_init(struct tegra_emc *emc)
1020 {
1021     const struct tegra_mc_soc *soc;
1022     struct icc_node *node;
1023     int err;
1024 
1025     emc->mc = devm_tegra_memory_controller_get(emc->dev);
1026     if (IS_ERR(emc->mc))
1027         return PTR_ERR(emc->mc);
1028 
1029     soc = emc->mc->soc;
1030 
1031     emc->provider.dev = emc->dev;
1032     emc->provider.set = emc_icc_set;
1033     emc->provider.data = &emc->provider;
1034     emc->provider.aggregate = soc->icc_ops->aggregate;
1035     emc->provider.xlate_extended = emc_of_icc_xlate_extended;
1036 
1037     err = icc_provider_add(&emc->provider);
1038     if (err)
1039         goto err_msg;
1040 
1041     /* create External Memory Controller node */
1042     node = icc_node_create(TEGRA_ICC_EMC);
1043     if (IS_ERR(node)) {
1044         err = PTR_ERR(node);
1045         goto del_provider;
1046     }
1047 
1048     node->name = "External Memory Controller";
1049     icc_node_add(node, &emc->provider);
1050 
1051     /* link External Memory Controller to External Memory (DRAM) */
1052     err = icc_link_create(node, TEGRA_ICC_EMEM);
1053     if (err)
1054         goto remove_nodes;
1055 
1056     /* create External Memory node */
1057     node = icc_node_create(TEGRA_ICC_EMEM);
1058     if (IS_ERR(node)) {
1059         err = PTR_ERR(node);
1060         goto remove_nodes;
1061     }
1062 
1063     node->name = "External Memory (DRAM)";
1064     icc_node_add(node, &emc->provider);
1065 
1066     return 0;
1067 
1068 remove_nodes:
1069     icc_nodes_remove(&emc->provider);
1070 del_provider:
1071     icc_provider_del(&emc->provider);
1072 err_msg:
1073     dev_err(emc->dev, "failed to initialize ICC: %d\n", err);
1074 
1075     return err;
1076 }
1077 
1078 static void devm_tegra_emc_unset_callback(void *data)
1079 {
1080     tegra20_clk_set_emc_round_callback(NULL, NULL);
1081 }
1082 
1083 static void devm_tegra_emc_unreg_clk_notifier(void *data)
1084 {
1085     struct tegra_emc *emc = data;
1086 
1087     clk_notifier_unregister(emc->clk, &emc->clk_nb);
1088 }
1089 
1090 static int tegra_emc_init_clk(struct tegra_emc *emc)
1091 {
1092     int err;
1093 
1094     tegra20_clk_set_emc_round_callback(emc_round_rate, emc);
1095 
1096     err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback,
1097                        NULL);
1098     if (err)
1099         return err;
1100 
1101     emc->clk = devm_clk_get(emc->dev, NULL);
1102     if (IS_ERR(emc->clk)) {
1103         dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk);
1104         return PTR_ERR(emc->clk);
1105     }
1106 
1107     err = clk_notifier_register(emc->clk, &emc->clk_nb);
1108     if (err) {
1109         dev_err(emc->dev, "failed to register clk notifier: %d\n", err);
1110         return err;
1111     }
1112 
1113     err = devm_add_action_or_reset(emc->dev,
1114                        devm_tegra_emc_unreg_clk_notifier, emc);
1115     if (err)
1116         return err;
1117 
1118     return 0;
1119 }
1120 
1121 static int tegra_emc_devfreq_target(struct device *dev, unsigned long *freq,
1122                     u32 flags)
1123 {
1124     struct tegra_emc *emc = dev_get_drvdata(dev);
1125     struct dev_pm_opp *opp;
1126     unsigned long rate;
1127 
1128     opp = devfreq_recommended_opp(dev, freq, flags);
1129     if (IS_ERR(opp)) {
1130         dev_err(dev, "failed to find opp for %lu Hz\n", *freq);
1131         return PTR_ERR(opp);
1132     }
1133 
1134     rate = dev_pm_opp_get_freq(opp);
1135     dev_pm_opp_put(opp);
1136 
1137     return emc_set_min_rate(emc, rate, EMC_RATE_DEVFREQ);
1138 }
1139 
1140 static int tegra_emc_devfreq_get_dev_status(struct device *dev,
1141                         struct devfreq_dev_status *stat)
1142 {
1143     struct tegra_emc *emc = dev_get_drvdata(dev);
1144 
1145     /* freeze counters */
1146     writel_relaxed(EMC_PWR_GATHER_DISABLE, emc->regs + EMC_STAT_CONTROL);
1147 
1148     /*
1149      *  busy_time: number of clocks EMC request was accepted
1150      * total_time: number of clocks PWR_GATHER control was set to ENABLE
1151      */
1152     stat->busy_time = readl_relaxed(emc->regs + EMC_STAT_PWR_COUNT);
1153     stat->total_time = readl_relaxed(emc->regs + EMC_STAT_PWR_CLOCKS);
1154     stat->current_frequency = clk_get_rate(emc->clk);
1155 
1156     /* clear counters and restart */
1157     writel_relaxed(EMC_PWR_GATHER_CLEAR, emc->regs + EMC_STAT_CONTROL);
1158     writel_relaxed(EMC_PWR_GATHER_ENABLE, emc->regs + EMC_STAT_CONTROL);
1159 
1160     return 0;
1161 }
1162 
1163 static struct devfreq_dev_profile tegra_emc_devfreq_profile = {
1164     .polling_ms = 30,
1165     .target = tegra_emc_devfreq_target,
1166     .get_dev_status = tegra_emc_devfreq_get_dev_status,
1167 };
1168 
1169 static int tegra_emc_devfreq_init(struct tegra_emc *emc)
1170 {
1171     struct devfreq *devfreq;
1172 
1173     /*
1174      * PWR_COUNT is 1/2 of PWR_CLOCKS at max, and thus, the up-threshold
1175      * should be less than 50.  Secondly, multiple active memory clients
1176      * may cause over 20% of lost clock cycles due to stalls caused by
1177      * competing memory accesses.  This means that threshold should be
1178      * set to a less than 30 in order to have a properly working governor.
1179      */
1180     emc->ondemand_data.upthreshold = 20;
1181 
1182     /*
1183      * Reset statistic gathers state, select global bandwidth for the
1184      * statistics collection mode and set clocks counter saturation
1185      * limit to maximum.
1186      */
1187     writel_relaxed(0x00000000, emc->regs + EMC_STAT_CONTROL);
1188     writel_relaxed(0x00000000, emc->regs + EMC_STAT_LLMC_CONTROL);
1189     writel_relaxed(0xffffffff, emc->regs + EMC_STAT_PWR_CLOCK_LIMIT);
1190 
1191     devfreq = devm_devfreq_add_device(emc->dev, &tegra_emc_devfreq_profile,
1192                       DEVFREQ_GOV_SIMPLE_ONDEMAND,
1193                       &emc->ondemand_data);
1194     if (IS_ERR(devfreq)) {
1195         dev_err(emc->dev, "failed to initialize devfreq: %pe", devfreq);
1196         return PTR_ERR(devfreq);
1197     }
1198 
1199     return 0;
1200 }
1201 
1202 static int tegra_emc_probe(struct platform_device *pdev)
1203 {
1204     struct tegra_core_opp_params opp_params = {};
1205     struct device_node *np;
1206     struct tegra_emc *emc;
1207     int irq, err;
1208 
1209     irq = platform_get_irq(pdev, 0);
1210     if (irq < 0) {
1211         dev_err(&pdev->dev, "please update your device tree\n");
1212         return irq;
1213     }
1214 
1215     emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL);
1216     if (!emc)
1217         return -ENOMEM;
1218 
1219     mutex_init(&emc->rate_lock);
1220     emc->clk_nb.notifier_call = tegra_emc_clk_change_notify;
1221     emc->dev = &pdev->dev;
1222 
1223     emc->regs = devm_platform_ioremap_resource(pdev, 0);
1224     if (IS_ERR(emc->regs))
1225         return PTR_ERR(emc->regs);
1226 
1227     err = emc_setup_hw(emc);
1228     if (err)
1229         return err;
1230 
1231     np = tegra_emc_find_node_by_ram_code(emc);
1232     if (np) {
1233         err = tegra_emc_load_timings_from_dt(emc, np);
1234         of_node_put(np);
1235         if (err)
1236             return err;
1237     }
1238 
1239     err = devm_request_irq(&pdev->dev, irq, tegra_emc_isr, 0,
1240                    dev_name(&pdev->dev), emc);
1241     if (err) {
1242         dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1243         return err;
1244     }
1245 
1246     err = tegra_emc_init_clk(emc);
1247     if (err)
1248         return err;
1249 
1250     opp_params.init_state = true;
1251 
1252     err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params);
1253     if (err)
1254         return err;
1255 
1256     platform_set_drvdata(pdev, emc);
1257     tegra_emc_rate_requests_init(emc);
1258     tegra_emc_debugfs_init(emc);
1259     tegra_emc_interconnect_init(emc);
1260     tegra_emc_devfreq_init(emc);
1261 
1262     /*
1263      * Don't allow the kernel module to be unloaded. Unloading adds some
1264      * extra complexity which doesn't really worth the effort in a case of
1265      * this driver.
1266      */
1267     try_module_get(THIS_MODULE);
1268 
1269     return 0;
1270 }
1271 
1272 static const struct of_device_id tegra_emc_of_match[] = {
1273     { .compatible = "nvidia,tegra20-emc", },
1274     {},
1275 };
1276 MODULE_DEVICE_TABLE(of, tegra_emc_of_match);
1277 
1278 static struct platform_driver tegra_emc_driver = {
1279     .probe = tegra_emc_probe,
1280     .driver = {
1281         .name = "tegra20-emc",
1282         .of_match_table = tegra_emc_of_match,
1283         .suppress_bind_attrs = true,
1284         .sync_state = icc_sync_state,
1285     },
1286 };
1287 module_platform_driver(tegra_emc_driver);
1288 
1289 MODULE_AUTHOR("Dmitry Osipenko <digetx@gmail.com>");
1290 MODULE_DESCRIPTION("NVIDIA Tegra20 EMC driver");
1291 MODULE_SOFTDEP("pre: governor_simpleondemand");
1292 MODULE_LICENSE("GPL v2");
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