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0006 #include <soc/tegra/mc.h>
0007
0008 #include <dt-bindings/memory/tegra194-mc.h>
0009
0010 #include "mc.h"
0011
0012 static const struct tegra_mc_client tegra194_mc_clients[] = {
0013 {
0014 .id = TEGRA194_MEMORY_CLIENT_PTCR,
0015 .name = "ptcr",
0016 .sid = TEGRA194_SID_PASSTHROUGH,
0017 .regs = {
0018 .sid = {
0019 .override = 0x000,
0020 .security = 0x004,
0021 },
0022 },
0023 }, {
0024 .id = TEGRA194_MEMORY_CLIENT_MIU7R,
0025 .name = "miu7r",
0026 .sid = TEGRA194_SID_MIU,
0027 .regs = {
0028 .sid = {
0029 .override = 0x008,
0030 .security = 0x00c,
0031 },
0032 },
0033 }, {
0034 .id = TEGRA194_MEMORY_CLIENT_MIU7W,
0035 .name = "miu7w",
0036 .sid = TEGRA194_SID_MIU,
0037 .regs = {
0038 .sid = {
0039 .override = 0x010,
0040 .security = 0x014,
0041 },
0042 },
0043 }, {
0044 .id = TEGRA194_MEMORY_CLIENT_HDAR,
0045 .name = "hdar",
0046 .sid = TEGRA194_SID_HDA,
0047 .regs = {
0048 .sid = {
0049 .override = 0x0a8,
0050 .security = 0x0ac,
0051 },
0052 },
0053 }, {
0054 .id = TEGRA194_MEMORY_CLIENT_HOST1XDMAR,
0055 .name = "host1xdmar",
0056 .sid = TEGRA194_SID_HOST1X,
0057 .regs = {
0058 .sid = {
0059 .override = 0x0b0,
0060 .security = 0x0b4,
0061 },
0062 },
0063 }, {
0064 .id = TEGRA194_MEMORY_CLIENT_NVENCSRD,
0065 .name = "nvencsrd",
0066 .sid = TEGRA194_SID_NVENC,
0067 .regs = {
0068 .sid = {
0069 .override = 0x0e0,
0070 .security = 0x0e4,
0071 },
0072 },
0073 }, {
0074 .id = TEGRA194_MEMORY_CLIENT_SATAR,
0075 .name = "satar",
0076 .sid = TEGRA194_SID_SATA,
0077 .regs = {
0078 .sid = {
0079 .override = 0x0f8,
0080 .security = 0x0fc,
0081 },
0082 },
0083 }, {
0084 .id = TEGRA194_MEMORY_CLIENT_MPCORER,
0085 .name = "mpcorer",
0086 .sid = TEGRA194_SID_PASSTHROUGH,
0087 .regs = {
0088 .sid = {
0089 .override = 0x138,
0090 .security = 0x13c,
0091 },
0092 },
0093 }, {
0094 .id = TEGRA194_MEMORY_CLIENT_NVENCSWR,
0095 .name = "nvencswr",
0096 .sid = TEGRA194_SID_NVENC,
0097 .regs = {
0098 .sid = {
0099 .override = 0x158,
0100 .security = 0x15c,
0101 },
0102 },
0103 }, {
0104 .id = TEGRA194_MEMORY_CLIENT_HDAW,
0105 .name = "hdaw",
0106 .sid = TEGRA194_SID_HDA,
0107 .regs = {
0108 .sid = {
0109 .override = 0x1a8,
0110 .security = 0x1ac,
0111 },
0112 },
0113 }, {
0114 .id = TEGRA194_MEMORY_CLIENT_MPCOREW,
0115 .name = "mpcorew",
0116 .sid = TEGRA194_SID_PASSTHROUGH,
0117 .regs = {
0118 .sid = {
0119 .override = 0x1c8,
0120 .security = 0x1cc,
0121 },
0122 },
0123 }, {
0124 .id = TEGRA194_MEMORY_CLIENT_SATAW,
0125 .name = "sataw",
0126 .sid = TEGRA194_SID_SATA,
0127 .regs = {
0128 .sid = {
0129 .override = 0x1e8,
0130 .security = 0x1ec,
0131 },
0132 },
0133 }, {
0134 .id = TEGRA194_MEMORY_CLIENT_ISPRA,
0135 .name = "ispra",
0136 .sid = TEGRA194_SID_ISP,
0137 .regs = {
0138 .sid = {
0139 .override = 0x220,
0140 .security = 0x224,
0141 },
0142 },
0143 }, {
0144 .id = TEGRA194_MEMORY_CLIENT_ISPFALR,
0145 .name = "ispfalr",
0146 .sid = TEGRA194_SID_ISP_FALCON,
0147 .regs = {
0148 .sid = {
0149 .override = 0x228,
0150 .security = 0x22c,
0151 },
0152 },
0153 }, {
0154 .id = TEGRA194_MEMORY_CLIENT_ISPWA,
0155 .name = "ispwa",
0156 .sid = TEGRA194_SID_ISP,
0157 .regs = {
0158 .sid = {
0159 .override = 0x230,
0160 .security = 0x234,
0161 },
0162 },
0163 }, {
0164 .id = TEGRA194_MEMORY_CLIENT_ISPWB,
0165 .name = "ispwb",
0166 .sid = TEGRA194_SID_ISP,
0167 .regs = {
0168 .sid = {
0169 .override = 0x238,
0170 .security = 0x23c,
0171 },
0172 },
0173 }, {
0174 .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTR,
0175 .name = "xusb_hostr",
0176 .sid = TEGRA194_SID_XUSB_HOST,
0177 .regs = {
0178 .sid = {
0179 .override = 0x250,
0180 .security = 0x254,
0181 },
0182 },
0183 }, {
0184 .id = TEGRA194_MEMORY_CLIENT_XUSB_HOSTW,
0185 .name = "xusb_hostw",
0186 .sid = TEGRA194_SID_XUSB_HOST,
0187 .regs = {
0188 .sid = {
0189 .override = 0x258,
0190 .security = 0x25c,
0191 },
0192 },
0193 }, {
0194 .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVR,
0195 .name = "xusb_devr",
0196 .sid = TEGRA194_SID_XUSB_DEV,
0197 .regs = {
0198 .sid = {
0199 .override = 0x260,
0200 .security = 0x264,
0201 },
0202 },
0203 }, {
0204 .id = TEGRA194_MEMORY_CLIENT_XUSB_DEVW,
0205 .name = "xusb_devw",
0206 .sid = TEGRA194_SID_XUSB_DEV,
0207 .regs = {
0208 .sid = {
0209 .override = 0x268,
0210 .security = 0x26c,
0211 },
0212 },
0213 }, {
0214 .id = TEGRA194_MEMORY_CLIENT_SDMMCRA,
0215 .name = "sdmmcra",
0216 .sid = TEGRA194_SID_SDMMC1,
0217 .regs = {
0218 .sid = {
0219 .override = 0x300,
0220 .security = 0x304,
0221 },
0222 },
0223 }, {
0224 .id = TEGRA194_MEMORY_CLIENT_SDMMCR,
0225 .name = "sdmmcr",
0226 .sid = TEGRA194_SID_SDMMC3,
0227 .regs = {
0228 .sid = {
0229 .override = 0x310,
0230 .security = 0x314,
0231 },
0232 },
0233 }, {
0234 .id = TEGRA194_MEMORY_CLIENT_SDMMCRAB,
0235 .name = "sdmmcrab",
0236 .sid = TEGRA194_SID_SDMMC4,
0237 .regs = {
0238 .sid = {
0239 .override = 0x318,
0240 .security = 0x31c,
0241 },
0242 },
0243 }, {
0244 .id = TEGRA194_MEMORY_CLIENT_SDMMCWA,
0245 .name = "sdmmcwa",
0246 .sid = TEGRA194_SID_SDMMC1,
0247 .regs = {
0248 .sid = {
0249 .override = 0x320,
0250 .security = 0x324,
0251 },
0252 },
0253 }, {
0254 .id = TEGRA194_MEMORY_CLIENT_SDMMCW,
0255 .name = "sdmmcw",
0256 .sid = TEGRA194_SID_SDMMC3,
0257 .regs = {
0258 .sid = {
0259 .override = 0x330,
0260 .security = 0x334,
0261 },
0262 },
0263 }, {
0264 .id = TEGRA194_MEMORY_CLIENT_SDMMCWAB,
0265 .name = "sdmmcwab",
0266 .sid = TEGRA194_SID_SDMMC4,
0267 .regs = {
0268 .sid = {
0269 .override = 0x338,
0270 .security = 0x33c,
0271 },
0272 },
0273 }, {
0274 .id = TEGRA194_MEMORY_CLIENT_VICSRD,
0275 .name = "vicsrd",
0276 .sid = TEGRA194_SID_VIC,
0277 .regs = {
0278 .sid = {
0279 .override = 0x360,
0280 .security = 0x364,
0281 },
0282 },
0283 }, {
0284 .id = TEGRA194_MEMORY_CLIENT_VICSWR,
0285 .name = "vicswr",
0286 .sid = TEGRA194_SID_VIC,
0287 .regs = {
0288 .sid = {
0289 .override = 0x368,
0290 .security = 0x36c,
0291 },
0292 },
0293 }, {
0294 .id = TEGRA194_MEMORY_CLIENT_VIW,
0295 .name = "viw",
0296 .sid = TEGRA194_SID_VI,
0297 .regs = {
0298 .sid = {
0299 .override = 0x390,
0300 .security = 0x394,
0301 },
0302 },
0303 }, {
0304 .id = TEGRA194_MEMORY_CLIENT_NVDECSRD,
0305 .name = "nvdecsrd",
0306 .sid = TEGRA194_SID_NVDEC,
0307 .regs = {
0308 .sid = {
0309 .override = 0x3c0,
0310 .security = 0x3c4,
0311 },
0312 },
0313 }, {
0314 .id = TEGRA194_MEMORY_CLIENT_NVDECSWR,
0315 .name = "nvdecswr",
0316 .sid = TEGRA194_SID_NVDEC,
0317 .regs = {
0318 .sid = {
0319 .override = 0x3c8,
0320 .security = 0x3cc,
0321 },
0322 },
0323 }, {
0324 .id = TEGRA194_MEMORY_CLIENT_APER,
0325 .name = "aper",
0326 .sid = TEGRA194_SID_APE,
0327 .regs = {
0328 .sid = {
0329 .override = 0x3c0,
0330 .security = 0x3c4,
0331 },
0332 },
0333 }, {
0334 .id = TEGRA194_MEMORY_CLIENT_APEW,
0335 .name = "apew",
0336 .sid = TEGRA194_SID_APE,
0337 .regs = {
0338 .sid = {
0339 .override = 0x3d0,
0340 .security = 0x3d4,
0341 },
0342 },
0343 }, {
0344 .id = TEGRA194_MEMORY_CLIENT_NVJPGSRD,
0345 .name = "nvjpgsrd",
0346 .sid = TEGRA194_SID_NVJPG,
0347 .regs = {
0348 .sid = {
0349 .override = 0x3f0,
0350 .security = 0x3f4,
0351 },
0352 },
0353 }, {
0354 .id = TEGRA194_MEMORY_CLIENT_NVJPGSWR,
0355 .name = "nvjpgswr",
0356 .sid = TEGRA194_SID_NVJPG,
0357 .regs = {
0358 .sid = {
0359 .override = 0x3f0,
0360 .security = 0x3f4,
0361 },
0362 },
0363 }, {
0364 .name = "axiapr",
0365 .id = TEGRA194_MEMORY_CLIENT_AXIAPR,
0366 .sid = TEGRA194_SID_PASSTHROUGH,
0367 .regs = {
0368 .sid = {
0369 .override = 0x410,
0370 .security = 0x414,
0371 },
0372 },
0373 }, {
0374 .id = TEGRA194_MEMORY_CLIENT_AXIAPW,
0375 .name = "axiapw",
0376 .sid = TEGRA194_SID_PASSTHROUGH,
0377 .regs = {
0378 .sid = {
0379 .override = 0x418,
0380 .security = 0x41c,
0381 },
0382 },
0383 }, {
0384 .id = TEGRA194_MEMORY_CLIENT_ETRR,
0385 .name = "etrr",
0386 .sid = TEGRA194_SID_ETR,
0387 .regs = {
0388 .sid = {
0389 .override = 0x420,
0390 .security = 0x424,
0391 },
0392 },
0393 }, {
0394 .id = TEGRA194_MEMORY_CLIENT_ETRW,
0395 .name = "etrw",
0396 .sid = TEGRA194_SID_ETR,
0397 .regs = {
0398 .sid = {
0399 .override = 0x428,
0400 .security = 0x42c,
0401 },
0402 },
0403 }, {
0404 .id = TEGRA194_MEMORY_CLIENT_AXISR,
0405 .name = "axisr",
0406 .sid = TEGRA194_SID_PASSTHROUGH,
0407 .regs = {
0408 .sid = {
0409 .override = 0x460,
0410 .security = 0x464,
0411 },
0412 },
0413 }, {
0414 .id = TEGRA194_MEMORY_CLIENT_AXISW,
0415 .name = "axisw",
0416 .sid = TEGRA194_SID_PASSTHROUGH,
0417 .regs = {
0418 .sid = {
0419 .override = 0x468,
0420 .security = 0x46c,
0421 },
0422 },
0423 }, {
0424 .id = TEGRA194_MEMORY_CLIENT_EQOSR,
0425 .name = "eqosr",
0426 .sid = TEGRA194_SID_EQOS,
0427 .regs = {
0428 .sid = {
0429 .override = 0x470,
0430 .security = 0x474,
0431 },
0432 },
0433 }, {
0434 .name = "eqosw",
0435 .id = TEGRA194_MEMORY_CLIENT_EQOSW,
0436 .sid = TEGRA194_SID_EQOS,
0437 .regs = {
0438 .sid = {
0439 .override = 0x478,
0440 .security = 0x47c,
0441 },
0442 },
0443 }, {
0444 .id = TEGRA194_MEMORY_CLIENT_UFSHCR,
0445 .name = "ufshcr",
0446 .sid = TEGRA194_SID_UFSHC,
0447 .regs = {
0448 .sid = {
0449 .override = 0x480,
0450 .security = 0x484,
0451 },
0452 },
0453 }, {
0454 .id = TEGRA194_MEMORY_CLIENT_UFSHCW,
0455 .name = "ufshcw",
0456 .sid = TEGRA194_SID_UFSHC,
0457 .regs = {
0458 .sid = {
0459 .override = 0x488,
0460 .security = 0x48c,
0461 },
0462 },
0463 }, {
0464 .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR,
0465 .name = "nvdisplayr",
0466 .sid = TEGRA194_SID_NVDISPLAY,
0467 .regs = {
0468 .sid = {
0469 .override = 0x490,
0470 .security = 0x494,
0471 },
0472 },
0473 }, {
0474 .id = TEGRA194_MEMORY_CLIENT_BPMPR,
0475 .name = "bpmpr",
0476 .sid = TEGRA194_SID_BPMP,
0477 .regs = {
0478 .sid = {
0479 .override = 0x498,
0480 .security = 0x49c,
0481 },
0482 },
0483 }, {
0484 .id = TEGRA194_MEMORY_CLIENT_BPMPW,
0485 .name = "bpmpw",
0486 .sid = TEGRA194_SID_BPMP,
0487 .regs = {
0488 .sid = {
0489 .override = 0x4a0,
0490 .security = 0x4a4,
0491 },
0492 },
0493 }, {
0494 .id = TEGRA194_MEMORY_CLIENT_BPMPDMAR,
0495 .name = "bpmpdmar",
0496 .sid = TEGRA194_SID_BPMP,
0497 .regs = {
0498 .sid = {
0499 .override = 0x4a8,
0500 .security = 0x4ac,
0501 },
0502 },
0503 }, {
0504 .id = TEGRA194_MEMORY_CLIENT_BPMPDMAW,
0505 .name = "bpmpdmaw",
0506 .sid = TEGRA194_SID_BPMP,
0507 .regs = {
0508 .sid = {
0509 .override = 0x4b0,
0510 .security = 0x4b4,
0511 },
0512 },
0513 }, {
0514 .id = TEGRA194_MEMORY_CLIENT_AONR,
0515 .name = "aonr",
0516 .sid = TEGRA194_SID_AON,
0517 .regs = {
0518 .sid = {
0519 .override = 0x4b8,
0520 .security = 0x4bc,
0521 },
0522 },
0523 }, {
0524 .id = TEGRA194_MEMORY_CLIENT_AONW,
0525 .name = "aonw",
0526 .sid = TEGRA194_SID_AON,
0527 .regs = {
0528 .sid = {
0529 .override = 0x4c0,
0530 .security = 0x4c4,
0531 },
0532 },
0533 }, {
0534 .id = TEGRA194_MEMORY_CLIENT_AONDMAR,
0535 .name = "aondmar",
0536 .sid = TEGRA194_SID_AON,
0537 .regs = {
0538 .sid = {
0539 .override = 0x4c8,
0540 .security = 0x4cc,
0541 },
0542 },
0543 }, {
0544 .id = TEGRA194_MEMORY_CLIENT_AONDMAW,
0545 .name = "aondmaw",
0546 .sid = TEGRA194_SID_AON,
0547 .regs = {
0548 .sid = {
0549 .override = 0x4d0,
0550 .security = 0x4d4,
0551 },
0552 },
0553 }, {
0554 .id = TEGRA194_MEMORY_CLIENT_SCER,
0555 .name = "scer",
0556 .sid = TEGRA194_SID_SCE,
0557 .regs = {
0558 .sid = {
0559 .override = 0x4d8,
0560 .security = 0x4dc,
0561 },
0562 },
0563 }, {
0564 .id = TEGRA194_MEMORY_CLIENT_SCEW,
0565 .name = "scew",
0566 .sid = TEGRA194_SID_SCE,
0567 .regs = {
0568 .sid = {
0569 .override = 0x4e0,
0570 .security = 0x4e4,
0571 },
0572 },
0573 }, {
0574 .id = TEGRA194_MEMORY_CLIENT_SCEDMAR,
0575 .name = "scedmar",
0576 .sid = TEGRA194_SID_SCE,
0577 .regs = {
0578 .sid = {
0579 .override = 0x4e8,
0580 .security = 0x4ec,
0581 },
0582 },
0583 }, {
0584 .id = TEGRA194_MEMORY_CLIENT_SCEDMAW,
0585 .name = "scedmaw",
0586 .sid = TEGRA194_SID_SCE,
0587 .regs = {
0588 .sid = {
0589 .override = 0x4f0,
0590 .security = 0x4f4,
0591 },
0592 },
0593 }, {
0594 .id = TEGRA194_MEMORY_CLIENT_APEDMAR,
0595 .name = "apedmar",
0596 .sid = TEGRA194_SID_APE,
0597 .regs = {
0598 .sid = {
0599 .override = 0x4f8,
0600 .security = 0x4fc,
0601 },
0602 },
0603 }, {
0604 .id = TEGRA194_MEMORY_CLIENT_APEDMAW,
0605 .name = "apedmaw",
0606 .sid = TEGRA194_SID_APE,
0607 .regs = {
0608 .sid = {
0609 .override = 0x500,
0610 .security = 0x504,
0611 },
0612 },
0613 }, {
0614 .id = TEGRA194_MEMORY_CLIENT_NVDISPLAYR1,
0615 .name = "nvdisplayr1",
0616 .sid = TEGRA194_SID_NVDISPLAY,
0617 .regs = {
0618 .sid = {
0619 .override = 0x508,
0620 .security = 0x50c,
0621 },
0622 },
0623 }, {
0624 .id = TEGRA194_MEMORY_CLIENT_VICSRD1,
0625 .name = "vicsrd1",
0626 .sid = TEGRA194_SID_VIC,
0627 .regs = {
0628 .sid = {
0629 .override = 0x510,
0630 .security = 0x514,
0631 },
0632 },
0633 }, {
0634 .id = TEGRA194_MEMORY_CLIENT_NVDECSRD1,
0635 .name = "nvdecsrd1",
0636 .sid = TEGRA194_SID_NVDEC,
0637 .regs = {
0638 .sid = {
0639 .override = 0x518,
0640 .security = 0x51c,
0641 },
0642 },
0643 }, {
0644 .id = TEGRA194_MEMORY_CLIENT_MIU0R,
0645 .name = "miu0r",
0646 .sid = TEGRA194_SID_MIU,
0647 .regs = {
0648 .sid = {
0649 .override = 0x530,
0650 .security = 0x534,
0651 },
0652 },
0653 }, {
0654 .name = "miu0w",
0655 .id = TEGRA194_MEMORY_CLIENT_MIU0W,
0656 .sid = TEGRA194_SID_MIU,
0657 .regs = {
0658 .sid = {
0659 .override = 0x538,
0660 .security = 0x53c,
0661 },
0662 },
0663 }, {
0664 .id = TEGRA194_MEMORY_CLIENT_MIU1R,
0665 .name = "miu1r",
0666 .sid = TEGRA194_SID_MIU,
0667 .regs = {
0668 .sid = {
0669 .override = 0x540,
0670 .security = 0x544,
0671 },
0672 },
0673 }, {
0674 .id = TEGRA194_MEMORY_CLIENT_MIU1W,
0675 .name = "miu1w",
0676 .sid = TEGRA194_SID_MIU,
0677 .regs = {
0678 .sid = {
0679 .override = 0x548,
0680 .security = 0x54c,
0681 },
0682 },
0683 }, {
0684 .id = TEGRA194_MEMORY_CLIENT_MIU2R,
0685 .name = "miu2r",
0686 .sid = TEGRA194_SID_MIU,
0687 .regs = {
0688 .sid = {
0689 .override = 0x570,
0690 .security = 0x574,
0691 },
0692 },
0693 }, {
0694 .id = TEGRA194_MEMORY_CLIENT_MIU2W,
0695 .name = "miu2w",
0696 .sid = TEGRA194_SID_MIU,
0697 .regs = {
0698 .sid = {
0699 .override = 0x578,
0700 .security = 0x57c,
0701 },
0702 },
0703 }, {
0704 .id = TEGRA194_MEMORY_CLIENT_MIU3R,
0705 .name = "miu3r",
0706 .sid = TEGRA194_SID_MIU,
0707 .regs = {
0708 .sid = {
0709 .override = 0x580,
0710 .security = 0x584,
0711 },
0712 },
0713 }, {
0714 .id = TEGRA194_MEMORY_CLIENT_MIU3W,
0715 .name = "miu3w",
0716 .sid = TEGRA194_SID_MIU,
0717 .regs = {
0718 .sid = {
0719 .override = 0x588,
0720 .security = 0x58c,
0721 },
0722 },
0723 }, {
0724 .id = TEGRA194_MEMORY_CLIENT_MIU4R,
0725 .name = "miu4r",
0726 .sid = TEGRA194_SID_MIU,
0727 .regs = {
0728 .sid = {
0729 .override = 0x590,
0730 .security = 0x594,
0731 },
0732 },
0733 }, {
0734 .id = TEGRA194_MEMORY_CLIENT_MIU4W,
0735 .name = "miu4w",
0736 .sid = TEGRA194_SID_MIU,
0737 .regs = {
0738 .sid = {
0739 .override = 0x598,
0740 .security = 0x59c,
0741 },
0742 },
0743 }, {
0744 .id = TEGRA194_MEMORY_CLIENT_DPMUR,
0745 .name = "dpmur",
0746 .sid = TEGRA194_SID_PASSTHROUGH,
0747 .regs = {
0748 .sid = {
0749 .override = 0x598,
0750 .security = 0x59c,
0751 },
0752 },
0753 }, {
0754 .id = TEGRA194_MEMORY_CLIENT_VIFALR,
0755 .name = "vifalr",
0756 .sid = TEGRA194_SID_VI_FALCON,
0757 .regs = {
0758 .sid = {
0759 .override = 0x5e0,
0760 .security = 0x5e4,
0761 },
0762 },
0763 }, {
0764 .id = TEGRA194_MEMORY_CLIENT_VIFALW,
0765 .name = "vifalw",
0766 .sid = TEGRA194_SID_VI_FALCON,
0767 .regs = {
0768 .sid = {
0769 .override = 0x5e8,
0770 .security = 0x5ec,
0771 },
0772 },
0773 }, {
0774 .id = TEGRA194_MEMORY_CLIENT_DLA0RDA,
0775 .name = "dla0rda",
0776 .sid = TEGRA194_SID_NVDLA0,
0777 .regs = {
0778 .sid = {
0779 .override = 0x5f0,
0780 .security = 0x5f4,
0781 },
0782 },
0783 }, {
0784 .id = TEGRA194_MEMORY_CLIENT_DLA0FALRDB,
0785 .name = "dla0falrdb",
0786 .sid = TEGRA194_SID_NVDLA0,
0787 .regs = {
0788 .sid = {
0789 .override = 0x5f8,
0790 .security = 0x5fc,
0791 },
0792 },
0793 }, {
0794 .id = TEGRA194_MEMORY_CLIENT_DLA0WRA,
0795 .name = "dla0wra",
0796 .sid = TEGRA194_SID_NVDLA0,
0797 .regs = {
0798 .sid = {
0799 .override = 0x600,
0800 .security = 0x604,
0801 },
0802 },
0803 }, {
0804 .id = TEGRA194_MEMORY_CLIENT_DLA0FALWRB,
0805 .name = "dla0falwrb",
0806 .sid = TEGRA194_SID_NVDLA0,
0807 .regs = {
0808 .sid = {
0809 .override = 0x608,
0810 .security = 0x60c,
0811 },
0812 },
0813 }, {
0814 .id = TEGRA194_MEMORY_CLIENT_DLA1RDA,
0815 .name = "dla1rda",
0816 .sid = TEGRA194_SID_NVDLA1,
0817 .regs = {
0818 .sid = {
0819 .override = 0x610,
0820 .security = 0x614,
0821 },
0822 },
0823 }, {
0824 .id = TEGRA194_MEMORY_CLIENT_DLA1FALRDB,
0825 .name = "dla1falrdb",
0826 .sid = TEGRA194_SID_NVDLA1,
0827 .regs = {
0828 .sid = {
0829 .override = 0x618,
0830 .security = 0x61c,
0831 },
0832 },
0833 }, {
0834 .id = TEGRA194_MEMORY_CLIENT_DLA1WRA,
0835 .name = "dla1wra",
0836 .sid = TEGRA194_SID_NVDLA1,
0837 .regs = {
0838 .sid = {
0839 .override = 0x620,
0840 .security = 0x624,
0841 },
0842 },
0843 }, {
0844 .id = TEGRA194_MEMORY_CLIENT_DLA1FALWRB,
0845 .name = "dla1falwrb",
0846 .sid = TEGRA194_SID_NVDLA1,
0847 .regs = {
0848 .sid = {
0849 .override = 0x628,
0850 .security = 0x62c,
0851 },
0852 },
0853 }, {
0854 .id = TEGRA194_MEMORY_CLIENT_PVA0RDA,
0855 .name = "pva0rda",
0856 .sid = TEGRA194_SID_PVA0,
0857 .regs = {
0858 .sid = {
0859 .override = 0x630,
0860 .security = 0x634,
0861 },
0862 },
0863 }, {
0864 .id = TEGRA194_MEMORY_CLIENT_PVA0RDB,
0865 .name = "pva0rdb",
0866 .sid = TEGRA194_SID_PVA0,
0867 .regs = {
0868 .sid = {
0869 .override = 0x638,
0870 .security = 0x63c,
0871 },
0872 },
0873 }, {
0874 .id = TEGRA194_MEMORY_CLIENT_PVA0RDC,
0875 .name = "pva0rdc",
0876 .sid = TEGRA194_SID_PVA0,
0877 .regs = {
0878 .sid = {
0879 .override = 0x640,
0880 .security = 0x644,
0881 },
0882 },
0883 }, {
0884 .id = TEGRA194_MEMORY_CLIENT_PVA0WRA,
0885 .name = "pva0wra",
0886 .sid = TEGRA194_SID_PVA0,
0887 .regs = {
0888 .sid = {
0889 .override = 0x648,
0890 .security = 0x64c,
0891 },
0892 },
0893 }, {
0894 .id = TEGRA194_MEMORY_CLIENT_PVA0WRB,
0895 .name = "pva0wrb",
0896 .sid = TEGRA194_SID_PVA0,
0897 .regs = {
0898 .sid = {
0899 .override = 0x650,
0900 .security = 0x654,
0901 },
0902 },
0903 }, {
0904 .id = TEGRA194_MEMORY_CLIENT_PVA0WRC,
0905 .name = "pva0wrc",
0906 .sid = TEGRA194_SID_PVA0,
0907 .regs = {
0908 .sid = {
0909 .override = 0x658,
0910 .security = 0x65c,
0911 },
0912 },
0913 }, {
0914 .id = TEGRA194_MEMORY_CLIENT_PVA1RDA,
0915 .name = "pva1rda",
0916 .sid = TEGRA194_SID_PVA1,
0917 .regs = {
0918 .sid = {
0919 .override = 0x660,
0920 .security = 0x664,
0921 },
0922 },
0923 }, {
0924 .id = TEGRA194_MEMORY_CLIENT_PVA1RDB,
0925 .name = "pva1rdb",
0926 .sid = TEGRA194_SID_PVA1,
0927 .regs = {
0928 .sid = {
0929 .override = 0x668,
0930 .security = 0x66c,
0931 },
0932 },
0933 }, {
0934 .id = TEGRA194_MEMORY_CLIENT_PVA1RDC,
0935 .name = "pva1rdc",
0936 .sid = TEGRA194_SID_PVA1,
0937 .regs = {
0938 .sid = {
0939 .override = 0x670,
0940 .security = 0x674,
0941 },
0942 },
0943 }, {
0944 .id = TEGRA194_MEMORY_CLIENT_PVA1WRA,
0945 .name = "pva1wra",
0946 .sid = TEGRA194_SID_PVA1,
0947 .regs = {
0948 .sid = {
0949 .override = 0x678,
0950 .security = 0x67c,
0951 },
0952 },
0953 }, {
0954 .id = TEGRA194_MEMORY_CLIENT_PVA1WRB,
0955 .name = "pva1wrb",
0956 .sid = TEGRA194_SID_PVA1,
0957 .regs = {
0958 .sid = {
0959 .override = 0x680,
0960 .security = 0x684,
0961 },
0962 },
0963 }, {
0964 .id = TEGRA194_MEMORY_CLIENT_PVA1WRC,
0965 .name = "pva1wrc",
0966 .sid = TEGRA194_SID_PVA1,
0967 .regs = {
0968 .sid = {
0969 .override = 0x688,
0970 .security = 0x68c,
0971 },
0972 },
0973 }, {
0974 .id = TEGRA194_MEMORY_CLIENT_RCER,
0975 .name = "rcer",
0976 .sid = TEGRA194_SID_RCE,
0977 .regs = {
0978 .sid = {
0979 .override = 0x690,
0980 .security = 0x694,
0981 },
0982 },
0983 }, {
0984 .id = TEGRA194_MEMORY_CLIENT_RCEW,
0985 .name = "rcew",
0986 .sid = TEGRA194_SID_RCE,
0987 .regs = {
0988 .sid = {
0989 .override = 0x698,
0990 .security = 0x69c,
0991 },
0992 },
0993 }, {
0994 .id = TEGRA194_MEMORY_CLIENT_RCEDMAR,
0995 .name = "rcedmar",
0996 .sid = TEGRA194_SID_RCE,
0997 .regs = {
0998 .sid = {
0999 .override = 0x6a0,
1000 .security = 0x6a4,
1001 },
1002 },
1003 }, {
1004 .id = TEGRA194_MEMORY_CLIENT_RCEDMAW,
1005 .name = "rcedmaw",
1006 .sid = TEGRA194_SID_RCE,
1007 .regs = {
1008 .sid = {
1009 .override = 0x6a8,
1010 .security = 0x6ac,
1011 },
1012 },
1013 }, {
1014 .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD,
1015 .name = "nvenc1srd",
1016 .sid = TEGRA194_SID_NVENC1,
1017 .regs = {
1018 .sid = {
1019 .override = 0x6b0,
1020 .security = 0x6b4,
1021 },
1022 },
1023 }, {
1024 .id = TEGRA194_MEMORY_CLIENT_NVENC1SWR,
1025 .name = "nvenc1swr",
1026 .sid = TEGRA194_SID_NVENC1,
1027 .regs = {
1028 .sid = {
1029 .override = 0x6b8,
1030 .security = 0x6bc,
1031 },
1032 },
1033 }, {
1034 .id = TEGRA194_MEMORY_CLIENT_PCIE0R,
1035 .name = "pcie0r",
1036 .sid = TEGRA194_SID_PCIE0,
1037 .regs = {
1038 .sid = {
1039 .override = 0x6c0,
1040 .security = 0x6c4,
1041 },
1042 },
1043 }, {
1044 .id = TEGRA194_MEMORY_CLIENT_PCIE0W,
1045 .name = "pcie0w",
1046 .sid = TEGRA194_SID_PCIE0,
1047 .regs = {
1048 .sid = {
1049 .override = 0x6c8,
1050 .security = 0x6cc,
1051 },
1052 },
1053 }, {
1054 .id = TEGRA194_MEMORY_CLIENT_PCIE1R,
1055 .name = "pcie1r",
1056 .sid = TEGRA194_SID_PCIE1,
1057 .regs = {
1058 .sid = {
1059 .override = 0x6d0,
1060 .security = 0x6d4,
1061 },
1062 },
1063 }, {
1064 .id = TEGRA194_MEMORY_CLIENT_PCIE1W,
1065 .name = "pcie1w",
1066 .sid = TEGRA194_SID_PCIE1,
1067 .regs = {
1068 .sid = {
1069 .override = 0x6d8,
1070 .security = 0x6dc,
1071 },
1072 },
1073 }, {
1074 .id = TEGRA194_MEMORY_CLIENT_PCIE2AR,
1075 .name = "pcie2ar",
1076 .sid = TEGRA194_SID_PCIE2,
1077 .regs = {
1078 .sid = {
1079 .override = 0x6e0,
1080 .security = 0x6e4,
1081 },
1082 },
1083 }, {
1084 .id = TEGRA194_MEMORY_CLIENT_PCIE2AW,
1085 .name = "pcie2aw",
1086 .sid = TEGRA194_SID_PCIE2,
1087 .regs = {
1088 .sid = {
1089 .override = 0x6e8,
1090 .security = 0x6ec,
1091 },
1092 },
1093 }, {
1094 .id = TEGRA194_MEMORY_CLIENT_PCIE3R,
1095 .name = "pcie3r",
1096 .sid = TEGRA194_SID_PCIE3,
1097 .regs = {
1098 .sid = {
1099 .override = 0x6f0,
1100 .security = 0x6f4,
1101 },
1102 },
1103 }, {
1104 .id = TEGRA194_MEMORY_CLIENT_PCIE3W,
1105 .name = "pcie3w",
1106 .sid = TEGRA194_SID_PCIE3,
1107 .regs = {
1108 .sid = {
1109 .override = 0x6f8,
1110 .security = 0x6fc,
1111 },
1112 },
1113 }, {
1114 .id = TEGRA194_MEMORY_CLIENT_PCIE4R,
1115 .name = "pcie4r",
1116 .sid = TEGRA194_SID_PCIE4,
1117 .regs = {
1118 .sid = {
1119 .override = 0x700,
1120 .security = 0x704,
1121 },
1122 },
1123 }, {
1124 .id = TEGRA194_MEMORY_CLIENT_PCIE4W,
1125 .name = "pcie4w",
1126 .sid = TEGRA194_SID_PCIE4,
1127 .regs = {
1128 .sid = {
1129 .override = 0x708,
1130 .security = 0x70c,
1131 },
1132 },
1133 }, {
1134 .id = TEGRA194_MEMORY_CLIENT_PCIE5R,
1135 .name = "pcie5r",
1136 .sid = TEGRA194_SID_PCIE5,
1137 .regs = {
1138 .sid = {
1139 .override = 0x710,
1140 .security = 0x714,
1141 },
1142 },
1143 }, {
1144 .id = TEGRA194_MEMORY_CLIENT_PCIE5W,
1145 .name = "pcie5w",
1146 .sid = TEGRA194_SID_PCIE5,
1147 .regs = {
1148 .sid = {
1149 .override = 0x718,
1150 .security = 0x71c,
1151 },
1152 },
1153 }, {
1154 .id = TEGRA194_MEMORY_CLIENT_ISPFALW,
1155 .name = "ispfalw",
1156 .sid = TEGRA194_SID_ISP_FALCON,
1157 .regs = {
1158 .sid = {
1159 .override = 0x720,
1160 .security = 0x724,
1161 },
1162 },
1163 }, {
1164 .id = TEGRA194_MEMORY_CLIENT_DLA0RDA1,
1165 .name = "dla0rda1",
1166 .sid = TEGRA194_SID_NVDLA0,
1167 .regs = {
1168 .sid = {
1169 .override = 0x748,
1170 .security = 0x74c,
1171 },
1172 },
1173 }, {
1174 .id = TEGRA194_MEMORY_CLIENT_DLA1RDA1,
1175 .name = "dla1rda1",
1176 .sid = TEGRA194_SID_NVDLA1,
1177 .regs = {
1178 .sid = {
1179 .override = 0x750,
1180 .security = 0x754,
1181 },
1182 },
1183 }, {
1184 .id = TEGRA194_MEMORY_CLIENT_PVA0RDA1,
1185 .name = "pva0rda1",
1186 .sid = TEGRA194_SID_PVA0,
1187 .regs = {
1188 .sid = {
1189 .override = 0x758,
1190 .security = 0x75c,
1191 },
1192 },
1193 }, {
1194 .id = TEGRA194_MEMORY_CLIENT_PVA0RDB1,
1195 .name = "pva0rdb1",
1196 .sid = TEGRA194_SID_PVA0,
1197 .regs = {
1198 .sid = {
1199 .override = 0x760,
1200 .security = 0x764,
1201 },
1202 },
1203 }, {
1204 .id = TEGRA194_MEMORY_CLIENT_PVA1RDA1,
1205 .name = "pva1rda1",
1206 .sid = TEGRA194_SID_PVA1,
1207 .regs = {
1208 .sid = {
1209 .override = 0x768,
1210 .security = 0x76c,
1211 },
1212 },
1213 }, {
1214 .id = TEGRA194_MEMORY_CLIENT_PVA1RDB1,
1215 .name = "pva1rdb1",
1216 .sid = TEGRA194_SID_PVA1,
1217 .regs = {
1218 .sid = {
1219 .override = 0x770,
1220 .security = 0x774,
1221 },
1222 },
1223 }, {
1224 .id = TEGRA194_MEMORY_CLIENT_PCIE5R1,
1225 .name = "pcie5r1",
1226 .sid = TEGRA194_SID_PCIE5,
1227 .regs = {
1228 .sid = {
1229 .override = 0x778,
1230 .security = 0x77c,
1231 },
1232 },
1233 }, {
1234 .id = TEGRA194_MEMORY_CLIENT_NVENCSRD1,
1235 .name = "nvencsrd1",
1236 .sid = TEGRA194_SID_NVENC,
1237 .regs = {
1238 .sid = {
1239 .override = 0x780,
1240 .security = 0x784,
1241 },
1242 },
1243 }, {
1244 .id = TEGRA194_MEMORY_CLIENT_NVENC1SRD1,
1245 .name = "nvenc1srd1",
1246 .sid = TEGRA194_SID_NVENC1,
1247 .regs = {
1248 .sid = {
1249 .override = 0x788,
1250 .security = 0x78c,
1251 },
1252 },
1253 }, {
1254 .id = TEGRA194_MEMORY_CLIENT_ISPRA1,
1255 .name = "ispra1",
1256 .sid = TEGRA194_SID_ISP,
1257 .regs = {
1258 .sid = {
1259 .override = 0x790,
1260 .security = 0x794,
1261 },
1262 },
1263 }, {
1264 .id = TEGRA194_MEMORY_CLIENT_PCIE0R1,
1265 .name = "pcie0r1",
1266 .sid = TEGRA194_SID_PCIE0,
1267 .regs = {
1268 .sid = {
1269 .override = 0x798,
1270 .security = 0x79c,
1271 },
1272 },
1273 }, {
1274 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD,
1275 .name = "nvdec1srd",
1276 .sid = TEGRA194_SID_NVDEC1,
1277 .regs = {
1278 .sid = {
1279 .override = 0x7c8,
1280 .security = 0x7cc,
1281 },
1282 },
1283 }, {
1284 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SRD1,
1285 .name = "nvdec1srd1",
1286 .sid = TEGRA194_SID_NVDEC1,
1287 .regs = {
1288 .sid = {
1289 .override = 0x7d0,
1290 .security = 0x7d4,
1291 },
1292 },
1293 }, {
1294 .id = TEGRA194_MEMORY_CLIENT_NVDEC1SWR,
1295 .name = "nvdec1swr",
1296 .sid = TEGRA194_SID_NVDEC1,
1297 .regs = {
1298 .sid = {
1299 .override = 0x7d8,
1300 .security = 0x7dc,
1301 },
1302 },
1303 }, {
1304 .id = TEGRA194_MEMORY_CLIENT_MIU5R,
1305 .name = "miu5r",
1306 .sid = TEGRA194_SID_MIU,
1307 .regs = {
1308 .sid = {
1309 .override = 0x7e0,
1310 .security = 0x7e4,
1311 },
1312 },
1313 }, {
1314 .id = TEGRA194_MEMORY_CLIENT_MIU5W,
1315 .name = "miu5w",
1316 .sid = TEGRA194_SID_MIU,
1317 .regs = {
1318 .sid = {
1319 .override = 0x7e8,
1320 .security = 0x7ec,
1321 },
1322 },
1323 }, {
1324 .id = TEGRA194_MEMORY_CLIENT_MIU6R,
1325 .name = "miu6r",
1326 .sid = TEGRA194_SID_MIU,
1327 .regs = {
1328 .sid = {
1329 .override = 0x7f0,
1330 .security = 0x7f4,
1331 },
1332 },
1333 }, {
1334 .id = TEGRA194_MEMORY_CLIENT_MIU6W,
1335 .name = "miu6w",
1336 .sid = TEGRA194_SID_MIU,
1337 .regs = {
1338 .sid = {
1339 .override = 0x7f8,
1340 .security = 0x7fc,
1341 },
1342 },
1343 },
1344 };
1345
1346 const struct tegra_mc_soc tegra194_mc_soc = {
1347 .num_clients = ARRAY_SIZE(tegra194_mc_clients),
1348 .clients = tegra194_mc_clients,
1349 .num_address_bits = 40,
1350 .num_channels = 16,
1351 .client_id_mask = 0xff,
1352 .intmask = MC_INT_DECERR_ROUTE_SANITY |
1353 MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
1354 MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1355 MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1356 .has_addr_hi_reg = true,
1357 .ops = &tegra186_mc_ops,
1358 .ch_intmask = 0x00000f00,
1359 .global_intstatus_channel_shift = 8,
1360 };
