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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2017-2021 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/io.h>
0007 #include <linux/iommu.h>
0008 #include <linux/module.h>
0009 #include <linux/mod_devicetable.h>
0010 #include <linux/of_device.h>
0011 #include <linux/platform_device.h>
0012 
0013 #include <soc/tegra/mc.h>
0014 
0015 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
0016 #include <dt-bindings/memory/tegra186-mc.h>
0017 #endif
0018 
0019 #include "mc.h"
0020 
0021 #define MC_SID_STREAMID_OVERRIDE_MASK GENMASK(7, 0)
0022 #define MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED BIT(16)
0023 #define MC_SID_STREAMID_SECURITY_OVERRIDE BIT(8)
0024 
0025 static void tegra186_mc_program_sid(struct tegra_mc *mc)
0026 {
0027     unsigned int i;
0028 
0029     for (i = 0; i < mc->soc->num_clients; i++) {
0030         const struct tegra_mc_client *client = &mc->soc->clients[i];
0031         u32 override, security;
0032 
0033         override = readl(mc->regs + client->regs.sid.override);
0034         security = readl(mc->regs + client->regs.sid.security);
0035 
0036         dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
0037             client->name, override, security);
0038 
0039         dev_dbg(mc->dev, "setting SID %u for %s\n", client->sid,
0040             client->name);
0041         writel(client->sid, mc->regs + client->regs.sid.override);
0042 
0043         override = readl(mc->regs + client->regs.sid.override);
0044         security = readl(mc->regs + client->regs.sid.security);
0045 
0046         dev_dbg(mc->dev, "client %s: override: %x security: %x\n",
0047             client->name, override, security);
0048     }
0049 }
0050 
0051 static int tegra186_mc_probe(struct tegra_mc *mc)
0052 {
0053     struct platform_device *pdev = to_platform_device(mc->dev);
0054     unsigned int i;
0055     char name[8];
0056     int err;
0057 
0058     mc->bcast_ch_regs = devm_platform_ioremap_resource_byname(pdev, "broadcast");
0059     if (IS_ERR(mc->bcast_ch_regs)) {
0060         if (PTR_ERR(mc->bcast_ch_regs) == -EINVAL) {
0061             dev_warn(&pdev->dev,
0062                  "Broadcast channel is missing, please update your device-tree\n");
0063             mc->bcast_ch_regs = NULL;
0064             goto populate;
0065         }
0066 
0067         return PTR_ERR(mc->bcast_ch_regs);
0068     }
0069 
0070     mc->ch_regs = devm_kcalloc(mc->dev, mc->soc->num_channels, sizeof(*mc->ch_regs),
0071                    GFP_KERNEL);
0072     if (!mc->ch_regs)
0073         return -ENOMEM;
0074 
0075     for (i = 0; i < mc->soc->num_channels; i++) {
0076         snprintf(name, sizeof(name), "ch%u", i);
0077 
0078         mc->ch_regs[i] = devm_platform_ioremap_resource_byname(pdev, name);
0079         if (IS_ERR(mc->ch_regs[i]))
0080             return PTR_ERR(mc->ch_regs[i]);
0081     }
0082 
0083 populate:
0084     err = of_platform_populate(mc->dev->of_node, NULL, NULL, mc->dev);
0085     if (err < 0)
0086         return err;
0087 
0088     tegra186_mc_program_sid(mc);
0089 
0090     return 0;
0091 }
0092 
0093 static void tegra186_mc_remove(struct tegra_mc *mc)
0094 {
0095     of_platform_depopulate(mc->dev);
0096 }
0097 
0098 static int tegra186_mc_resume(struct tegra_mc *mc)
0099 {
0100     tegra186_mc_program_sid(mc);
0101 
0102     return 0;
0103 }
0104 
0105 #if IS_ENABLED(CONFIG_IOMMU_API)
0106 static void tegra186_mc_client_sid_override(struct tegra_mc *mc,
0107                         const struct tegra_mc_client *client,
0108                         unsigned int sid)
0109 {
0110     u32 value, old;
0111 
0112     value = readl(mc->regs + client->regs.sid.security);
0113     if ((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0) {
0114         /*
0115          * If the secure firmware has locked this down the override
0116          * for this memory client, there's nothing we can do here.
0117          */
0118         if (value & MC_SID_STREAMID_SECURITY_WRITE_ACCESS_DISABLED)
0119             return;
0120 
0121         /*
0122          * Otherwise, try to set the override itself. Typically the
0123          * secure firmware will never have set this configuration.
0124          * Instead, it will either have disabled write access to
0125          * this field, or it will already have set an explicit
0126          * override itself.
0127          */
0128         WARN_ON((value & MC_SID_STREAMID_SECURITY_OVERRIDE) == 0);
0129 
0130         value |= MC_SID_STREAMID_SECURITY_OVERRIDE;
0131         writel(value, mc->regs + client->regs.sid.security);
0132     }
0133 
0134     value = readl(mc->regs + client->regs.sid.override);
0135     old = value & MC_SID_STREAMID_OVERRIDE_MASK;
0136 
0137     if (old != sid) {
0138         dev_dbg(mc->dev, "overriding SID %x for %s with %x\n", old,
0139             client->name, sid);
0140         writel(sid, mc->regs + client->regs.sid.override);
0141     }
0142 }
0143 #endif
0144 
0145 static int tegra186_mc_probe_device(struct tegra_mc *mc, struct device *dev)
0146 {
0147 #if IS_ENABLED(CONFIG_IOMMU_API)
0148     struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
0149     struct of_phandle_args args;
0150     unsigned int i, index = 0;
0151 
0152     while (!of_parse_phandle_with_args(dev->of_node, "interconnects", "#interconnect-cells",
0153                        index, &args)) {
0154         if (args.np == mc->dev->of_node && args.args_count != 0) {
0155             for (i = 0; i < mc->soc->num_clients; i++) {
0156                 const struct tegra_mc_client *client = &mc->soc->clients[i];
0157 
0158                 if (client->id == args.args[0]) {
0159                     u32 sid = fwspec->ids[0] & MC_SID_STREAMID_OVERRIDE_MASK;
0160 
0161                     tegra186_mc_client_sid_override(mc, client, sid);
0162                 }
0163             }
0164         }
0165 
0166         index++;
0167     }
0168 #endif
0169 
0170     return 0;
0171 }
0172 
0173 const struct tegra_mc_ops tegra186_mc_ops = {
0174     .probe = tegra186_mc_probe,
0175     .remove = tegra186_mc_remove,
0176     .resume = tegra186_mc_resume,
0177     .probe_device = tegra186_mc_probe_device,
0178     .handle_irq = tegra30_mc_handle_irq,
0179 };
0180 
0181 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
0182 static const struct tegra_mc_client tegra186_mc_clients[] = {
0183     {
0184         .id = TEGRA186_MEMORY_CLIENT_PTCR,
0185         .name = "ptcr",
0186         .sid = TEGRA186_SID_PASSTHROUGH,
0187         .regs = {
0188             .sid = {
0189                 .override = 0x000,
0190                 .security = 0x004,
0191             },
0192         },
0193     }, {
0194         .id = TEGRA186_MEMORY_CLIENT_AFIR,
0195         .name = "afir",
0196         .sid = TEGRA186_SID_AFI,
0197         .regs = {
0198             .sid = {
0199                 .override = 0x070,
0200                 .security = 0x074,
0201             },
0202         },
0203     }, {
0204         .id = TEGRA186_MEMORY_CLIENT_HDAR,
0205         .name = "hdar",
0206         .sid = TEGRA186_SID_HDA,
0207         .regs = {
0208             .sid = {
0209                 .override = 0x0a8,
0210                 .security = 0x0ac,
0211             },
0212         },
0213     }, {
0214         .id = TEGRA186_MEMORY_CLIENT_HOST1XDMAR,
0215         .name = "host1xdmar",
0216         .sid = TEGRA186_SID_HOST1X,
0217         .regs = {
0218             .sid = {
0219                 .override = 0x0b0,
0220                 .security = 0x0b4,
0221             },
0222         },
0223     }, {
0224         .id = TEGRA186_MEMORY_CLIENT_NVENCSRD,
0225         .name = "nvencsrd",
0226         .sid = TEGRA186_SID_NVENC,
0227         .regs = {
0228             .sid = {
0229                 .override = 0x0e0,
0230                 .security = 0x0e4,
0231             },
0232         },
0233     }, {
0234         .id = TEGRA186_MEMORY_CLIENT_SATAR,
0235         .name = "satar",
0236         .sid = TEGRA186_SID_SATA,
0237         .regs = {
0238             .sid = {
0239                 .override = 0x0f8,
0240                 .security = 0x0fc,
0241             },
0242         },
0243     }, {
0244         .id = TEGRA186_MEMORY_CLIENT_MPCORER,
0245         .name = "mpcorer",
0246         .sid = TEGRA186_SID_PASSTHROUGH,
0247         .regs = {
0248             .sid = {
0249                 .override = 0x138,
0250                 .security = 0x13c,
0251             },
0252         },
0253     }, {
0254         .id = TEGRA186_MEMORY_CLIENT_NVENCSWR,
0255         .name = "nvencswr",
0256         .sid = TEGRA186_SID_NVENC,
0257         .regs = {
0258             .sid = {
0259                 .override = 0x158,
0260                 .security = 0x15c,
0261             },
0262         },
0263     }, {
0264         .id = TEGRA186_MEMORY_CLIENT_AFIW,
0265         .name = "afiw",
0266         .sid = TEGRA186_SID_AFI,
0267         .regs = {
0268             .sid = {
0269                 .override = 0x188,
0270                 .security = 0x18c,
0271             },
0272         },
0273     }, {
0274         .id = TEGRA186_MEMORY_CLIENT_HDAW,
0275         .name = "hdaw",
0276         .sid = TEGRA186_SID_HDA,
0277         .regs = {
0278             .sid = {
0279                 .override = 0x1a8,
0280                 .security = 0x1ac,
0281             },
0282         },
0283     }, {
0284         .id = TEGRA186_MEMORY_CLIENT_MPCOREW,
0285         .name = "mpcorew",
0286         .sid = TEGRA186_SID_PASSTHROUGH,
0287         .regs = {
0288             .sid = {
0289                 .override = 0x1c8,
0290                 .security = 0x1cc,
0291             },
0292         },
0293     }, {
0294         .id = TEGRA186_MEMORY_CLIENT_SATAW,
0295         .name = "sataw",
0296         .sid = TEGRA186_SID_SATA,
0297         .regs = {
0298             .sid = {
0299                 .override = 0x1e8,
0300                 .security = 0x1ec,
0301             },
0302         },
0303     }, {
0304         .id = TEGRA186_MEMORY_CLIENT_ISPRA,
0305         .name = "ispra",
0306         .sid = TEGRA186_SID_ISP,
0307         .regs = {
0308             .sid = {
0309                 .override = 0x220,
0310                 .security = 0x224,
0311             },
0312         },
0313     }, {
0314         .id = TEGRA186_MEMORY_CLIENT_ISPWA,
0315         .name = "ispwa",
0316         .sid = TEGRA186_SID_ISP,
0317         .regs = {
0318             .sid = {
0319                 .override = 0x230,
0320                 .security = 0x234,
0321             },
0322         },
0323     }, {
0324         .id = TEGRA186_MEMORY_CLIENT_ISPWB,
0325         .name = "ispwb",
0326         .sid = TEGRA186_SID_ISP,
0327         .regs = {
0328             .sid = {
0329                 .override = 0x238,
0330                 .security = 0x23c,
0331             },
0332         },
0333     }, {
0334         .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTR,
0335         .name = "xusb_hostr",
0336         .sid = TEGRA186_SID_XUSB_HOST,
0337         .regs = {
0338             .sid = {
0339                 .override = 0x250,
0340                 .security = 0x254,
0341             },
0342         },
0343     }, {
0344         .id = TEGRA186_MEMORY_CLIENT_XUSB_HOSTW,
0345         .name = "xusb_hostw",
0346         .sid = TEGRA186_SID_XUSB_HOST,
0347         .regs = {
0348             .sid = {
0349                 .override = 0x258,
0350                 .security = 0x25c,
0351             },
0352         },
0353     }, {
0354         .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVR,
0355         .name = "xusb_devr",
0356         .sid = TEGRA186_SID_XUSB_DEV,
0357         .regs = {
0358             .sid = {
0359                 .override = 0x260,
0360                 .security = 0x264,
0361             },
0362         },
0363     }, {
0364         .id = TEGRA186_MEMORY_CLIENT_XUSB_DEVW,
0365         .name = "xusb_devw",
0366         .sid = TEGRA186_SID_XUSB_DEV,
0367         .regs = {
0368             .sid = {
0369                 .override = 0x268,
0370                 .security = 0x26c,
0371             },
0372         },
0373     }, {
0374         .id = TEGRA186_MEMORY_CLIENT_TSECSRD,
0375         .name = "tsecsrd",
0376         .sid = TEGRA186_SID_TSEC,
0377         .regs = {
0378             .sid = {
0379                 .override = 0x2a0,
0380                 .security = 0x2a4,
0381             },
0382         },
0383     }, {
0384         .id = TEGRA186_MEMORY_CLIENT_TSECSWR,
0385         .name = "tsecswr",
0386         .sid = TEGRA186_SID_TSEC,
0387         .regs = {
0388             .sid = {
0389                 .override = 0x2a8,
0390                 .security = 0x2ac,
0391             },
0392         },
0393     }, {
0394         .id = TEGRA186_MEMORY_CLIENT_GPUSRD,
0395         .name = "gpusrd",
0396         .sid = TEGRA186_SID_GPU,
0397         .regs = {
0398             .sid = {
0399                 .override = 0x2c0,
0400                 .security = 0x2c4,
0401             },
0402         },
0403     }, {
0404         .id = TEGRA186_MEMORY_CLIENT_GPUSWR,
0405         .name = "gpuswr",
0406         .sid = TEGRA186_SID_GPU,
0407         .regs = {
0408             .sid = {
0409                 .override = 0x2c8,
0410                 .security = 0x2cc,
0411             },
0412         },
0413     }, {
0414         .id = TEGRA186_MEMORY_CLIENT_SDMMCRA,
0415         .name = "sdmmcra",
0416         .sid = TEGRA186_SID_SDMMC1,
0417         .regs = {
0418             .sid = {
0419                 .override = 0x300,
0420                 .security = 0x304,
0421             },
0422         },
0423     }, {
0424         .id = TEGRA186_MEMORY_CLIENT_SDMMCRAA,
0425         .name = "sdmmcraa",
0426         .sid = TEGRA186_SID_SDMMC2,
0427         .regs = {
0428             .sid = {
0429                 .override = 0x308,
0430                 .security = 0x30c,
0431             },
0432         },
0433     }, {
0434         .id = TEGRA186_MEMORY_CLIENT_SDMMCR,
0435         .name = "sdmmcr",
0436         .sid = TEGRA186_SID_SDMMC3,
0437         .regs = {
0438             .sid = {
0439                 .override = 0x310,
0440                 .security = 0x314,
0441             },
0442         },
0443     }, {
0444         .id = TEGRA186_MEMORY_CLIENT_SDMMCRAB,
0445         .name = "sdmmcrab",
0446         .sid = TEGRA186_SID_SDMMC4,
0447         .regs = {
0448             .sid = {
0449                 .override = 0x318,
0450                 .security = 0x31c,
0451             },
0452         },
0453     }, {
0454         .id = TEGRA186_MEMORY_CLIENT_SDMMCWA,
0455         .name = "sdmmcwa",
0456         .sid = TEGRA186_SID_SDMMC1,
0457         .regs = {
0458             .sid = {
0459                 .override = 0x320,
0460                 .security = 0x324,
0461             },
0462         },
0463     }, {
0464         .id = TEGRA186_MEMORY_CLIENT_SDMMCWAA,
0465         .name = "sdmmcwaa",
0466         .sid = TEGRA186_SID_SDMMC2,
0467         .regs = {
0468             .sid = {
0469                 .override = 0x328,
0470                 .security = 0x32c,
0471             },
0472         },
0473     }, {
0474         .id = TEGRA186_MEMORY_CLIENT_SDMMCW,
0475         .name = "sdmmcw",
0476         .sid = TEGRA186_SID_SDMMC3,
0477         .regs = {
0478             .sid = {
0479                 .override = 0x330,
0480                 .security = 0x334,
0481             },
0482         },
0483     }, {
0484         .id = TEGRA186_MEMORY_CLIENT_SDMMCWAB,
0485         .name = "sdmmcwab",
0486         .sid = TEGRA186_SID_SDMMC4,
0487         .regs = {
0488             .sid = {
0489                 .override = 0x338,
0490                 .security = 0x33c,
0491             },
0492         },
0493     }, {
0494         .id = TEGRA186_MEMORY_CLIENT_VICSRD,
0495         .name = "vicsrd",
0496         .sid = TEGRA186_SID_VIC,
0497         .regs = {
0498             .sid = {
0499                 .override = 0x360,
0500                 .security = 0x364,
0501             },
0502         },
0503     }, {
0504         .id = TEGRA186_MEMORY_CLIENT_VICSWR,
0505         .name = "vicswr",
0506         .sid = TEGRA186_SID_VIC,
0507         .regs = {
0508             .sid = {
0509                 .override = 0x368,
0510                 .security = 0x36c,
0511             },
0512         },
0513     }, {
0514         .id = TEGRA186_MEMORY_CLIENT_VIW,
0515         .name = "viw",
0516         .sid = TEGRA186_SID_VI,
0517         .regs = {
0518             .sid = {
0519                 .override = 0x390,
0520                 .security = 0x394,
0521             },
0522         },
0523     }, {
0524         .id = TEGRA186_MEMORY_CLIENT_NVDECSRD,
0525         .name = "nvdecsrd",
0526         .sid = TEGRA186_SID_NVDEC,
0527         .regs = {
0528             .sid = {
0529                 .override = 0x3c0,
0530                 .security = 0x3c4,
0531             },
0532         },
0533     }, {
0534         .id = TEGRA186_MEMORY_CLIENT_NVDECSWR,
0535         .name = "nvdecswr",
0536         .sid = TEGRA186_SID_NVDEC,
0537         .regs = {
0538             .sid = {
0539                 .override = 0x3c8,
0540                 .security = 0x3cc,
0541             },
0542         },
0543     }, {
0544         .id = TEGRA186_MEMORY_CLIENT_APER,
0545         .name = "aper",
0546         .sid = TEGRA186_SID_APE,
0547         .regs = {
0548             .sid = {
0549                 .override = 0x3d0,
0550                 .security = 0x3d4,
0551             },
0552         },
0553     }, {
0554         .id = TEGRA186_MEMORY_CLIENT_APEW,
0555         .name = "apew",
0556         .sid = TEGRA186_SID_APE,
0557         .regs = {
0558             .sid = {
0559                 .override = 0x3d8,
0560                 .security = 0x3dc,
0561             },
0562         },
0563     }, {
0564         .id = TEGRA186_MEMORY_CLIENT_NVJPGSRD,
0565         .name = "nvjpgsrd",
0566         .sid = TEGRA186_SID_NVJPG,
0567         .regs = {
0568             .sid = {
0569                 .override = 0x3f0,
0570                 .security = 0x3f4,
0571             },
0572         },
0573     }, {
0574         .id = TEGRA186_MEMORY_CLIENT_NVJPGSWR,
0575         .name = "nvjpgswr",
0576         .sid = TEGRA186_SID_NVJPG,
0577         .regs = {
0578             .sid = {
0579                 .override = 0x3f8,
0580                 .security = 0x3fc,
0581             },
0582         },
0583     }, {
0584         .id = TEGRA186_MEMORY_CLIENT_SESRD,
0585         .name = "sesrd",
0586         .sid = TEGRA186_SID_SE,
0587         .regs = {
0588             .sid = {
0589                 .override = 0x400,
0590                 .security = 0x404,
0591             },
0592         },
0593     }, {
0594         .id = TEGRA186_MEMORY_CLIENT_SESWR,
0595         .name = "seswr",
0596         .sid = TEGRA186_SID_SE,
0597         .regs = {
0598             .sid = {
0599                 .override = 0x408,
0600                 .security = 0x40c,
0601             },
0602         },
0603     }, {
0604         .id = TEGRA186_MEMORY_CLIENT_ETRR,
0605         .name = "etrr",
0606         .sid = TEGRA186_SID_ETR,
0607         .regs = {
0608             .sid = {
0609                 .override = 0x420,
0610                 .security = 0x424,
0611             },
0612         },
0613     }, {
0614         .id = TEGRA186_MEMORY_CLIENT_ETRW,
0615         .name = "etrw",
0616         .sid = TEGRA186_SID_ETR,
0617         .regs = {
0618             .sid = {
0619                 .override = 0x428,
0620                 .security = 0x42c,
0621             },
0622         },
0623     }, {
0624         .id = TEGRA186_MEMORY_CLIENT_TSECSRDB,
0625         .name = "tsecsrdb",
0626         .sid = TEGRA186_SID_TSECB,
0627         .regs = {
0628             .sid = {
0629                 .override = 0x430,
0630                 .security = 0x434,
0631             },
0632         },
0633     }, {
0634         .id = TEGRA186_MEMORY_CLIENT_TSECSWRB,
0635         .name = "tsecswrb",
0636         .sid = TEGRA186_SID_TSECB,
0637         .regs = {
0638             .sid = {
0639                 .override = 0x438,
0640                 .security = 0x43c,
0641             },
0642         },
0643     }, {
0644         .id = TEGRA186_MEMORY_CLIENT_GPUSRD2,
0645         .name = "gpusrd2",
0646         .sid = TEGRA186_SID_GPU,
0647         .regs = {
0648             .sid = {
0649                 .override = 0x440,
0650                 .security = 0x444,
0651             },
0652         },
0653     }, {
0654         .id = TEGRA186_MEMORY_CLIENT_GPUSWR2,
0655         .name = "gpuswr2",
0656         .sid = TEGRA186_SID_GPU,
0657         .regs = {
0658             .sid = {
0659                 .override = 0x448,
0660                 .security = 0x44c,
0661             },
0662         },
0663     }, {
0664         .id = TEGRA186_MEMORY_CLIENT_AXISR,
0665         .name = "axisr",
0666         .sid = TEGRA186_SID_GPCDMA_0,
0667         .regs = {
0668             .sid = {
0669                 .override = 0x460,
0670                 .security = 0x464,
0671             },
0672         },
0673     }, {
0674         .id = TEGRA186_MEMORY_CLIENT_AXISW,
0675         .name = "axisw",
0676         .sid = TEGRA186_SID_GPCDMA_0,
0677         .regs = {
0678             .sid = {
0679                 .override = 0x468,
0680                 .security = 0x46c,
0681             },
0682         },
0683     }, {
0684         .id = TEGRA186_MEMORY_CLIENT_EQOSR,
0685         .name = "eqosr",
0686         .sid = TEGRA186_SID_EQOS,
0687         .regs = {
0688             .sid = {
0689                 .override = 0x470,
0690                 .security = 0x474,
0691             },
0692         },
0693     }, {
0694         .id = TEGRA186_MEMORY_CLIENT_EQOSW,
0695         .name = "eqosw",
0696         .sid = TEGRA186_SID_EQOS,
0697         .regs = {
0698             .sid = {
0699                 .override = 0x478,
0700                 .security = 0x47c,
0701             },
0702         },
0703     }, {
0704         .id = TEGRA186_MEMORY_CLIENT_UFSHCR,
0705         .name = "ufshcr",
0706         .sid = TEGRA186_SID_UFSHC,
0707         .regs = {
0708             .sid = {
0709                 .override = 0x480,
0710                 .security = 0x484,
0711             },
0712         },
0713     }, {
0714         .id = TEGRA186_MEMORY_CLIENT_UFSHCW,
0715         .name = "ufshcw",
0716         .sid = TEGRA186_SID_UFSHC,
0717         .regs = {
0718             .sid = {
0719                 .override = 0x488,
0720                 .security = 0x48c,
0721             },
0722         },
0723     }, {
0724         .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR,
0725         .name = "nvdisplayr",
0726         .sid = TEGRA186_SID_NVDISPLAY,
0727         .regs = {
0728             .sid = {
0729                 .override = 0x490,
0730                 .security = 0x494,
0731             },
0732         },
0733     }, {
0734         .id = TEGRA186_MEMORY_CLIENT_BPMPR,
0735         .name = "bpmpr",
0736         .sid = TEGRA186_SID_BPMP,
0737         .regs = {
0738             .sid = {
0739                 .override = 0x498,
0740                 .security = 0x49c,
0741             },
0742         },
0743     }, {
0744         .id = TEGRA186_MEMORY_CLIENT_BPMPW,
0745         .name = "bpmpw",
0746         .sid = TEGRA186_SID_BPMP,
0747         .regs = {
0748             .sid = {
0749                 .override = 0x4a0,
0750                 .security = 0x4a4,
0751             },
0752         },
0753     }, {
0754         .id = TEGRA186_MEMORY_CLIENT_BPMPDMAR,
0755         .name = "bpmpdmar",
0756         .sid = TEGRA186_SID_BPMP,
0757         .regs = {
0758             .sid = {
0759                 .override = 0x4a8,
0760                 .security = 0x4ac,
0761             },
0762         },
0763     }, {
0764         .id = TEGRA186_MEMORY_CLIENT_BPMPDMAW,
0765         .name = "bpmpdmaw",
0766         .sid = TEGRA186_SID_BPMP,
0767         .regs = {
0768             .sid = {
0769                 .override = 0x4b0,
0770                 .security = 0x4b4,
0771             },
0772         },
0773     }, {
0774         .id = TEGRA186_MEMORY_CLIENT_AONR,
0775         .name = "aonr",
0776         .sid = TEGRA186_SID_AON,
0777         .regs = {
0778             .sid = {
0779                 .override = 0x4b8,
0780                 .security = 0x4bc,
0781             },
0782         },
0783     }, {
0784         .id = TEGRA186_MEMORY_CLIENT_AONW,
0785         .name = "aonw",
0786         .sid = TEGRA186_SID_AON,
0787         .regs = {
0788             .sid = {
0789                 .override = 0x4c0,
0790                 .security = 0x4c4,
0791             },
0792         },
0793     }, {
0794         .id = TEGRA186_MEMORY_CLIENT_AONDMAR,
0795         .name = "aondmar",
0796         .sid = TEGRA186_SID_AON,
0797         .regs = {
0798             .sid = {
0799                 .override = 0x4c8,
0800                 .security = 0x4cc,
0801             },
0802         },
0803     }, {
0804         .id = TEGRA186_MEMORY_CLIENT_AONDMAW,
0805         .name = "aondmaw",
0806         .sid = TEGRA186_SID_AON,
0807         .regs = {
0808             .sid = {
0809                 .override = 0x4d0,
0810                 .security = 0x4d4,
0811             },
0812         },
0813     }, {
0814         .id = TEGRA186_MEMORY_CLIENT_SCER,
0815         .name = "scer",
0816         .sid = TEGRA186_SID_SCE,
0817         .regs = {
0818             .sid = {
0819                 .override = 0x4d8,
0820                 .security = 0x4dc,
0821             },
0822         },
0823     }, {
0824         .id = TEGRA186_MEMORY_CLIENT_SCEW,
0825         .name = "scew",
0826         .sid = TEGRA186_SID_SCE,
0827         .regs = {
0828             .sid = {
0829                 .override = 0x4e0,
0830                 .security = 0x4e4,
0831             },
0832         },
0833     }, {
0834         .id = TEGRA186_MEMORY_CLIENT_SCEDMAR,
0835         .name = "scedmar",
0836         .sid = TEGRA186_SID_SCE,
0837         .regs = {
0838             .sid = {
0839                 .override = 0x4e8,
0840                 .security = 0x4ec,
0841             },
0842         },
0843     }, {
0844         .id = TEGRA186_MEMORY_CLIENT_SCEDMAW,
0845         .name = "scedmaw",
0846         .sid = TEGRA186_SID_SCE,
0847         .regs = {
0848             .sid = {
0849                 .override = 0x4f0,
0850                 .security = 0x4f4,
0851             },
0852         },
0853     }, {
0854         .id = TEGRA186_MEMORY_CLIENT_APEDMAR,
0855         .name = "apedmar",
0856         .sid = TEGRA186_SID_APE,
0857         .regs = {
0858             .sid = {
0859                 .override = 0x4f8,
0860                 .security = 0x4fc,
0861             },
0862         },
0863     }, {
0864         .id = TEGRA186_MEMORY_CLIENT_APEDMAW,
0865         .name = "apedmaw",
0866         .sid = TEGRA186_SID_APE,
0867         .regs = {
0868             .sid = {
0869                 .override = 0x500,
0870                 .security = 0x504,
0871             },
0872         },
0873     }, {
0874         .id = TEGRA186_MEMORY_CLIENT_NVDISPLAYR1,
0875         .name = "nvdisplayr1",
0876         .sid = TEGRA186_SID_NVDISPLAY,
0877         .regs = {
0878             .sid = {
0879                 .override = 0x508,
0880                 .security = 0x50c,
0881             },
0882         },
0883     }, {
0884         .id = TEGRA186_MEMORY_CLIENT_VICSRD1,
0885         .name = "vicsrd1",
0886         .sid = TEGRA186_SID_VIC,
0887         .regs = {
0888             .sid = {
0889                 .override = 0x510,
0890                 .security = 0x514,
0891             },
0892         },
0893     }, {
0894         .id = TEGRA186_MEMORY_CLIENT_NVDECSRD1,
0895         .name = "nvdecsrd1",
0896         .sid = TEGRA186_SID_NVDEC,
0897         .regs = {
0898             .sid = {
0899                 .override = 0x518,
0900                 .security = 0x51c,
0901             },
0902         },
0903     },
0904 };
0905 
0906 const struct tegra_mc_soc tegra186_mc_soc = {
0907     .num_clients = ARRAY_SIZE(tegra186_mc_clients),
0908     .clients = tegra186_mc_clients,
0909     .num_address_bits = 40,
0910     .num_channels = 4,
0911     .client_id_mask = 0xff,
0912     .intmask = MC_INT_DECERR_GENERALIZED_CARVEOUT | MC_INT_DECERR_MTS |
0913            MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
0914            MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
0915     .ops = &tegra186_mc_ops,
0916     .ch_intmask = 0x0000000f,
0917     .global_intstatus_channel_shift = 0,
0918 };
0919 #endif
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