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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/of.h>
0007 #include <linux/of_device.h>
0008 #include <linux/slab.h>
0009 
0010 #include <dt-bindings/memory/tegra124-mc.h>
0011 
0012 #include "mc.h"
0013 
0014 static const struct tegra_mc_client tegra124_mc_clients[] = {
0015     {
0016         .id = 0x00,
0017         .name = "ptcr",
0018         .swgroup = TEGRA_SWGROUP_PTC,
0019         .regs = {
0020             .la = {
0021                 .reg = 0x34c,
0022                 .shift = 0,
0023                 .mask = 0xff,
0024                 .def = 0x0,
0025             },
0026         },
0027     }, {
0028         .id = 0x01,
0029         .name = "display0a",
0030         .swgroup = TEGRA_SWGROUP_DC,
0031         .regs = {
0032             .smmu = {
0033                 .reg = 0x228,
0034                 .bit = 1,
0035             },
0036             .la = {
0037                 .reg = 0x2e8,
0038                 .shift = 0,
0039                 .mask = 0xff,
0040                 .def = 0xc2,
0041             },
0042         },
0043     }, {
0044         .id = 0x02,
0045         .name = "display0ab",
0046         .swgroup = TEGRA_SWGROUP_DCB,
0047         .regs = {
0048             .smmu = {
0049                 .reg = 0x228,
0050                 .bit = 2,
0051             },
0052             .la = {
0053                 .reg = 0x2f4,
0054                 .shift = 0,
0055                 .mask = 0xff,
0056                 .def = 0xc6,
0057             },
0058         },
0059     }, {
0060         .id = 0x03,
0061         .name = "display0b",
0062         .swgroup = TEGRA_SWGROUP_DC,
0063         .regs = {
0064             .smmu = {
0065                 .reg = 0x228,
0066                 .bit = 3,
0067             },
0068             .la = {
0069                 .reg = 0x2e8,
0070                 .shift = 16,
0071                 .mask = 0xff,
0072                 .def = 0x50,
0073             },
0074         },
0075     }, {
0076         .id = 0x04,
0077         .name = "display0bb",
0078         .swgroup = TEGRA_SWGROUP_DCB,
0079         .regs = {
0080             .smmu = {
0081                 .reg = 0x228,
0082                 .bit = 4,
0083             },
0084             .la = {
0085                 .reg = 0x2f4,
0086                 .shift = 16,
0087                 .mask = 0xff,
0088                 .def = 0x50,
0089             },
0090         },
0091     }, {
0092         .id = 0x05,
0093         .name = "display0c",
0094         .swgroup = TEGRA_SWGROUP_DC,
0095         .regs = {
0096             .smmu = {
0097                 .reg = 0x228,
0098                 .bit = 5,
0099             },
0100             .la = {
0101                 .reg = 0x2ec,
0102                 .shift = 0,
0103                 .mask = 0xff,
0104                 .def = 0x50,
0105             },
0106         },
0107     }, {
0108         .id = 0x06,
0109         .name = "display0cb",
0110         .swgroup = TEGRA_SWGROUP_DCB,
0111         .regs = {
0112             .smmu = {
0113                 .reg = 0x228,
0114                 .bit = 6,
0115             },
0116             .la = {
0117                 .reg = 0x2f8,
0118                 .shift = 0,
0119                 .mask = 0xff,
0120                 .def = 0x50,
0121             },
0122         },
0123     }, {
0124         .id = 0x0e,
0125         .name = "afir",
0126         .swgroup = TEGRA_SWGROUP_AFI,
0127         .regs = {
0128             .smmu = {
0129                 .reg = 0x228,
0130                 .bit = 14,
0131             },
0132             .la = {
0133                 .reg = 0x2e0,
0134                 .shift = 0,
0135                 .mask = 0xff,
0136                 .def = 0x13,
0137             },
0138         },
0139     }, {
0140         .id = 0x0f,
0141         .name = "avpcarm7r",
0142         .swgroup = TEGRA_SWGROUP_AVPC,
0143         .regs = {
0144             .smmu = {
0145                 .reg = 0x228,
0146                 .bit = 15,
0147             },
0148             .la = {
0149                 .reg = 0x2e4,
0150                 .shift = 0,
0151                 .mask = 0xff,
0152                 .def = 0x04,
0153             },
0154         },
0155     }, {
0156         .id = 0x10,
0157         .name = "displayhc",
0158         .swgroup = TEGRA_SWGROUP_DC,
0159         .regs = {
0160             .smmu = {
0161                 .reg = 0x228,
0162                 .bit = 16,
0163             },
0164             .la = {
0165                 .reg = 0x2f0,
0166                 .shift = 0,
0167                 .mask = 0xff,
0168                 .def = 0x50,
0169             },
0170         },
0171     }, {
0172         .id = 0x11,
0173         .name = "displayhcb",
0174         .swgroup = TEGRA_SWGROUP_DCB,
0175         .regs = {
0176             .smmu = {
0177                 .reg = 0x228,
0178                 .bit = 17,
0179             },
0180             .la = {
0181                 .reg = 0x2fc,
0182                 .shift = 0,
0183                 .mask = 0xff,
0184                 .def = 0x50,
0185             },
0186         },
0187     }, {
0188         .id = 0x15,
0189         .name = "hdar",
0190         .swgroup = TEGRA_SWGROUP_HDA,
0191         .regs = {
0192             .smmu = {
0193                 .reg = 0x228,
0194                 .bit = 21,
0195             },
0196             .la = {
0197                 .reg = 0x318,
0198                 .shift = 0,
0199                 .mask = 0xff,
0200                 .def = 0x24,
0201             },
0202         },
0203     }, {
0204         .id = 0x16,
0205         .name = "host1xdmar",
0206         .swgroup = TEGRA_SWGROUP_HC,
0207         .regs = {
0208             .smmu = {
0209                 .reg = 0x228,
0210                 .bit = 22,
0211             },
0212             .la = {
0213                 .reg = 0x310,
0214                 .shift = 0,
0215                 .mask = 0xff,
0216                 .def = 0x1e,
0217             },
0218         },
0219     }, {
0220         .id = 0x17,
0221         .name = "host1xr",
0222         .swgroup = TEGRA_SWGROUP_HC,
0223         .regs = {
0224             .smmu = {
0225                 .reg = 0x228,
0226                 .bit = 23,
0227             },
0228             .la = {
0229                 .reg = 0x310,
0230                 .shift = 16,
0231                 .mask = 0xff,
0232                 .def = 0x50,
0233             },
0234         },
0235     }, {
0236         .id = 0x1c,
0237         .name = "msencsrd",
0238         .swgroup = TEGRA_SWGROUP_MSENC,
0239         .regs = {
0240             .smmu = {
0241                 .reg = 0x228,
0242                 .bit = 28,
0243             },
0244             .la = {
0245                 .reg = 0x328,
0246                 .shift = 0,
0247                 .mask = 0xff,
0248                 .def = 0x23,
0249             },
0250         },
0251     }, {
0252         .id = 0x1d,
0253         .name = "ppcsahbdmar",
0254         .swgroup = TEGRA_SWGROUP_PPCS,
0255         .regs = {
0256             .smmu = {
0257                 .reg = 0x228,
0258                 .bit = 29,
0259             },
0260             .la = {
0261                 .reg = 0x344,
0262                 .shift = 0,
0263                 .mask = 0xff,
0264                 .def = 0x49,
0265             },
0266         },
0267     }, {
0268         .id = 0x1e,
0269         .name = "ppcsahbslvr",
0270         .swgroup = TEGRA_SWGROUP_PPCS,
0271         .regs = {
0272             .smmu = {
0273                 .reg = 0x228,
0274                 .bit = 30,
0275             },
0276             .la = {
0277                 .reg = 0x344,
0278                 .shift = 16,
0279                 .mask = 0xff,
0280                 .def = 0x1a,
0281             },
0282         },
0283     }, {
0284         .id = 0x1f,
0285         .name = "satar",
0286         .swgroup = TEGRA_SWGROUP_SATA,
0287         .regs = {
0288             .smmu = {
0289                 .reg = 0x228,
0290                 .bit = 31,
0291             },
0292             .la = {
0293                 .reg = 0x350,
0294                 .shift = 0,
0295                 .mask = 0xff,
0296                 .def = 0x65,
0297             },
0298         },
0299     }, {
0300         .id = 0x22,
0301         .name = "vdebsevr",
0302         .swgroup = TEGRA_SWGROUP_VDE,
0303         .regs = {
0304             .smmu = {
0305                 .reg = 0x22c,
0306                 .bit = 2,
0307             },
0308             .la = {
0309                 .reg = 0x354,
0310                 .shift = 0,
0311                 .mask = 0xff,
0312                 .def = 0x4f,
0313             },
0314         },
0315     }, {
0316         .id = 0x23,
0317         .name = "vdember",
0318         .swgroup = TEGRA_SWGROUP_VDE,
0319         .regs = {
0320             .smmu = {
0321                 .reg = 0x22c,
0322                 .bit = 3,
0323             },
0324             .la = {
0325                 .reg = 0x354,
0326                 .shift = 16,
0327                 .mask = 0xff,
0328                 .def = 0x3d,
0329             },
0330         },
0331     }, {
0332         .id = 0x24,
0333         .name = "vdemcer",
0334         .swgroup = TEGRA_SWGROUP_VDE,
0335         .regs = {
0336             .smmu = {
0337                 .reg = 0x22c,
0338                 .bit = 4,
0339             },
0340             .la = {
0341                 .reg = 0x358,
0342                 .shift = 0,
0343                 .mask = 0xff,
0344                 .def = 0x66,
0345             },
0346         },
0347     }, {
0348         .id = 0x25,
0349         .name = "vdetper",
0350         .swgroup = TEGRA_SWGROUP_VDE,
0351         .regs = {
0352             .smmu = {
0353                 .reg = 0x22c,
0354                 .bit = 5,
0355             },
0356             .la = {
0357                 .reg = 0x358,
0358                 .shift = 16,
0359                 .mask = 0xff,
0360                 .def = 0xa5,
0361             },
0362         },
0363     }, {
0364         .id = 0x26,
0365         .name = "mpcorelpr",
0366         .swgroup = TEGRA_SWGROUP_MPCORELP,
0367         .regs = {
0368             .la = {
0369                 .reg = 0x324,
0370                 .shift = 0,
0371                 .mask = 0xff,
0372                 .def = 0x04,
0373             },
0374         },
0375     }, {
0376         .id = 0x27,
0377         .name = "mpcorer",
0378         .swgroup = TEGRA_SWGROUP_MPCORE,
0379         .regs = {
0380             .la = {
0381                 .reg = 0x320,
0382                 .shift = 0,
0383                 .mask = 0xff,
0384                 .def = 0x04,
0385             },
0386         },
0387     }, {
0388         .id = 0x2b,
0389         .name = "msencswr",
0390         .swgroup = TEGRA_SWGROUP_MSENC,
0391         .regs = {
0392             .smmu = {
0393                 .reg = 0x22c,
0394                 .bit = 11,
0395             },
0396             .la = {
0397                 .reg = 0x328,
0398                 .shift = 16,
0399                 .mask = 0xff,
0400                 .def = 0x80,
0401             },
0402         },
0403     }, {
0404         .id = 0x31,
0405         .name = "afiw",
0406         .swgroup = TEGRA_SWGROUP_AFI,
0407         .regs = {
0408             .smmu = {
0409                 .reg = 0x22c,
0410                 .bit = 17,
0411             },
0412             .la = {
0413                 .reg = 0x2e0,
0414                 .shift = 16,
0415                 .mask = 0xff,
0416                 .def = 0x80,
0417             },
0418         },
0419     }, {
0420         .id = 0x32,
0421         .name = "avpcarm7w",
0422         .swgroup = TEGRA_SWGROUP_AVPC,
0423         .regs = {
0424             .smmu = {
0425                 .reg = 0x22c,
0426                 .bit = 18,
0427             },
0428             .la = {
0429                 .reg = 0x2e4,
0430                 .shift = 16,
0431                 .mask = 0xff,
0432                 .def = 0x80,
0433             },
0434         },
0435     }, {
0436         .id = 0x35,
0437         .name = "hdaw",
0438         .swgroup = TEGRA_SWGROUP_HDA,
0439         .regs = {
0440             .smmu = {
0441                 .reg = 0x22c,
0442                 .bit = 21,
0443             },
0444             .la = {
0445                 .reg = 0x318,
0446                 .shift = 16,
0447                 .mask = 0xff,
0448                 .def = 0x80,
0449             },
0450         },
0451     }, {
0452         .id = 0x36,
0453         .name = "host1xw",
0454         .swgroup = TEGRA_SWGROUP_HC,
0455         .regs = {
0456             .smmu = {
0457                 .reg = 0x22c,
0458                 .bit = 22,
0459             },
0460             .la = {
0461                 .reg = 0x314,
0462                 .shift = 0,
0463                 .mask = 0xff,
0464                 .def = 0x80,
0465             },
0466         },
0467     }, {
0468         .id = 0x38,
0469         .name = "mpcorelpw",
0470         .swgroup = TEGRA_SWGROUP_MPCORELP,
0471         .regs = {
0472             .la = {
0473                 .reg = 0x324,
0474                 .shift = 16,
0475                 .mask = 0xff,
0476                 .def = 0x80,
0477             },
0478         },
0479     }, {
0480         .id = 0x39,
0481         .name = "mpcorew",
0482         .swgroup = TEGRA_SWGROUP_MPCORE,
0483         .regs = {
0484             .la = {
0485                 .reg = 0x320,
0486                 .shift = 16,
0487                 .mask = 0xff,
0488                 .def = 0x80,
0489             },
0490         },
0491     }, {
0492         .id = 0x3b,
0493         .name = "ppcsahbdmaw",
0494         .swgroup = TEGRA_SWGROUP_PPCS,
0495         .regs = {
0496             .smmu = {
0497                 .reg = 0x22c,
0498                 .bit = 27,
0499             },
0500             .la = {
0501                 .reg = 0x348,
0502                 .shift = 0,
0503                 .mask = 0xff,
0504                 .def = 0x80,
0505             },
0506         },
0507     }, {
0508         .id = 0x3c,
0509         .name = "ppcsahbslvw",
0510         .swgroup = TEGRA_SWGROUP_PPCS,
0511         .regs = {
0512             .smmu = {
0513                 .reg = 0x22c,
0514                 .bit = 28,
0515             },
0516             .la = {
0517                 .reg = 0x348,
0518                 .shift = 16,
0519                 .mask = 0xff,
0520                 .def = 0x80,
0521             },
0522         },
0523     }, {
0524         .id = 0x3d,
0525         .name = "sataw",
0526         .swgroup = TEGRA_SWGROUP_SATA,
0527         .regs = {
0528             .smmu = {
0529                 .reg = 0x22c,
0530                 .bit = 29,
0531             },
0532             .la = {
0533                 .reg = 0x350,
0534                 .shift = 16,
0535                 .mask = 0xff,
0536                 .def = 0x65,
0537             },
0538         },
0539     }, {
0540         .id = 0x3e,
0541         .name = "vdebsevw",
0542         .swgroup = TEGRA_SWGROUP_VDE,
0543         .regs = {
0544             .smmu = {
0545                 .reg = 0x22c,
0546                 .bit = 30,
0547             },
0548             .la = {
0549                 .reg = 0x35c,
0550                 .shift = 0,
0551                 .mask = 0xff,
0552                 .def = 0x80,
0553             },
0554         },
0555     }, {
0556         .id = 0x3f,
0557         .name = "vdedbgw",
0558         .swgroup = TEGRA_SWGROUP_VDE,
0559         .regs = {
0560             .smmu = {
0561                 .reg = 0x22c,
0562                 .bit = 31,
0563             },
0564             .la = {
0565                 .reg = 0x35c,
0566                 .shift = 16,
0567                 .mask = 0xff,
0568                 .def = 0x80,
0569             },
0570         },
0571     }, {
0572         .id = 0x40,
0573         .name = "vdembew",
0574         .swgroup = TEGRA_SWGROUP_VDE,
0575         .regs = {
0576             .smmu = {
0577                 .reg = 0x230,
0578                 .bit = 0,
0579             },
0580             .la = {
0581                 .reg = 0x360,
0582                 .shift = 0,
0583                 .mask = 0xff,
0584                 .def = 0x80,
0585             },
0586         },
0587     }, {
0588         .id = 0x41,
0589         .name = "vdetpmw",
0590         .swgroup = TEGRA_SWGROUP_VDE,
0591         .regs = {
0592             .smmu = {
0593                 .reg = 0x230,
0594                 .bit = 1,
0595             },
0596             .la = {
0597                 .reg = 0x360,
0598                 .shift = 16,
0599                 .mask = 0xff,
0600                 .def = 0x80,
0601             },
0602         },
0603     }, {
0604         .id = 0x44,
0605         .name = "ispra",
0606         .swgroup = TEGRA_SWGROUP_ISP2,
0607         .regs = {
0608             .smmu = {
0609                 .reg = 0x230,
0610                 .bit = 4,
0611             },
0612             .la = {
0613                 .reg = 0x370,
0614                 .shift = 0,
0615                 .mask = 0xff,
0616                 .def = 0x18,
0617             },
0618         },
0619     }, {
0620         .id = 0x46,
0621         .name = "ispwa",
0622         .swgroup = TEGRA_SWGROUP_ISP2,
0623         .regs = {
0624             .smmu = {
0625                 .reg = 0x230,
0626                 .bit = 6,
0627             },
0628             .la = {
0629                 .reg = 0x374,
0630                 .shift = 0,
0631                 .mask = 0xff,
0632                 .def = 0x80,
0633             },
0634         },
0635     }, {
0636         .id = 0x47,
0637         .name = "ispwb",
0638         .swgroup = TEGRA_SWGROUP_ISP2,
0639         .regs = {
0640             .smmu = {
0641                 .reg = 0x230,
0642                 .bit = 7,
0643             },
0644             .la = {
0645                 .reg = 0x374,
0646                 .shift = 16,
0647                 .mask = 0xff,
0648                 .def = 0x80,
0649             },
0650         },
0651     }, {
0652         .id = 0x4a,
0653         .name = "xusb_hostr",
0654         .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0655         .regs = {
0656             .smmu = {
0657                 .reg = 0x230,
0658                 .bit = 10,
0659             },
0660             .la = {
0661                 .reg = 0x37c,
0662                 .shift = 0,
0663                 .mask = 0xff,
0664                 .def = 0x39,
0665             },
0666         },
0667     }, {
0668         .id = 0x4b,
0669         .name = "xusb_hostw",
0670         .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0671         .regs = {
0672             .smmu = {
0673                 .reg = 0x230,
0674                 .bit = 11,
0675             },
0676             .la = {
0677                 .reg = 0x37c,
0678                 .shift = 16,
0679                 .mask = 0xff,
0680                 .def = 0x80,
0681             },
0682         },
0683     }, {
0684         .id = 0x4c,
0685         .name = "xusb_devr",
0686         .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0687         .regs = {
0688             .smmu = {
0689                 .reg = 0x230,
0690                 .bit = 12,
0691             },
0692             .la = {
0693                 .reg = 0x380,
0694                 .shift = 0,
0695                 .mask = 0xff,
0696                 .def = 0x39,
0697             },
0698         },
0699     }, {
0700         .id = 0x4d,
0701         .name = "xusb_devw",
0702         .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0703         .regs = {
0704             .smmu = {
0705                 .reg = 0x230,
0706                 .bit = 13,
0707             },
0708             .la = {
0709                 .reg = 0x380,
0710                 .shift = 16,
0711                 .mask = 0xff,
0712                 .def = 0x80,
0713             },
0714         },
0715     }, {
0716         .id = 0x4e,
0717         .name = "isprab",
0718         .swgroup = TEGRA_SWGROUP_ISP2B,
0719         .regs = {
0720             .smmu = {
0721                 .reg = 0x230,
0722                 .bit = 14,
0723             },
0724             .la = {
0725                 .reg = 0x384,
0726                 .shift = 0,
0727                 .mask = 0xff,
0728                 .def = 0x18,
0729             },
0730         },
0731     }, {
0732         .id = 0x50,
0733         .name = "ispwab",
0734         .swgroup = TEGRA_SWGROUP_ISP2B,
0735         .regs = {
0736             .smmu = {
0737                 .reg = 0x230,
0738                 .bit = 16,
0739             },
0740             .la = {
0741                 .reg = 0x388,
0742                 .shift = 0,
0743                 .mask = 0xff,
0744                 .def = 0x80,
0745             },
0746         },
0747     }, {
0748         .id = 0x51,
0749         .name = "ispwbb",
0750         .swgroup = TEGRA_SWGROUP_ISP2B,
0751         .regs = {
0752             .smmu = {
0753                 .reg = 0x230,
0754                 .bit = 17,
0755             },
0756             .la = {
0757                 .reg = 0x388,
0758                 .shift = 16,
0759                 .mask = 0xff,
0760                 .def = 0x80,
0761             },
0762         },
0763     }, {
0764         .id = 0x54,
0765         .name = "tsecsrd",
0766         .swgroup = TEGRA_SWGROUP_TSEC,
0767         .regs = {
0768             .smmu = {
0769                 .reg = 0x230,
0770                 .bit = 20,
0771             },
0772             .la = {
0773                 .reg = 0x390,
0774                 .shift = 0,
0775                 .mask = 0xff,
0776                 .def = 0x9b,
0777             },
0778         },
0779     }, {
0780         .id = 0x55,
0781         .name = "tsecswr",
0782         .swgroup = TEGRA_SWGROUP_TSEC,
0783         .regs = {
0784             .smmu = {
0785                 .reg = 0x230,
0786                 .bit = 21,
0787             },
0788             .la = {
0789                 .reg = 0x390,
0790                 .shift = 16,
0791                 .mask = 0xff,
0792                 .def = 0x80,
0793             },
0794         },
0795     }, {
0796         .id = 0x56,
0797         .name = "a9avpscr",
0798         .swgroup = TEGRA_SWGROUP_A9AVP,
0799         .regs = {
0800             .smmu = {
0801                 .reg = 0x230,
0802                 .bit = 22,
0803             },
0804             .la = {
0805                 .reg = 0x3a4,
0806                 .shift = 0,
0807                 .mask = 0xff,
0808                 .def = 0x04,
0809             },
0810         },
0811     }, {
0812         .id = 0x57,
0813         .name = "a9avpscw",
0814         .swgroup = TEGRA_SWGROUP_A9AVP,
0815         .regs = {
0816             .smmu = {
0817                 .reg = 0x230,
0818                 .bit = 23,
0819             },
0820             .la = {
0821                 .reg = 0x3a4,
0822                 .shift = 16,
0823                 .mask = 0xff,
0824                 .def = 0x80,
0825             },
0826         },
0827     }, {
0828         .id = 0x58,
0829         .name = "gpusrd",
0830         .swgroup = TEGRA_SWGROUP_GPU,
0831         .regs = {
0832             .smmu = {
0833                 /* read-only */
0834                 .reg = 0x230,
0835                 .bit = 24,
0836             },
0837             .la = {
0838                 .reg = 0x3c8,
0839                 .shift = 0,
0840                 .mask = 0xff,
0841                 .def = 0x1a,
0842             },
0843         },
0844     }, {
0845         .id = 0x59,
0846         .name = "gpuswr",
0847         .swgroup = TEGRA_SWGROUP_GPU,
0848         .regs = {
0849             .smmu = {
0850                 /* read-only */
0851                 .reg = 0x230,
0852                 .bit = 25,
0853             },
0854             .la = {
0855                 .reg = 0x3c8,
0856                 .shift = 16,
0857                 .mask = 0xff,
0858                 .def = 0x80,
0859             },
0860         },
0861     }, {
0862         .id = 0x5a,
0863         .name = "displayt",
0864         .swgroup = TEGRA_SWGROUP_DC,
0865         .regs = {
0866             .smmu = {
0867                 .reg = 0x230,
0868                 .bit = 26,
0869             },
0870             .la = {
0871                 .reg = 0x2f0,
0872                 .shift = 16,
0873                 .mask = 0xff,
0874                 .def = 0x50,
0875             },
0876         },
0877     }, {
0878         .id = 0x60,
0879         .name = "sdmmcra",
0880         .swgroup = TEGRA_SWGROUP_SDMMC1A,
0881         .regs = {
0882             .smmu = {
0883                 .reg = 0x234,
0884                 .bit = 0,
0885             },
0886             .la = {
0887                 .reg = 0x3b8,
0888                 .shift = 0,
0889                 .mask = 0xff,
0890                 .def = 0x49,
0891             },
0892         },
0893     }, {
0894         .id = 0x61,
0895         .name = "sdmmcraa",
0896         .swgroup = TEGRA_SWGROUP_SDMMC2A,
0897         .regs = {
0898             .smmu = {
0899                 .reg = 0x234,
0900                 .bit = 1,
0901             },
0902             .la = {
0903                 .reg = 0x3bc,
0904                 .shift = 0,
0905                 .mask = 0xff,
0906                 .def = 0x49,
0907             },
0908         },
0909     }, {
0910         .id = 0x62,
0911         .name = "sdmmcr",
0912         .swgroup = TEGRA_SWGROUP_SDMMC3A,
0913         .regs = {
0914             .smmu = {
0915                 .reg = 0x234,
0916                 .bit = 2,
0917             },
0918             .la = {
0919                 .reg = 0x3c0,
0920                 .shift = 0,
0921                 .mask = 0xff,
0922                 .def = 0x49,
0923             },
0924         },
0925     }, {
0926         .id = 0x63,
0927         .swgroup = TEGRA_SWGROUP_SDMMC4A,
0928         .name = "sdmmcrab",
0929         .regs = {
0930             .smmu = {
0931                 .reg = 0x234,
0932                 .bit = 3,
0933             },
0934             .la = {
0935                 .reg = 0x3c4,
0936                 .shift = 0,
0937                 .mask = 0xff,
0938                 .def = 0x49,
0939             },
0940         },
0941     }, {
0942         .id = 0x64,
0943         .name = "sdmmcwa",
0944         .swgroup = TEGRA_SWGROUP_SDMMC1A,
0945         .regs = {
0946             .smmu = {
0947                 .reg = 0x234,
0948                 .bit = 4,
0949             },
0950             .la = {
0951                 .reg = 0x3b8,
0952                 .shift = 16,
0953                 .mask = 0xff,
0954                 .def = 0x80,
0955             },
0956         },
0957     }, {
0958         .id = 0x65,
0959         .name = "sdmmcwaa",
0960         .swgroup = TEGRA_SWGROUP_SDMMC2A,
0961         .regs = {
0962             .smmu = {
0963                 .reg = 0x234,
0964                 .bit = 5,
0965             },
0966             .la = {
0967                 .reg = 0x3bc,
0968                 .shift = 16,
0969                 .mask = 0xff,
0970                 .def = 0x80,
0971             },
0972         },
0973     }, {
0974         .id = 0x66,
0975         .name = "sdmmcw",
0976         .swgroup = TEGRA_SWGROUP_SDMMC3A,
0977         .regs = {
0978             .smmu = {
0979                 .reg = 0x234,
0980                 .bit = 6,
0981             },
0982             .la = {
0983                 .reg = 0x3c0,
0984                 .shift = 16,
0985                 .mask = 0xff,
0986                 .def = 0x80,
0987             },
0988         },
0989     }, {
0990         .id = 0x67,
0991         .name = "sdmmcwab",
0992         .swgroup = TEGRA_SWGROUP_SDMMC4A,
0993         .regs = {
0994             .smmu = {
0995                 .reg = 0x234,
0996                 .bit = 7,
0997             },
0998             .la = {
0999                 .reg = 0x3c4,
1000                 .shift = 16,
1001                 .mask = 0xff,
1002                 .def = 0x80,
1003             },
1004         },
1005     }, {
1006         .id = 0x6c,
1007         .name = "vicsrd",
1008         .swgroup = TEGRA_SWGROUP_VIC,
1009         .regs = {
1010             .smmu = {
1011                 .reg = 0x234,
1012                 .bit = 12,
1013             },
1014             .la = {
1015                 .reg = 0x394,
1016                 .shift = 0,
1017                 .mask = 0xff,
1018                 .def = 0x1a,
1019             },
1020         },
1021     }, {
1022         .id = 0x6d,
1023         .name = "vicswr",
1024         .swgroup = TEGRA_SWGROUP_VIC,
1025         .regs = {
1026             .smmu = {
1027                 .reg = 0x234,
1028                 .bit = 13,
1029             },
1030             .la = {
1031                 .reg = 0x394,
1032                 .shift = 16,
1033                 .mask = 0xff,
1034                 .def = 0x80,
1035             },
1036         },
1037     }, {
1038         .id = 0x72,
1039         .name = "viw",
1040         .swgroup = TEGRA_SWGROUP_VI,
1041         .regs = {
1042             .smmu = {
1043                 .reg = 0x234,
1044                 .bit = 18,
1045             },
1046             .la = {
1047                 .reg = 0x398,
1048                 .shift = 0,
1049                 .mask = 0xff,
1050                 .def = 0x80,
1051             },
1052         },
1053     }, {
1054         .id = 0x73,
1055         .name = "displayd",
1056         .swgroup = TEGRA_SWGROUP_DC,
1057         .regs = {
1058             .smmu = {
1059                 .reg = 0x234,
1060                 .bit = 19,
1061             },
1062             .la = {
1063                 .reg = 0x3c8,
1064                 .shift = 0,
1065                 .mask = 0xff,
1066                 .def = 0x50,
1067             },
1068         },
1069     },
1070 };
1071 
1072 static const struct tegra_smmu_swgroup tegra124_swgroups[] = {
1073     { .name = "dc",        .swgroup = TEGRA_SWGROUP_DC,        .reg = 0x240 },
1074     { .name = "dcb",       .swgroup = TEGRA_SWGROUP_DCB,       .reg = 0x244 },
1075     { .name = "afi",       .swgroup = TEGRA_SWGROUP_AFI,       .reg = 0x238 },
1076     { .name = "avpc",      .swgroup = TEGRA_SWGROUP_AVPC,      .reg = 0x23c },
1077     { .name = "hda",       .swgroup = TEGRA_SWGROUP_HDA,       .reg = 0x254 },
1078     { .name = "hc",        .swgroup = TEGRA_SWGROUP_HC,        .reg = 0x250 },
1079     { .name = "msenc",     .swgroup = TEGRA_SWGROUP_MSENC,     .reg = 0x264 },
1080     { .name = "ppcs",      .swgroup = TEGRA_SWGROUP_PPCS,      .reg = 0x270 },
1081     { .name = "sata",      .swgroup = TEGRA_SWGROUP_SATA,      .reg = 0x274 },
1082     { .name = "vde",       .swgroup = TEGRA_SWGROUP_VDE,       .reg = 0x27c },
1083     { .name = "isp2",      .swgroup = TEGRA_SWGROUP_ISP2,      .reg = 0x258 },
1084     { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1085     { .name = "xusb_dev",  .swgroup = TEGRA_SWGROUP_XUSB_DEV,  .reg = 0x28c },
1086     { .name = "isp2b",     .swgroup = TEGRA_SWGROUP_ISP2B,     .reg = 0xaa4 },
1087     { .name = "tsec",      .swgroup = TEGRA_SWGROUP_TSEC,      .reg = 0x294 },
1088     { .name = "a9avp",     .swgroup = TEGRA_SWGROUP_A9AVP,     .reg = 0x290 },
1089     { .name = "gpu",       .swgroup = TEGRA_SWGROUP_GPU,       .reg = 0xaac },
1090     { .name = "sdmmc1a",   .swgroup = TEGRA_SWGROUP_SDMMC1A,   .reg = 0xa94 },
1091     { .name = "sdmmc2a",   .swgroup = TEGRA_SWGROUP_SDMMC2A,   .reg = 0xa98 },
1092     { .name = "sdmmc3a",   .swgroup = TEGRA_SWGROUP_SDMMC3A,   .reg = 0xa9c },
1093     { .name = "sdmmc4a",   .swgroup = TEGRA_SWGROUP_SDMMC4A,   .reg = 0xaa0 },
1094     { .name = "vic",       .swgroup = TEGRA_SWGROUP_VIC,       .reg = 0x284 },
1095     { .name = "vi",        .swgroup = TEGRA_SWGROUP_VI,        .reg = 0x280 },
1096 };
1097 
1098 static const unsigned int tegra124_group_drm[] = {
1099     TEGRA_SWGROUP_DC,
1100     TEGRA_SWGROUP_DCB,
1101     TEGRA_SWGROUP_VIC,
1102 };
1103 
1104 static const struct tegra_smmu_group_soc tegra124_groups[] = {
1105     {
1106         .name = "drm",
1107         .swgroups = tegra124_group_drm,
1108         .num_swgroups = ARRAY_SIZE(tegra124_group_drm),
1109     },
1110 };
1111 
1112 #define TEGRA124_MC_RESET(_name, _control, _status, _bit)   \
1113     {                           \
1114         .name = #_name,                 \
1115         .id = TEGRA124_MC_RESET_##_name,        \
1116         .control = _control,                \
1117         .status = _status,              \
1118         .bit = _bit,                    \
1119     }
1120 
1121 static const struct tegra_mc_reset tegra124_mc_resets[] = {
1122     TEGRA124_MC_RESET(AFI,       0x200, 0x204,  0),
1123     TEGRA124_MC_RESET(AVPC,      0x200, 0x204,  1),
1124     TEGRA124_MC_RESET(DC,        0x200, 0x204,  2),
1125     TEGRA124_MC_RESET(DCB,       0x200, 0x204,  3),
1126     TEGRA124_MC_RESET(HC,        0x200, 0x204,  6),
1127     TEGRA124_MC_RESET(HDA,       0x200, 0x204,  7),
1128     TEGRA124_MC_RESET(ISP2,      0x200, 0x204,  8),
1129     TEGRA124_MC_RESET(MPCORE,    0x200, 0x204,  9),
1130     TEGRA124_MC_RESET(MPCORELP,  0x200, 0x204, 10),
1131     TEGRA124_MC_RESET(MSENC,     0x200, 0x204, 11),
1132     TEGRA124_MC_RESET(PPCS,      0x200, 0x204, 14),
1133     TEGRA124_MC_RESET(SATA,      0x200, 0x204, 15),
1134     TEGRA124_MC_RESET(VDE,       0x200, 0x204, 16),
1135     TEGRA124_MC_RESET(VI,        0x200, 0x204, 17),
1136     TEGRA124_MC_RESET(VIC,       0x200, 0x204, 18),
1137     TEGRA124_MC_RESET(XUSB_HOST, 0x200, 0x204, 19),
1138     TEGRA124_MC_RESET(XUSB_DEV,  0x200, 0x204, 20),
1139     TEGRA124_MC_RESET(TSEC,      0x200, 0x204, 21),
1140     TEGRA124_MC_RESET(SDMMC1,    0x200, 0x204, 22),
1141     TEGRA124_MC_RESET(SDMMC2,    0x200, 0x204, 23),
1142     TEGRA124_MC_RESET(SDMMC3,    0x200, 0x204, 25),
1143     TEGRA124_MC_RESET(SDMMC4,    0x970, 0x974,  0),
1144     TEGRA124_MC_RESET(ISP2B,     0x970, 0x974,  1),
1145     TEGRA124_MC_RESET(GPU,       0x970, 0x974,  2),
1146 };
1147 
1148 static int tegra124_mc_icc_set(struct icc_node *src, struct icc_node *dst)
1149 {
1150     /* TODO: program PTSA */
1151     return 0;
1152 }
1153 
1154 static int tegra124_mc_icc_aggreate(struct icc_node *node, u32 tag, u32 avg_bw,
1155                     u32 peak_bw, u32 *agg_avg, u32 *agg_peak)
1156 {
1157     /*
1158      * ISO clients need to reserve extra bandwidth up-front because
1159      * there could be high bandwidth pressure during initial filling
1160      * of the client's FIFO buffers.  Secondly, we need to take into
1161      * account impurities of the memory subsystem.
1162      */
1163     if (tag & TEGRA_MC_ICC_TAG_ISO)
1164         peak_bw = tegra_mc_scale_percents(peak_bw, 400);
1165 
1166     *agg_avg += avg_bw;
1167     *agg_peak = max(*agg_peak, peak_bw);
1168 
1169     return 0;
1170 }
1171 
1172 static struct icc_node_data *
1173 tegra124_mc_of_icc_xlate_extended(struct of_phandle_args *spec, void *data)
1174 {
1175     struct tegra_mc *mc = icc_provider_to_tegra_mc(data);
1176     const struct tegra_mc_client *client;
1177     unsigned int i, idx = spec->args[0];
1178     struct icc_node_data *ndata;
1179     struct icc_node *node;
1180 
1181     list_for_each_entry(node, &mc->provider.nodes, node_list) {
1182         if (node->id != idx)
1183             continue;
1184 
1185         ndata = kzalloc(sizeof(*ndata), GFP_KERNEL);
1186         if (!ndata)
1187             return ERR_PTR(-ENOMEM);
1188 
1189         client = &mc->soc->clients[idx];
1190         ndata->node = node;
1191 
1192         switch (client->swgroup) {
1193         case TEGRA_SWGROUP_DC:
1194         case TEGRA_SWGROUP_DCB:
1195         case TEGRA_SWGROUP_PTC:
1196         case TEGRA_SWGROUP_VI:
1197             /* these clients are isochronous by default */
1198             ndata->tag = TEGRA_MC_ICC_TAG_ISO;
1199             break;
1200 
1201         default:
1202             ndata->tag = TEGRA_MC_ICC_TAG_DEFAULT;
1203             break;
1204         }
1205 
1206         return ndata;
1207     }
1208 
1209     for (i = 0; i < mc->soc->num_clients; i++) {
1210         if (mc->soc->clients[i].id == idx)
1211             return ERR_PTR(-EPROBE_DEFER);
1212     }
1213 
1214     dev_err(mc->dev, "invalid ICC client ID %u\n", idx);
1215 
1216     return ERR_PTR(-EINVAL);
1217 }
1218 
1219 static const struct tegra_mc_icc_ops tegra124_mc_icc_ops = {
1220     .xlate_extended = tegra124_mc_of_icc_xlate_extended,
1221     .aggregate = tegra124_mc_icc_aggreate,
1222     .set = tegra124_mc_icc_set,
1223 };
1224 
1225 #ifdef CONFIG_ARCH_TEGRA_124_SOC
1226 static const unsigned long tegra124_mc_emem_regs[] = {
1227     MC_EMEM_ARB_CFG,
1228     MC_EMEM_ARB_OUTSTANDING_REQ,
1229     MC_EMEM_ARB_TIMING_RCD,
1230     MC_EMEM_ARB_TIMING_RP,
1231     MC_EMEM_ARB_TIMING_RC,
1232     MC_EMEM_ARB_TIMING_RAS,
1233     MC_EMEM_ARB_TIMING_FAW,
1234     MC_EMEM_ARB_TIMING_RRD,
1235     MC_EMEM_ARB_TIMING_RAP2PRE,
1236     MC_EMEM_ARB_TIMING_WAP2PRE,
1237     MC_EMEM_ARB_TIMING_R2R,
1238     MC_EMEM_ARB_TIMING_W2W,
1239     MC_EMEM_ARB_TIMING_R2W,
1240     MC_EMEM_ARB_TIMING_W2R,
1241     MC_EMEM_ARB_DA_TURNS,
1242     MC_EMEM_ARB_DA_COVERS,
1243     MC_EMEM_ARB_MISC0,
1244     MC_EMEM_ARB_MISC1,
1245     MC_EMEM_ARB_RING1_THROTTLE
1246 };
1247 
1248 static const struct tegra_smmu_soc tegra124_smmu_soc = {
1249     .clients = tegra124_mc_clients,
1250     .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1251     .swgroups = tegra124_swgroups,
1252     .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1253     .groups = tegra124_groups,
1254     .num_groups = ARRAY_SIZE(tegra124_groups),
1255     .supports_round_robin_arbitration = true,
1256     .supports_request_limit = true,
1257     .num_tlb_lines = 32,
1258     .num_asids = 128,
1259 };
1260 
1261 const struct tegra_mc_soc tegra124_mc_soc = {
1262     .clients = tegra124_mc_clients,
1263     .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1264     .num_address_bits = 34,
1265     .atom_size = 32,
1266     .client_id_mask = 0x7f,
1267     .smmu = &tegra124_smmu_soc,
1268     .emem_regs = tegra124_mc_emem_regs,
1269     .num_emem_regs = ARRAY_SIZE(tegra124_mc_emem_regs),
1270     .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1271            MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1272            MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1273     .reset_ops = &tegra_mc_reset_ops_common,
1274     .resets = tegra124_mc_resets,
1275     .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1276     .icc_ops = &tegra124_mc_icc_ops,
1277     .ops = &tegra30_mc_ops,
1278 };
1279 #endif /* CONFIG_ARCH_TEGRA_124_SOC */
1280 
1281 #ifdef CONFIG_ARCH_TEGRA_132_SOC
1282 static const struct tegra_smmu_soc tegra132_smmu_soc = {
1283     .clients = tegra124_mc_clients,
1284     .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1285     .swgroups = tegra124_swgroups,
1286     .num_swgroups = ARRAY_SIZE(tegra124_swgroups),
1287     .groups = tegra124_groups,
1288     .num_groups = ARRAY_SIZE(tegra124_groups),
1289     .supports_round_robin_arbitration = true,
1290     .supports_request_limit = true,
1291     .num_tlb_lines = 32,
1292     .num_asids = 128,
1293 };
1294 
1295 const struct tegra_mc_soc tegra132_mc_soc = {
1296     .clients = tegra124_mc_clients,
1297     .num_clients = ARRAY_SIZE(tegra124_mc_clients),
1298     .num_address_bits = 34,
1299     .atom_size = 32,
1300     .client_id_mask = 0x7f,
1301     .smmu = &tegra132_smmu_soc,
1302     .intmask = MC_INT_DECERR_MTS | MC_INT_SECERR_SEC | MC_INT_DECERR_VPR |
1303            MC_INT_INVALID_APB_ASID_UPDATE | MC_INT_INVALID_SMMU_PAGE |
1304            MC_INT_SECURITY_VIOLATION | MC_INT_DECERR_EMEM,
1305     .reset_ops = &tegra_mc_reset_ops_common,
1306     .resets = tegra124_mc_resets,
1307     .num_resets = ARRAY_SIZE(tegra124_mc_resets),
1308     .icc_ops = &tegra124_mc_icc_ops,
1309     .ops = &tegra30_mc_ops,
1310 };
1311 #endif /* CONFIG_ARCH_TEGRA_132_SOC */
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