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0006 #include <linux/of.h>
0007 #include <linux/mm.h>
0008
0009 #include <dt-bindings/memory/tegra114-mc.h>
0010
0011 #include "mc.h"
0012
0013 static const struct tegra_mc_client tegra114_mc_clients[] = {
0014 {
0015 .id = 0x00,
0016 .name = "ptcr",
0017 .swgroup = TEGRA_SWGROUP_PTC,
0018 .regs = {
0019 .la = {
0020 .reg = 0x34c,
0021 .shift = 0,
0022 .mask = 0xff,
0023 .def = 0x0,
0024 },
0025 },
0026 }, {
0027 .id = 0x01,
0028 .name = "display0a",
0029 .swgroup = TEGRA_SWGROUP_DC,
0030 .regs = {
0031 .smmu = {
0032 .reg = 0x228,
0033 .bit = 1,
0034 },
0035 .la = {
0036 .reg = 0x2e8,
0037 .shift = 0,
0038 .mask = 0xff,
0039 .def = 0x4e,
0040 },
0041 },
0042 }, {
0043 .id = 0x02,
0044 .name = "display0ab",
0045 .swgroup = TEGRA_SWGROUP_DCB,
0046 .regs = {
0047 .smmu = {
0048 .reg = 0x228,
0049 .bit = 2,
0050 },
0051 .la = {
0052 .reg = 0x2f4,
0053 .shift = 0,
0054 .mask = 0xff,
0055 .def = 0x4e,
0056 },
0057 },
0058 }, {
0059 .id = 0x03,
0060 .name = "display0b",
0061 .swgroup = TEGRA_SWGROUP_DC,
0062 .regs = {
0063 .smmu = {
0064 .reg = 0x228,
0065 .bit = 3,
0066 },
0067 .la = {
0068 .reg = 0x2e8,
0069 .shift = 16,
0070 .mask = 0xff,
0071 .def = 0x4e,
0072 },
0073 },
0074 }, {
0075 .id = 0x04,
0076 .name = "display0bb",
0077 .swgroup = TEGRA_SWGROUP_DCB,
0078 .regs = {
0079 .smmu = {
0080 .reg = 0x228,
0081 .bit = 4,
0082 },
0083 .la = {
0084 .reg = 0x2f4,
0085 .shift = 16,
0086 .mask = 0xff,
0087 .def = 0x4e,
0088 },
0089 },
0090 }, {
0091 .id = 0x05,
0092 .name = "display0c",
0093 .swgroup = TEGRA_SWGROUP_DC,
0094 .regs = {
0095 .smmu = {
0096 .reg = 0x228,
0097 .bit = 5,
0098 },
0099 .la = {
0100 .reg = 0x2ec,
0101 .shift = 0,
0102 .mask = 0xff,
0103 .def = 0x4e,
0104 },
0105 },
0106 }, {
0107 .id = 0x06,
0108 .name = "display0cb",
0109 .swgroup = TEGRA_SWGROUP_DCB,
0110 .regs = {
0111 .smmu = {
0112 .reg = 0x228,
0113 .bit = 6,
0114 },
0115 .la = {
0116 .reg = 0x2f8,
0117 .shift = 0,
0118 .mask = 0xff,
0119 .def = 0x4e,
0120 },
0121 },
0122 }, {
0123 .id = 0x09,
0124 .name = "eppup",
0125 .swgroup = TEGRA_SWGROUP_EPP,
0126 .regs = {
0127 .smmu = {
0128 .reg = 0x228,
0129 .bit = 9,
0130 },
0131 .la = {
0132 .reg = 0x300,
0133 .shift = 0,
0134 .mask = 0xff,
0135 .def = 0x33,
0136 },
0137 },
0138 }, {
0139 .id = 0x0a,
0140 .name = "g2pr",
0141 .swgroup = TEGRA_SWGROUP_G2,
0142 .regs = {
0143 .smmu = {
0144 .reg = 0x228,
0145 .bit = 10,
0146 },
0147 .la = {
0148 .reg = 0x308,
0149 .shift = 0,
0150 .mask = 0xff,
0151 .def = 0x09,
0152 },
0153 },
0154 }, {
0155 .id = 0x0b,
0156 .name = "g2sr",
0157 .swgroup = TEGRA_SWGROUP_G2,
0158 .regs = {
0159 .smmu = {
0160 .reg = 0x228,
0161 .bit = 11,
0162 },
0163 .la = {
0164 .reg = 0x308,
0165 .shift = 16,
0166 .mask = 0xff,
0167 .def = 0x09,
0168 },
0169 },
0170 }, {
0171 .id = 0x0f,
0172 .name = "avpcarm7r",
0173 .swgroup = TEGRA_SWGROUP_AVPC,
0174 .regs = {
0175 .smmu = {
0176 .reg = 0x228,
0177 .bit = 15,
0178 },
0179 .la = {
0180 .reg = 0x2e4,
0181 .shift = 0,
0182 .mask = 0xff,
0183 .def = 0x04,
0184 },
0185 },
0186 }, {
0187 .id = 0x10,
0188 .name = "displayhc",
0189 .swgroup = TEGRA_SWGROUP_DC,
0190 .regs = {
0191 .smmu = {
0192 .reg = 0x228,
0193 .bit = 16,
0194 },
0195 .la = {
0196 .reg = 0x2f0,
0197 .shift = 0,
0198 .mask = 0xff,
0199 .def = 0x68,
0200 },
0201 },
0202 }, {
0203 .id = 0x11,
0204 .name = "displayhcb",
0205 .swgroup = TEGRA_SWGROUP_DCB,
0206 .regs = {
0207 .smmu = {
0208 .reg = 0x228,
0209 .bit = 17,
0210 },
0211 .la = {
0212 .reg = 0x2fc,
0213 .shift = 0,
0214 .mask = 0xff,
0215 .def = 0x68,
0216 },
0217 },
0218 }, {
0219 .id = 0x12,
0220 .name = "fdcdrd",
0221 .swgroup = TEGRA_SWGROUP_NV,
0222 .regs = {
0223 .smmu = {
0224 .reg = 0x228,
0225 .bit = 18,
0226 },
0227 .la = {
0228 .reg = 0x334,
0229 .shift = 0,
0230 .mask = 0xff,
0231 .def = 0x0c,
0232 },
0233 },
0234 }, {
0235 .id = 0x13,
0236 .name = "fdcdrd2",
0237 .swgroup = TEGRA_SWGROUP_NV,
0238 .regs = {
0239 .smmu = {
0240 .reg = 0x228,
0241 .bit = 19,
0242 },
0243 .la = {
0244 .reg = 0x33c,
0245 .shift = 0,
0246 .mask = 0xff,
0247 .def = 0x0c,
0248 },
0249 },
0250 }, {
0251 .id = 0x14,
0252 .name = "g2dr",
0253 .swgroup = TEGRA_SWGROUP_G2,
0254 .regs = {
0255 .smmu = {
0256 .reg = 0x228,
0257 .bit = 20,
0258 },
0259 .la = {
0260 .reg = 0x30c,
0261 .shift = 0,
0262 .mask = 0xff,
0263 .def = 0x0a,
0264 },
0265 },
0266 }, {
0267 .id = 0x15,
0268 .name = "hdar",
0269 .swgroup = TEGRA_SWGROUP_HDA,
0270 .regs = {
0271 .smmu = {
0272 .reg = 0x228,
0273 .bit = 21,
0274 },
0275 .la = {
0276 .reg = 0x318,
0277 .shift = 0,
0278 .mask = 0xff,
0279 .def = 0xff,
0280 },
0281 },
0282 }, {
0283 .id = 0x16,
0284 .name = "host1xdmar",
0285 .swgroup = TEGRA_SWGROUP_HC,
0286 .regs = {
0287 .smmu = {
0288 .reg = 0x228,
0289 .bit = 22,
0290 },
0291 .la = {
0292 .reg = 0x310,
0293 .shift = 0,
0294 .mask = 0xff,
0295 .def = 0x10,
0296 },
0297 },
0298 }, {
0299 .id = 0x17,
0300 .name = "host1xr",
0301 .swgroup = TEGRA_SWGROUP_HC,
0302 .regs = {
0303 .smmu = {
0304 .reg = 0x228,
0305 .bit = 23,
0306 },
0307 .la = {
0308 .reg = 0x310,
0309 .shift = 16,
0310 .mask = 0xff,
0311 .def = 0xa5,
0312 },
0313 },
0314 }, {
0315 .id = 0x18,
0316 .name = "idxsrd",
0317 .swgroup = TEGRA_SWGROUP_NV,
0318 .regs = {
0319 .smmu = {
0320 .reg = 0x228,
0321 .bit = 24,
0322 },
0323 .la = {
0324 .reg = 0x334,
0325 .shift = 16,
0326 .mask = 0xff,
0327 .def = 0x0b,
0328 },
0329 },
0330 }, {
0331 .id = 0x1c,
0332 .name = "msencsrd",
0333 .swgroup = TEGRA_SWGROUP_MSENC,
0334 .regs = {
0335 .smmu = {
0336 .reg = 0x228,
0337 .bit = 28,
0338 },
0339 .la = {
0340 .reg = 0x328,
0341 .shift = 0,
0342 .mask = 0xff,
0343 .def = 0x80,
0344 },
0345 },
0346 }, {
0347 .id = 0x1d,
0348 .name = "ppcsahbdmar",
0349 .swgroup = TEGRA_SWGROUP_PPCS,
0350 .regs = {
0351 .smmu = {
0352 .reg = 0x228,
0353 .bit = 29,
0354 },
0355 .la = {
0356 .reg = 0x344,
0357 .shift = 0,
0358 .mask = 0xff,
0359 .def = 0x50,
0360 },
0361 },
0362 }, {
0363 .id = 0x1e,
0364 .name = "ppcsahbslvr",
0365 .swgroup = TEGRA_SWGROUP_PPCS,
0366 .regs = {
0367 .smmu = {
0368 .reg = 0x228,
0369 .bit = 30,
0370 },
0371 .la = {
0372 .reg = 0x344,
0373 .shift = 16,
0374 .mask = 0xff,
0375 .def = 0xe8,
0376 },
0377 },
0378 }, {
0379 .id = 0x20,
0380 .name = "texl2srd",
0381 .swgroup = TEGRA_SWGROUP_NV,
0382 .regs = {
0383 .smmu = {
0384 .reg = 0x22c,
0385 .bit = 0,
0386 },
0387 .la = {
0388 .reg = 0x338,
0389 .shift = 0,
0390 .mask = 0xff,
0391 .def = 0x0c,
0392 },
0393 },
0394 }, {
0395 .id = 0x22,
0396 .name = "vdebsevr",
0397 .swgroup = TEGRA_SWGROUP_VDE,
0398 .regs = {
0399 .smmu = {
0400 .reg = 0x22c,
0401 .bit = 2,
0402 },
0403 .la = {
0404 .reg = 0x354,
0405 .shift = 0,
0406 .mask = 0xff,
0407 .def = 0xff,
0408 },
0409 },
0410 }, {
0411 .id = 0x23,
0412 .name = "vdember",
0413 .swgroup = TEGRA_SWGROUP_VDE,
0414 .regs = {
0415 .smmu = {
0416 .reg = 0x22c,
0417 .bit = 3,
0418 },
0419 .la = {
0420 .reg = 0x354,
0421 .shift = 16,
0422 .mask = 0xff,
0423 .def = 0xff,
0424 },
0425 },
0426 }, {
0427 .id = 0x24,
0428 .name = "vdemcer",
0429 .swgroup = TEGRA_SWGROUP_VDE,
0430 .regs = {
0431 .smmu = {
0432 .reg = 0x22c,
0433 .bit = 4,
0434 },
0435 .la = {
0436 .reg = 0x358,
0437 .shift = 0,
0438 .mask = 0xff,
0439 .def = 0xb8,
0440 },
0441 },
0442 }, {
0443 .id = 0x25,
0444 .name = "vdetper",
0445 .swgroup = TEGRA_SWGROUP_VDE,
0446 .regs = {
0447 .smmu = {
0448 .reg = 0x22c,
0449 .bit = 5,
0450 },
0451 .la = {
0452 .reg = 0x358,
0453 .shift = 16,
0454 .mask = 0xff,
0455 .def = 0xee,
0456 },
0457 },
0458 }, {
0459 .id = 0x26,
0460 .name = "mpcorelpr",
0461 .swgroup = TEGRA_SWGROUP_MPCORELP,
0462 .regs = {
0463 .la = {
0464 .reg = 0x324,
0465 .shift = 0,
0466 .mask = 0xff,
0467 .def = 0x04,
0468 },
0469 },
0470 }, {
0471 .id = 0x27,
0472 .name = "mpcorer",
0473 .swgroup = TEGRA_SWGROUP_MPCORE,
0474 .regs = {
0475 .la = {
0476 .reg = 0x320,
0477 .shift = 0,
0478 .mask = 0xff,
0479 .def = 0x04,
0480 },
0481 },
0482 }, {
0483 .id = 0x28,
0484 .name = "eppu",
0485 .swgroup = TEGRA_SWGROUP_EPP,
0486 .regs = {
0487 .smmu = {
0488 .reg = 0x22c,
0489 .bit = 8,
0490 },
0491 .la = {
0492 .reg = 0x300,
0493 .shift = 16,
0494 .mask = 0xff,
0495 .def = 0x33,
0496 },
0497 },
0498 }, {
0499 .id = 0x29,
0500 .name = "eppv",
0501 .swgroup = TEGRA_SWGROUP_EPP,
0502 .regs = {
0503 .smmu = {
0504 .reg = 0x22c,
0505 .bit = 9,
0506 },
0507 .la = {
0508 .reg = 0x304,
0509 .shift = 0,
0510 .mask = 0xff,
0511 .def = 0x6c,
0512 },
0513 },
0514 }, {
0515 .id = 0x2a,
0516 .name = "eppy",
0517 .swgroup = TEGRA_SWGROUP_EPP,
0518 .regs = {
0519 .smmu = {
0520 .reg = 0x22c,
0521 .bit = 10,
0522 },
0523 .la = {
0524 .reg = 0x304,
0525 .shift = 16,
0526 .mask = 0xff,
0527 .def = 0x6c,
0528 },
0529 },
0530 }, {
0531 .id = 0x2b,
0532 .name = "msencswr",
0533 .swgroup = TEGRA_SWGROUP_MSENC,
0534 .regs = {
0535 .smmu = {
0536 .reg = 0x22c,
0537 .bit = 11,
0538 },
0539 .la = {
0540 .reg = 0x328,
0541 .shift = 16,
0542 .mask = 0xff,
0543 .def = 0x80,
0544 },
0545 },
0546 }, {
0547 .id = 0x2c,
0548 .name = "viwsb",
0549 .swgroup = TEGRA_SWGROUP_VI,
0550 .regs = {
0551 .smmu = {
0552 .reg = 0x22c,
0553 .bit = 12,
0554 },
0555 .la = {
0556 .reg = 0x364,
0557 .shift = 0,
0558 .mask = 0xff,
0559 .def = 0x47,
0560 },
0561 },
0562 }, {
0563 .id = 0x2d,
0564 .name = "viwu",
0565 .swgroup = TEGRA_SWGROUP_VI,
0566 .regs = {
0567 .smmu = {
0568 .reg = 0x22c,
0569 .bit = 13,
0570 },
0571 .la = {
0572 .reg = 0x368,
0573 .shift = 0,
0574 .mask = 0xff,
0575 .def = 0xff,
0576 },
0577 },
0578 }, {
0579 .id = 0x2e,
0580 .name = "viwv",
0581 .swgroup = TEGRA_SWGROUP_VI,
0582 .regs = {
0583 .smmu = {
0584 .reg = 0x22c,
0585 .bit = 14,
0586 },
0587 .la = {
0588 .reg = 0x368,
0589 .shift = 16,
0590 .mask = 0xff,
0591 .def = 0xff,
0592 },
0593 },
0594 }, {
0595 .id = 0x2f,
0596 .name = "viwy",
0597 .swgroup = TEGRA_SWGROUP_VI,
0598 .regs = {
0599 .smmu = {
0600 .reg = 0x22c,
0601 .bit = 15,
0602 },
0603 .la = {
0604 .reg = 0x36c,
0605 .shift = 0,
0606 .mask = 0xff,
0607 .def = 0x47,
0608 },
0609 },
0610 }, {
0611 .id = 0x30,
0612 .name = "g2dw",
0613 .swgroup = TEGRA_SWGROUP_G2,
0614 .regs = {
0615 .smmu = {
0616 .reg = 0x22c,
0617 .bit = 16,
0618 },
0619 .la = {
0620 .reg = 0x30c,
0621 .shift = 16,
0622 .mask = 0xff,
0623 .def = 0x9,
0624 },
0625 },
0626 }, {
0627 .id = 0x32,
0628 .name = "avpcarm7w",
0629 .swgroup = TEGRA_SWGROUP_AVPC,
0630 .regs = {
0631 .smmu = {
0632 .reg = 0x22c,
0633 .bit = 18,
0634 },
0635 .la = {
0636 .reg = 0x2e4,
0637 .shift = 16,
0638 .mask = 0xff,
0639 .def = 0x0e,
0640 },
0641 },
0642 }, {
0643 .id = 0x33,
0644 .name = "fdcdwr",
0645 .swgroup = TEGRA_SWGROUP_NV,
0646 .regs = {
0647 .smmu = {
0648 .reg = 0x22c,
0649 .bit = 19,
0650 },
0651 .la = {
0652 .reg = 0x338,
0653 .shift = 16,
0654 .mask = 0xff,
0655 .def = 0x10,
0656 },
0657 },
0658 }, {
0659 .id = 0x34,
0660 .name = "fdcdwr2",
0661 .swgroup = TEGRA_SWGROUP_NV,
0662 .regs = {
0663 .smmu = {
0664 .reg = 0x22c,
0665 .bit = 20,
0666 },
0667 .la = {
0668 .reg = 0x340,
0669 .shift = 0,
0670 .mask = 0xff,
0671 .def = 0x10,
0672 },
0673 },
0674 }, {
0675 .id = 0x35,
0676 .name = "hdaw",
0677 .swgroup = TEGRA_SWGROUP_HDA,
0678 .regs = {
0679 .smmu = {
0680 .reg = 0x22c,
0681 .bit = 21,
0682 },
0683 .la = {
0684 .reg = 0x318,
0685 .shift = 16,
0686 .mask = 0xff,
0687 .def = 0xff,
0688 },
0689 },
0690 }, {
0691 .id = 0x36,
0692 .name = "host1xw",
0693 .swgroup = TEGRA_SWGROUP_HC,
0694 .regs = {
0695 .smmu = {
0696 .reg = 0x22c,
0697 .bit = 22,
0698 },
0699 .la = {
0700 .reg = 0x314,
0701 .shift = 0,
0702 .mask = 0xff,
0703 .def = 0x25,
0704 },
0705 },
0706 }, {
0707 .id = 0x37,
0708 .name = "ispw",
0709 .swgroup = TEGRA_SWGROUP_ISP,
0710 .regs = {
0711 .smmu = {
0712 .reg = 0x22c,
0713 .bit = 23,
0714 },
0715 .la = {
0716 .reg = 0x31c,
0717 .shift = 0,
0718 .mask = 0xff,
0719 .def = 0xff,
0720 },
0721 },
0722 }, {
0723 .id = 0x38,
0724 .name = "mpcorelpw",
0725 .swgroup = TEGRA_SWGROUP_MPCORELP,
0726 .regs = {
0727 .la = {
0728 .reg = 0x324,
0729 .shift = 16,
0730 .mask = 0xff,
0731 .def = 0x80,
0732 },
0733 },
0734 }, {
0735 .id = 0x39,
0736 .name = "mpcorew",
0737 .swgroup = TEGRA_SWGROUP_MPCORE,
0738 .regs = {
0739 .la = {
0740 .reg = 0x320,
0741 .shift = 16,
0742 .mask = 0xff,
0743 .def = 0x0e,
0744 },
0745 },
0746 }, {
0747 .id = 0x3b,
0748 .name = "ppcsahbdmaw",
0749 .swgroup = TEGRA_SWGROUP_PPCS,
0750 .regs = {
0751 .smmu = {
0752 .reg = 0x22c,
0753 .bit = 27,
0754 },
0755 .la = {
0756 .reg = 0x348,
0757 .shift = 0,
0758 .mask = 0xff,
0759 .def = 0xa5,
0760 },
0761 },
0762 }, {
0763 .id = 0x3c,
0764 .name = "ppcsahbslvw",
0765 .swgroup = TEGRA_SWGROUP_PPCS,
0766 .regs = {
0767 .smmu = {
0768 .reg = 0x22c,
0769 .bit = 28,
0770 },
0771 .la = {
0772 .reg = 0x348,
0773 .shift = 16,
0774 .mask = 0xff,
0775 .def = 0xe8,
0776 },
0777 },
0778 }, {
0779 .id = 0x3e,
0780 .name = "vdebsevw",
0781 .swgroup = TEGRA_SWGROUP_VDE,
0782 .regs = {
0783 .smmu = {
0784 .reg = 0x22c,
0785 .bit = 30,
0786 },
0787 .la = {
0788 .reg = 0x35c,
0789 .shift = 0,
0790 .mask = 0xff,
0791 .def = 0xff,
0792 },
0793 },
0794 }, {
0795 .id = 0x3f,
0796 .name = "vdedbgw",
0797 .swgroup = TEGRA_SWGROUP_VDE,
0798 .regs = {
0799 .smmu = {
0800 .reg = 0x22c,
0801 .bit = 31,
0802 },
0803 .la = {
0804 .reg = 0x35c,
0805 .shift = 16,
0806 .mask = 0xff,
0807 .def = 0xff,
0808 },
0809 },
0810 }, {
0811 .id = 0x40,
0812 .name = "vdembew",
0813 .swgroup = TEGRA_SWGROUP_VDE,
0814 .regs = {
0815 .smmu = {
0816 .reg = 0x230,
0817 .bit = 0,
0818 },
0819 .la = {
0820 .reg = 0x360,
0821 .shift = 0,
0822 .mask = 0xff,
0823 .def = 0x89,
0824 },
0825 },
0826 }, {
0827 .id = 0x41,
0828 .name = "vdetpmw",
0829 .swgroup = TEGRA_SWGROUP_VDE,
0830 .regs = {
0831 .smmu = {
0832 .reg = 0x230,
0833 .bit = 1,
0834 },
0835 .la = {
0836 .reg = 0x360,
0837 .shift = 16,
0838 .mask = 0xff,
0839 .def = 0x59,
0840 },
0841 },
0842 }, {
0843 .id = 0x4a,
0844 .name = "xusb_hostr",
0845 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0846 .regs = {
0847 .smmu = {
0848 .reg = 0x230,
0849 .bit = 10,
0850 },
0851 .la = {
0852 .reg = 0x37c,
0853 .shift = 0,
0854 .mask = 0xff,
0855 .def = 0xa5,
0856 },
0857 },
0858 }, {
0859 .id = 0x4b,
0860 .name = "xusb_hostw",
0861 .swgroup = TEGRA_SWGROUP_XUSB_HOST,
0862 .regs = {
0863 .smmu = {
0864 .reg = 0x230,
0865 .bit = 11,
0866 },
0867 .la = {
0868 .reg = 0x37c,
0869 .shift = 16,
0870 .mask = 0xff,
0871 .def = 0xa5,
0872 },
0873 },
0874 }, {
0875 .id = 0x4c,
0876 .name = "xusb_devr",
0877 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0878 .regs = {
0879 .smmu = {
0880 .reg = 0x230,
0881 .bit = 12,
0882 },
0883 .la = {
0884 .reg = 0x380,
0885 .shift = 0,
0886 .mask = 0xff,
0887 .def = 0xa5,
0888 },
0889 },
0890 }, {
0891 .id = 0x4d,
0892 .name = "xusb_devw",
0893 .swgroup = TEGRA_SWGROUP_XUSB_DEV,
0894 .regs = {
0895 .smmu = {
0896 .reg = 0x230,
0897 .bit = 13,
0898 },
0899 .la = {
0900 .reg = 0x380,
0901 .shift = 16,
0902 .mask = 0xff,
0903 .def = 0xa5,
0904 },
0905 },
0906 }, {
0907 .id = 0x4e,
0908 .name = "fdcdwr3",
0909 .swgroup = TEGRA_SWGROUP_NV,
0910 .regs = {
0911 .smmu = {
0912 .reg = 0x230,
0913 .bit = 14,
0914 },
0915 .la = {
0916 .reg = 0x388,
0917 .shift = 0,
0918 .mask = 0xff,
0919 .def = 0x10,
0920 },
0921 },
0922 }, {
0923 .id = 0x4f,
0924 .name = "fdcdrd3",
0925 .swgroup = TEGRA_SWGROUP_NV,
0926 .regs = {
0927 .smmu = {
0928 .reg = 0x230,
0929 .bit = 15,
0930 },
0931 .la = {
0932 .reg = 0x384,
0933 .shift = 0,
0934 .mask = 0xff,
0935 .def = 0x0c,
0936 },
0937 },
0938 }, {
0939 .id = 0x50,
0940 .name = "fdcwr4",
0941 .swgroup = TEGRA_SWGROUP_NV,
0942 .regs = {
0943 .smmu = {
0944 .reg = 0x230,
0945 .bit = 16,
0946 },
0947 .la = {
0948 .reg = 0x388,
0949 .shift = 16,
0950 .mask = 0xff,
0951 .def = 0x10,
0952 },
0953 },
0954 }, {
0955 .id = 0x51,
0956 .name = "fdcrd4",
0957 .swgroup = TEGRA_SWGROUP_NV,
0958 .regs = {
0959 .smmu = {
0960 .reg = 0x230,
0961 .bit = 17,
0962 },
0963 .la = {
0964 .reg = 0x384,
0965 .shift = 16,
0966 .mask = 0xff,
0967 .def = 0x0c,
0968 },
0969 },
0970 }, {
0971 .id = 0x52,
0972 .name = "emucifr",
0973 .swgroup = TEGRA_SWGROUP_EMUCIF,
0974 .regs = {
0975 .la = {
0976 .reg = 0x38c,
0977 .shift = 0,
0978 .mask = 0xff,
0979 .def = 0x04,
0980 },
0981 },
0982 }, {
0983 .id = 0x53,
0984 .name = "emucifw",
0985 .swgroup = TEGRA_SWGROUP_EMUCIF,
0986 .regs = {
0987 .la = {
0988 .reg = 0x38c,
0989 .shift = 16,
0990 .mask = 0xff,
0991 .def = 0x0e,
0992 },
0993 },
0994 }, {
0995 .id = 0x54,
0996 .name = "tsecsrd",
0997 .swgroup = TEGRA_SWGROUP_TSEC,
0998 .regs = {
0999 .smmu = {
1000 .reg = 0x230,
1001 .bit = 20,
1002 },
1003 .la = {
1004 .reg = 0x390,
1005 .shift = 0,
1006 .mask = 0xff,
1007 .def = 0x50,
1008 },
1009 },
1010 }, {
1011 .id = 0x55,
1012 .name = "tsecswr",
1013 .swgroup = TEGRA_SWGROUP_TSEC,
1014 .regs = {
1015 .smmu = {
1016 .reg = 0x230,
1017 .bit = 21,
1018 },
1019 .la = {
1020 .reg = 0x390,
1021 .shift = 16,
1022 .mask = 0xff,
1023 .def = 0x50,
1024 },
1025 },
1026 },
1027 };
1028
1029 static const struct tegra_smmu_swgroup tegra114_swgroups[] = {
1030 { .name = "dc", .swgroup = TEGRA_SWGROUP_DC, .reg = 0x240 },
1031 { .name = "dcb", .swgroup = TEGRA_SWGROUP_DCB, .reg = 0x244 },
1032 { .name = "epp", .swgroup = TEGRA_SWGROUP_EPP, .reg = 0x248 },
1033 { .name = "g2", .swgroup = TEGRA_SWGROUP_G2, .reg = 0x24c },
1034 { .name = "avpc", .swgroup = TEGRA_SWGROUP_AVPC, .reg = 0x23c },
1035 { .name = "nv", .swgroup = TEGRA_SWGROUP_NV, .reg = 0x268 },
1036 { .name = "hda", .swgroup = TEGRA_SWGROUP_HDA, .reg = 0x254 },
1037 { .name = "hc", .swgroup = TEGRA_SWGROUP_HC, .reg = 0x250 },
1038 { .name = "msenc", .swgroup = TEGRA_SWGROUP_MSENC, .reg = 0x264 },
1039 { .name = "ppcs", .swgroup = TEGRA_SWGROUP_PPCS, .reg = 0x270 },
1040 { .name = "vde", .swgroup = TEGRA_SWGROUP_VDE, .reg = 0x27c },
1041 { .name = "vi", .swgroup = TEGRA_SWGROUP_VI, .reg = 0x280 },
1042 { .name = "isp", .swgroup = TEGRA_SWGROUP_ISP, .reg = 0x258 },
1043 { .name = "xusb_host", .swgroup = TEGRA_SWGROUP_XUSB_HOST, .reg = 0x288 },
1044 { .name = "xusb_dev", .swgroup = TEGRA_SWGROUP_XUSB_DEV, .reg = 0x28c },
1045 { .name = "tsec", .swgroup = TEGRA_SWGROUP_TSEC, .reg = 0x294 },
1046 };
1047
1048 static const unsigned int tegra114_group_drm[] = {
1049 TEGRA_SWGROUP_DC,
1050 TEGRA_SWGROUP_DCB,
1051 TEGRA_SWGROUP_G2,
1052 TEGRA_SWGROUP_NV,
1053 };
1054
1055 static const struct tegra_smmu_group_soc tegra114_groups[] = {
1056 {
1057 .name = "drm",
1058 .swgroups = tegra114_group_drm,
1059 .num_swgroups = ARRAY_SIZE(tegra114_group_drm),
1060 },
1061 };
1062
1063 static const struct tegra_smmu_soc tegra114_smmu_soc = {
1064 .clients = tegra114_mc_clients,
1065 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1066 .swgroups = tegra114_swgroups,
1067 .num_swgroups = ARRAY_SIZE(tegra114_swgroups),
1068 .groups = tegra114_groups,
1069 .num_groups = ARRAY_SIZE(tegra114_groups),
1070 .supports_round_robin_arbitration = false,
1071 .supports_request_limit = false,
1072 .num_tlb_lines = 32,
1073 .num_asids = 4,
1074 };
1075
1076 #define TEGRA114_MC_RESET(_name, _control, _status, _bit) \
1077 { \
1078 .name = #_name, \
1079 .id = TEGRA114_MC_RESET_##_name, \
1080 .control = _control, \
1081 .status = _status, \
1082 .bit = _bit, \
1083 }
1084
1085 static const struct tegra_mc_reset tegra114_mc_resets[] = {
1086 TEGRA114_MC_RESET(AVPC, 0x200, 0x204, 1),
1087 TEGRA114_MC_RESET(DC, 0x200, 0x204, 2),
1088 TEGRA114_MC_RESET(DCB, 0x200, 0x204, 3),
1089 TEGRA114_MC_RESET(EPP, 0x200, 0x204, 4),
1090 TEGRA114_MC_RESET(2D, 0x200, 0x204, 5),
1091 TEGRA114_MC_RESET(HC, 0x200, 0x204, 6),
1092 TEGRA114_MC_RESET(HDA, 0x200, 0x204, 7),
1093 TEGRA114_MC_RESET(ISP, 0x200, 0x204, 8),
1094 TEGRA114_MC_RESET(MPCORE, 0x200, 0x204, 9),
1095 TEGRA114_MC_RESET(MPCORELP, 0x200, 0x204, 10),
1096 TEGRA114_MC_RESET(MPE, 0x200, 0x204, 11),
1097 TEGRA114_MC_RESET(3D, 0x200, 0x204, 12),
1098 TEGRA114_MC_RESET(3D2, 0x200, 0x204, 13),
1099 TEGRA114_MC_RESET(PPCS, 0x200, 0x204, 14),
1100 TEGRA114_MC_RESET(VDE, 0x200, 0x204, 16),
1101 TEGRA114_MC_RESET(VI, 0x200, 0x204, 17),
1102 };
1103
1104 const struct tegra_mc_soc tegra114_mc_soc = {
1105 .clients = tegra114_mc_clients,
1106 .num_clients = ARRAY_SIZE(tegra114_mc_clients),
1107 .num_address_bits = 32,
1108 .atom_size = 32,
1109 .client_id_mask = 0x7f,
1110 .smmu = &tegra114_smmu_soc,
1111 .intmask = MC_INT_INVALID_SMMU_PAGE | MC_INT_SECURITY_VIOLATION |
1112 MC_INT_DECERR_EMEM,
1113 .reset_ops = &tegra_mc_reset_ops_common,
1114 .resets = tegra114_mc_resets,
1115 .num_resets = ARRAY_SIZE(tegra114_mc_resets),
1116 .ops = &tegra30_mc_ops,
1117 };
