memory/tegra/mc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef MEMORY_TEGRA_MC_H
0007 #define MEMORY_TEGRA_MC_H
0008
0009 #include <linux/bits.h>
0010 #include <linux/io.h>
0011 #include <linux/types.h>
0012
0013 #include <soc/tegra/mc.h>
0014
0015 #define MC_INTSTATUS                    0x00
0016 #define MC_INTMASK                  0x04
0017 #define MC_ERR_STATUS                   0x08
0018 #define MC_ERR_ADR                  0x0c
0019 #define MC_GART_ERROR_REQ               0x30
0020 #define MC_EMEM_ADR_CFG                 0x54
0021 #define MC_DECERR_EMEM_OTHERS_STATUS            0x58
0022 #define MC_SECURITY_VIOLATION_STATUS            0x74
0023 #define MC_EMEM_ARB_CFG                 0x90
0024 #define MC_EMEM_ARB_OUTSTANDING_REQ         0x94
0025 #define MC_EMEM_ARB_TIMING_RCD              0x98
0026 #define MC_EMEM_ARB_TIMING_RP               0x9c
0027 #define MC_EMEM_ARB_TIMING_RC               0xa0
0028 #define MC_EMEM_ARB_TIMING_RAS              0xa4
0029 #define MC_EMEM_ARB_TIMING_FAW              0xa8
0030 #define MC_EMEM_ARB_TIMING_RRD              0xac
0031 #define MC_EMEM_ARB_TIMING_RAP2PRE          0xb0
0032 #define MC_EMEM_ARB_TIMING_WAP2PRE          0xb4
0033 #define MC_EMEM_ARB_TIMING_R2R              0xb8
0034 #define MC_EMEM_ARB_TIMING_W2W              0xbc
0035 #define MC_EMEM_ARB_TIMING_R2W              0xc0
0036 #define MC_EMEM_ARB_TIMING_W2R              0xc4
0037 #define MC_EMEM_ARB_MISC2               0xc8
0038 #define MC_EMEM_ARB_DA_TURNS                0xd0
0039 #define MC_EMEM_ARB_DA_COVERS               0xd4
0040 #define MC_EMEM_ARB_MISC0               0xd8
0041 #define MC_EMEM_ARB_MISC1               0xdc
0042 #define MC_EMEM_ARB_RING1_THROTTLE          0xe0
0043 #define MC_EMEM_ARB_OVERRIDE                0xe8
0044 #define MC_TIMING_CONTROL_DBG               0xf8
0045 #define MC_TIMING_CONTROL               0xfc
0046 #define MC_ERR_VPR_STATUS               0x654
0047 #define MC_ERR_VPR_ADR                  0x658
0048 #define MC_ERR_SEC_STATUS               0x67c
0049 #define MC_ERR_SEC_ADR                  0x680
0050 #define MC_ERR_MTS_STATUS               0x9b0
0051 #define MC_ERR_MTS_ADR                  0x9b4
0052 #define MC_ERR_ROUTE_SANITY_STATUS          0x9c0
0053 #define MC_ERR_ROUTE_SANITY_ADR             0x9c4
0054 #define MC_ERR_GENERALIZED_CARVEOUT_STATUS      0xc00
0055 #define MC_ERR_GENERALIZED_CARVEOUT_ADR         0xc04
0056 #define MC_GLOBAL_INTSTATUS             0xf24
0057 #define MC_ERR_ADR_HI                   0x11fc
0058
0059 #define MC_INT_DECERR_ROUTE_SANITY          BIT(20)
0060 #define MC_INT_DECERR_GENERALIZED_CARVEOUT      BIT(17)
0061 #define MC_INT_DECERR_MTS               BIT(16)
0062 #define MC_INT_SECERR_SEC               BIT(13)
0063 #define MC_INT_DECERR_VPR               BIT(12)
0064 #define MC_INT_INVALID_APB_ASID_UPDATE          BIT(11)
0065 #define MC_INT_INVALID_SMMU_PAGE            BIT(10)
0066 #define MC_INT_ARBITRATION_EMEM             BIT(9)
0067 #define MC_INT_SECURITY_VIOLATION           BIT(8)
0068 #define MC_INT_INVALID_GART_PAGE            BIT(7)
0069 #define MC_INT_DECERR_EMEM              BIT(6)
0070
0071 #define MC_ERR_STATUS_TYPE_SHIFT            28
0072 #define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE        (0x6 << 28)
0073 #define MC_ERR_STATUS_TYPE_MASK             (0x7 << 28)
0074 #define MC_ERR_STATUS_READABLE              BIT(27)
0075 #define MC_ERR_STATUS_WRITABLE              BIT(26)
0076 #define MC_ERR_STATUS_NONSECURE             BIT(25)
0077 #define MC_ERR_STATUS_ADR_HI_SHIFT          20
0078 #define MC_ERR_STATUS_ADR_HI_MASK           0x3
0079 #define MC_ERR_STATUS_SECURITY              BIT(17)
0080 #define MC_ERR_STATUS_RW                BIT(16)
0081
0082 #define MC_EMEM_ADR_CFG_EMEM_NUMDEV         BIT(0)
0083
0084 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(x)        ((x) & 0x1ff)
0085 #define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK      0x1ff
0086
0087 #define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK        0x1ff
0088 #define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE    BIT(30)
0089 #define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE    BIT(31)
0090
0091 #define MC_EMEM_ARB_OVERRIDE_EACK_MASK          0x3
0092
0093 #define MC_TIMING_UPDATE                BIT(0)
0094
0095 #define MC_BROADCAST_CHANNEL                ~0
0096
0097 static inline u32 tegra_mc_scale_percents(u64 val, unsigned int percents)
0098 {
0099     val = val * percents;
0100     do_div(val, 100);
0101
0102     return min_t(u64, val, U32_MAX);
0103 }
0104
0105 static inline struct tegra_mc *
0106 icc_provider_to_tegra_mc(struct icc_provider *provider)
0107 {
0108     return container_of(provider, struct tegra_mc, provider);
0109 }
0110
0111 static inline u32 mc_ch_readl(const struct tegra_mc *mc, int ch,
0112                   unsigned long offset)
0113 {
0114     if (!mc->bcast_ch_regs)
0115         return 0;
0116
0117     if (ch == MC_BROADCAST_CHANNEL)
0118         return readl_relaxed(mc->bcast_ch_regs + offset);
0119
0120     return readl_relaxed(mc->ch_regs[ch] + offset);
0121 }
0122
0123 static inline void mc_ch_writel(const struct tegra_mc *mc, int ch,
0124                 u32 value, unsigned long offset)
0125 {
0126     if (!mc->bcast_ch_regs)
0127         return;
0128
0129     if (ch == MC_BROADCAST_CHANNEL)
0130         writel_relaxed(value, mc->bcast_ch_regs + offset);
0131     else
0132         writel_relaxed(value, mc->ch_regs[ch] + offset);
0133 }
0134
0135 static inline u32 mc_readl(const struct tegra_mc *mc, unsigned long offset)
0136 {
0137     return readl_relaxed(mc->regs + offset);
0138 }
0139
0140 static inline void mc_writel(const struct tegra_mc *mc, u32 value,
0141                  unsigned long offset)
0142 {
0143     writel_relaxed(value, mc->regs + offset);
0144 }
0145
0146 extern const struct tegra_mc_reset_ops tegra_mc_reset_ops_common;
0147
0148 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
0149 extern const struct tegra_mc_soc tegra20_mc_soc;
0150 #endif
0151
0152 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
0153 extern const struct tegra_mc_soc tegra30_mc_soc;
0154 #endif
0155
0156 #ifdef CONFIG_ARCH_TEGRA_114_SOC
0157 extern const struct tegra_mc_soc tegra114_mc_soc;
0158 #endif
0159
0160 #ifdef CONFIG_ARCH_TEGRA_124_SOC
0161 extern const struct tegra_mc_soc tegra124_mc_soc;
0162 #endif
0163
0164 #ifdef CONFIG_ARCH_TEGRA_132_SOC
0165 extern const struct tegra_mc_soc tegra132_mc_soc;
0166 #endif
0167
0168 #ifdef CONFIG_ARCH_TEGRA_210_SOC
0169 extern const struct tegra_mc_soc tegra210_mc_soc;
0170 #endif
0171
0172 #ifdef CONFIG_ARCH_TEGRA_186_SOC
0173 extern const struct tegra_mc_soc tegra186_mc_soc;
0174 #endif
0175
0176 #ifdef CONFIG_ARCH_TEGRA_194_SOC
0177 extern const struct tegra_mc_soc tegra194_mc_soc;
0178 #endif
0179
0180 #ifdef CONFIG_ARCH_TEGRA_234_SOC
0181 extern const struct tegra_mc_soc tegra234_mc_soc;
0182 #endif
0183
0184 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
0185     defined(CONFIG_ARCH_TEGRA_114_SOC) || \
0186     defined(CONFIG_ARCH_TEGRA_124_SOC) || \
0187     defined(CONFIG_ARCH_TEGRA_132_SOC) || \
0188     defined(CONFIG_ARCH_TEGRA_210_SOC)
0189 int tegra30_mc_probe(struct tegra_mc *mc);
0190 extern const struct tegra_mc_ops tegra30_mc_ops;
0191 #endif
0192
0193 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
0194     defined(CONFIG_ARCH_TEGRA_194_SOC) || \
0195     defined(CONFIG_ARCH_TEGRA_234_SOC)
0196 extern const struct tegra_mc_ops tegra186_mc_ops;
0197 #endif
0198
0199 irqreturn_t tegra30_mc_handle_irq(int irq, void *data);
0200 extern const char * const tegra_mc_status_names[32];
0201 extern const char * const tegra_mc_error_names[8];
0202
0203 /*
0204  * These IDs are for internal use of Tegra ICC drivers. The ID numbers are
0205  * chosen such that they don't conflict with the device-tree ICC node IDs.
0206  */
0207 #define TEGRA_ICC_MC        1000
0208 #define TEGRA_ICC_EMC       1001
0209 #define TEGRA_ICC_EMEM      1002
0210
0211 #endif /* MEMORY_TEGRA_MC_H */