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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2014 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/export.h>
0010 #include <linux/interrupt.h>
0011 #include <linux/kernel.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_device.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/slab.h>
0017 #include <linux/sort.h>
0018 
0019 #include <soc/tegra/fuse.h>
0020 
0021 #include "mc.h"
0022 
0023 static const struct of_device_id tegra_mc_of_match[] = {
0024 #ifdef CONFIG_ARCH_TEGRA_2x_SOC
0025     { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
0026 #endif
0027 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
0028     { .compatible = "nvidia,tegra30-mc", .data = &tegra30_mc_soc },
0029 #endif
0030 #ifdef CONFIG_ARCH_TEGRA_114_SOC
0031     { .compatible = "nvidia,tegra114-mc", .data = &tegra114_mc_soc },
0032 #endif
0033 #ifdef CONFIG_ARCH_TEGRA_124_SOC
0034     { .compatible = "nvidia,tegra124-mc", .data = &tegra124_mc_soc },
0035 #endif
0036 #ifdef CONFIG_ARCH_TEGRA_132_SOC
0037     { .compatible = "nvidia,tegra132-mc", .data = &tegra132_mc_soc },
0038 #endif
0039 #ifdef CONFIG_ARCH_TEGRA_210_SOC
0040     { .compatible = "nvidia,tegra210-mc", .data = &tegra210_mc_soc },
0041 #endif
0042 #ifdef CONFIG_ARCH_TEGRA_186_SOC
0043     { .compatible = "nvidia,tegra186-mc", .data = &tegra186_mc_soc },
0044 #endif
0045 #ifdef CONFIG_ARCH_TEGRA_194_SOC
0046     { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
0047 #endif
0048 #ifdef CONFIG_ARCH_TEGRA_234_SOC
0049     { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
0050 #endif
0051     { /* sentinel */ }
0052 };
0053 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
0054 
0055 static void tegra_mc_devm_action_put_device(void *data)
0056 {
0057     struct tegra_mc *mc = data;
0058 
0059     put_device(mc->dev);
0060 }
0061 
0062 /**
0063  * devm_tegra_memory_controller_get() - get Tegra Memory Controller handle
0064  * @dev: device pointer for the consumer device
0065  *
0066  * This function will search for the Memory Controller node in a device-tree
0067  * and retrieve the Memory Controller handle.
0068  *
0069  * Return: ERR_PTR() on error or a valid pointer to a struct tegra_mc.
0070  */
0071 struct tegra_mc *devm_tegra_memory_controller_get(struct device *dev)
0072 {
0073     struct platform_device *pdev;
0074     struct device_node *np;
0075     struct tegra_mc *mc;
0076     int err;
0077 
0078     np = of_parse_phandle(dev->of_node, "nvidia,memory-controller", 0);
0079     if (!np)
0080         return ERR_PTR(-ENOENT);
0081 
0082     pdev = of_find_device_by_node(np);
0083     of_node_put(np);
0084     if (!pdev)
0085         return ERR_PTR(-ENODEV);
0086 
0087     mc = platform_get_drvdata(pdev);
0088     if (!mc) {
0089         put_device(&pdev->dev);
0090         return ERR_PTR(-EPROBE_DEFER);
0091     }
0092 
0093     err = devm_add_action_or_reset(dev, tegra_mc_devm_action_put_device, mc);
0094     if (err)
0095         return ERR_PTR(err);
0096 
0097     return mc;
0098 }
0099 EXPORT_SYMBOL_GPL(devm_tegra_memory_controller_get);
0100 
0101 int tegra_mc_probe_device(struct tegra_mc *mc, struct device *dev)
0102 {
0103     if (mc->soc->ops && mc->soc->ops->probe_device)
0104         return mc->soc->ops->probe_device(mc, dev);
0105 
0106     return 0;
0107 }
0108 EXPORT_SYMBOL_GPL(tegra_mc_probe_device);
0109 
0110 static int tegra_mc_block_dma_common(struct tegra_mc *mc,
0111                      const struct tegra_mc_reset *rst)
0112 {
0113     unsigned long flags;
0114     u32 value;
0115 
0116     spin_lock_irqsave(&mc->lock, flags);
0117 
0118     value = mc_readl(mc, rst->control) | BIT(rst->bit);
0119     mc_writel(mc, value, rst->control);
0120 
0121     spin_unlock_irqrestore(&mc->lock, flags);
0122 
0123     return 0;
0124 }
0125 
0126 static bool tegra_mc_dma_idling_common(struct tegra_mc *mc,
0127                        const struct tegra_mc_reset *rst)
0128 {
0129     return (mc_readl(mc, rst->status) & BIT(rst->bit)) != 0;
0130 }
0131 
0132 static int tegra_mc_unblock_dma_common(struct tegra_mc *mc,
0133                        const struct tegra_mc_reset *rst)
0134 {
0135     unsigned long flags;
0136     u32 value;
0137 
0138     spin_lock_irqsave(&mc->lock, flags);
0139 
0140     value = mc_readl(mc, rst->control) & ~BIT(rst->bit);
0141     mc_writel(mc, value, rst->control);
0142 
0143     spin_unlock_irqrestore(&mc->lock, flags);
0144 
0145     return 0;
0146 }
0147 
0148 static int tegra_mc_reset_status_common(struct tegra_mc *mc,
0149                     const struct tegra_mc_reset *rst)
0150 {
0151     return (mc_readl(mc, rst->control) & BIT(rst->bit)) != 0;
0152 }
0153 
0154 const struct tegra_mc_reset_ops tegra_mc_reset_ops_common = {
0155     .block_dma = tegra_mc_block_dma_common,
0156     .dma_idling = tegra_mc_dma_idling_common,
0157     .unblock_dma = tegra_mc_unblock_dma_common,
0158     .reset_status = tegra_mc_reset_status_common,
0159 };
0160 
0161 static inline struct tegra_mc *reset_to_mc(struct reset_controller_dev *rcdev)
0162 {
0163     return container_of(rcdev, struct tegra_mc, reset);
0164 }
0165 
0166 static const struct tegra_mc_reset *tegra_mc_reset_find(struct tegra_mc *mc,
0167                             unsigned long id)
0168 {
0169     unsigned int i;
0170 
0171     for (i = 0; i < mc->soc->num_resets; i++)
0172         if (mc->soc->resets[i].id == id)
0173             return &mc->soc->resets[i];
0174 
0175     return NULL;
0176 }
0177 
0178 static int tegra_mc_hotreset_assert(struct reset_controller_dev *rcdev,
0179                     unsigned long id)
0180 {
0181     struct tegra_mc *mc = reset_to_mc(rcdev);
0182     const struct tegra_mc_reset_ops *rst_ops;
0183     const struct tegra_mc_reset *rst;
0184     int retries = 500;
0185     int err;
0186 
0187     rst = tegra_mc_reset_find(mc, id);
0188     if (!rst)
0189         return -ENODEV;
0190 
0191     rst_ops = mc->soc->reset_ops;
0192     if (!rst_ops)
0193         return -ENODEV;
0194 
0195     /* DMA flushing will fail if reset is already asserted */
0196     if (rst_ops->reset_status) {
0197         /* check whether reset is asserted */
0198         if (rst_ops->reset_status(mc, rst))
0199             return 0;
0200     }
0201 
0202     if (rst_ops->block_dma) {
0203         /* block clients DMA requests */
0204         err = rst_ops->block_dma(mc, rst);
0205         if (err) {
0206             dev_err(mc->dev, "failed to block %s DMA: %d\n",
0207                 rst->name, err);
0208             return err;
0209         }
0210     }
0211 
0212     if (rst_ops->dma_idling) {
0213         /* wait for completion of the outstanding DMA requests */
0214         while (!rst_ops->dma_idling(mc, rst)) {
0215             if (!retries--) {
0216                 dev_err(mc->dev, "failed to flush %s DMA\n",
0217                     rst->name);
0218                 return -EBUSY;
0219             }
0220 
0221             usleep_range(10, 100);
0222         }
0223     }
0224 
0225     if (rst_ops->hotreset_assert) {
0226         /* clear clients DMA requests sitting before arbitration */
0227         err = rst_ops->hotreset_assert(mc, rst);
0228         if (err) {
0229             dev_err(mc->dev, "failed to hot reset %s: %d\n",
0230                 rst->name, err);
0231             return err;
0232         }
0233     }
0234 
0235     return 0;
0236 }
0237 
0238 static int tegra_mc_hotreset_deassert(struct reset_controller_dev *rcdev,
0239                       unsigned long id)
0240 {
0241     struct tegra_mc *mc = reset_to_mc(rcdev);
0242     const struct tegra_mc_reset_ops *rst_ops;
0243     const struct tegra_mc_reset *rst;
0244     int err;
0245 
0246     rst = tegra_mc_reset_find(mc, id);
0247     if (!rst)
0248         return -ENODEV;
0249 
0250     rst_ops = mc->soc->reset_ops;
0251     if (!rst_ops)
0252         return -ENODEV;
0253 
0254     if (rst_ops->hotreset_deassert) {
0255         /* take out client from hot reset */
0256         err = rst_ops->hotreset_deassert(mc, rst);
0257         if (err) {
0258             dev_err(mc->dev, "failed to deassert hot reset %s: %d\n",
0259                 rst->name, err);
0260             return err;
0261         }
0262     }
0263 
0264     if (rst_ops->unblock_dma) {
0265         /* allow new DMA requests to proceed to arbitration */
0266         err = rst_ops->unblock_dma(mc, rst);
0267         if (err) {
0268             dev_err(mc->dev, "failed to unblock %s DMA : %d\n",
0269                 rst->name, err);
0270             return err;
0271         }
0272     }
0273 
0274     return 0;
0275 }
0276 
0277 static int tegra_mc_hotreset_status(struct reset_controller_dev *rcdev,
0278                     unsigned long id)
0279 {
0280     struct tegra_mc *mc = reset_to_mc(rcdev);
0281     const struct tegra_mc_reset_ops *rst_ops;
0282     const struct tegra_mc_reset *rst;
0283 
0284     rst = tegra_mc_reset_find(mc, id);
0285     if (!rst)
0286         return -ENODEV;
0287 
0288     rst_ops = mc->soc->reset_ops;
0289     if (!rst_ops)
0290         return -ENODEV;
0291 
0292     return rst_ops->reset_status(mc, rst);
0293 }
0294 
0295 static const struct reset_control_ops tegra_mc_reset_ops = {
0296     .assert = tegra_mc_hotreset_assert,
0297     .deassert = tegra_mc_hotreset_deassert,
0298     .status = tegra_mc_hotreset_status,
0299 };
0300 
0301 static int tegra_mc_reset_setup(struct tegra_mc *mc)
0302 {
0303     int err;
0304 
0305     mc->reset.ops = &tegra_mc_reset_ops;
0306     mc->reset.owner = THIS_MODULE;
0307     mc->reset.of_node = mc->dev->of_node;
0308     mc->reset.of_reset_n_cells = 1;
0309     mc->reset.nr_resets = mc->soc->num_resets;
0310 
0311     err = reset_controller_register(&mc->reset);
0312     if (err < 0)
0313         return err;
0314 
0315     return 0;
0316 }
0317 
0318 int tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)
0319 {
0320     unsigned int i;
0321     struct tegra_mc_timing *timing = NULL;
0322 
0323     for (i = 0; i < mc->num_timings; i++) {
0324         if (mc->timings[i].rate == rate) {
0325             timing = &mc->timings[i];
0326             break;
0327         }
0328     }
0329 
0330     if (!timing) {
0331         dev_err(mc->dev, "no memory timing registered for rate %lu\n",
0332             rate);
0333         return -EINVAL;
0334     }
0335 
0336     for (i = 0; i < mc->soc->num_emem_regs; ++i)
0337         mc_writel(mc, timing->emem_data[i], mc->soc->emem_regs[i]);
0338 
0339     return 0;
0340 }
0341 EXPORT_SYMBOL_GPL(tegra_mc_write_emem_configuration);
0342 
0343 unsigned int tegra_mc_get_emem_device_count(struct tegra_mc *mc)
0344 {
0345     u8 dram_count;
0346 
0347     dram_count = mc_readl(mc, MC_EMEM_ADR_CFG);
0348     dram_count &= MC_EMEM_ADR_CFG_EMEM_NUMDEV;
0349     dram_count++;
0350 
0351     return dram_count;
0352 }
0353 EXPORT_SYMBOL_GPL(tegra_mc_get_emem_device_count);
0354 
0355 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
0356     defined(CONFIG_ARCH_TEGRA_114_SOC) || \
0357     defined(CONFIG_ARCH_TEGRA_124_SOC) || \
0358     defined(CONFIG_ARCH_TEGRA_132_SOC) || \
0359     defined(CONFIG_ARCH_TEGRA_210_SOC)
0360 static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)
0361 {
0362     unsigned long long tick;
0363     unsigned int i;
0364     u32 value;
0365 
0366     /* compute the number of MC clock cycles per tick */
0367     tick = (unsigned long long)mc->tick * clk_get_rate(mc->clk);
0368     do_div(tick, NSEC_PER_SEC);
0369 
0370     value = mc_readl(mc, MC_EMEM_ARB_CFG);
0371     value &= ~MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK;
0372     value |= MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE(tick);
0373     mc_writel(mc, value, MC_EMEM_ARB_CFG);
0374 
0375     /* write latency allowance defaults */
0376     for (i = 0; i < mc->soc->num_clients; i++) {
0377         const struct tegra_mc_client *client = &mc->soc->clients[i];
0378         u32 value;
0379 
0380         value = mc_readl(mc, client->regs.la.reg);
0381         value &= ~(client->regs.la.mask << client->regs.la.shift);
0382         value |= (client->regs.la.def & client->regs.la.mask) << client->regs.la.shift;
0383         mc_writel(mc, value, client->regs.la.reg);
0384     }
0385 
0386     /* latch new values */
0387     mc_writel(mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL);
0388 
0389     return 0;
0390 }
0391 
0392 static int load_one_timing(struct tegra_mc *mc,
0393                struct tegra_mc_timing *timing,
0394                struct device_node *node)
0395 {
0396     int err;
0397     u32 tmp;
0398 
0399     err = of_property_read_u32(node, "clock-frequency", &tmp);
0400     if (err) {
0401         dev_err(mc->dev,
0402             "timing %pOFn: failed to read rate\n", node);
0403         return err;
0404     }
0405 
0406     timing->rate = tmp;
0407     timing->emem_data = devm_kcalloc(mc->dev, mc->soc->num_emem_regs,
0408                      sizeof(u32), GFP_KERNEL);
0409     if (!timing->emem_data)
0410         return -ENOMEM;
0411 
0412     err = of_property_read_u32_array(node, "nvidia,emem-configuration",
0413                      timing->emem_data,
0414                      mc->soc->num_emem_regs);
0415     if (err) {
0416         dev_err(mc->dev,
0417             "timing %pOFn: failed to read EMEM configuration\n",
0418             node);
0419         return err;
0420     }
0421 
0422     return 0;
0423 }
0424 
0425 static int load_timings(struct tegra_mc *mc, struct device_node *node)
0426 {
0427     struct device_node *child;
0428     struct tegra_mc_timing *timing;
0429     int child_count = of_get_child_count(node);
0430     int i = 0, err;
0431 
0432     mc->timings = devm_kcalloc(mc->dev, child_count, sizeof(*timing),
0433                    GFP_KERNEL);
0434     if (!mc->timings)
0435         return -ENOMEM;
0436 
0437     mc->num_timings = child_count;
0438 
0439     for_each_child_of_node(node, child) {
0440         timing = &mc->timings[i++];
0441 
0442         err = load_one_timing(mc, timing, child);
0443         if (err) {
0444             of_node_put(child);
0445             return err;
0446         }
0447     }
0448 
0449     return 0;
0450 }
0451 
0452 static int tegra_mc_setup_timings(struct tegra_mc *mc)
0453 {
0454     struct device_node *node;
0455     u32 ram_code, node_ram_code;
0456     int err;
0457 
0458     ram_code = tegra_read_ram_code();
0459 
0460     mc->num_timings = 0;
0461 
0462     for_each_child_of_node(mc->dev->of_node, node) {
0463         err = of_property_read_u32(node, "nvidia,ram-code",
0464                        &node_ram_code);
0465         if (err || (node_ram_code != ram_code))
0466             continue;
0467 
0468         err = load_timings(mc, node);
0469         of_node_put(node);
0470         if (err)
0471             return err;
0472         break;
0473     }
0474 
0475     if (mc->num_timings == 0)
0476         dev_warn(mc->dev,
0477              "no memory timings for RAM code %u registered\n",
0478              ram_code);
0479 
0480     return 0;
0481 }
0482 
0483 int tegra30_mc_probe(struct tegra_mc *mc)
0484 {
0485     int err;
0486 
0487     mc->clk = devm_clk_get_optional(mc->dev, "mc");
0488     if (IS_ERR(mc->clk)) {
0489         dev_err(mc->dev, "failed to get MC clock: %ld\n", PTR_ERR(mc->clk));
0490         return PTR_ERR(mc->clk);
0491     }
0492 
0493     /* ensure that debug features are disabled */
0494     mc_writel(mc, 0x00000000, MC_TIMING_CONTROL_DBG);
0495 
0496     err = tegra_mc_setup_latency_allowance(mc);
0497     if (err < 0) {
0498         dev_err(mc->dev, "failed to setup latency allowance: %d\n", err);
0499         return err;
0500     }
0501 
0502     err = tegra_mc_setup_timings(mc);
0503     if (err < 0) {
0504         dev_err(mc->dev, "failed to setup timings: %d\n", err);
0505         return err;
0506     }
0507 
0508     return 0;
0509 }
0510 
0511 const struct tegra_mc_ops tegra30_mc_ops = {
0512     .probe = tegra30_mc_probe,
0513     .handle_irq = tegra30_mc_handle_irq,
0514 };
0515 #endif
0516 
0517 static int mc_global_intstatus_to_channel(const struct tegra_mc *mc, u32 status,
0518                       unsigned int *mc_channel)
0519 {
0520     if ((status & mc->soc->ch_intmask) == 0)
0521         return -EINVAL;
0522 
0523     *mc_channel = __ffs((status & mc->soc->ch_intmask) >>
0524                 mc->soc->global_intstatus_channel_shift);
0525 
0526     return 0;
0527 }
0528 
0529 static u32 mc_channel_to_global_intstatus(const struct tegra_mc *mc,
0530                       unsigned int channel)
0531 {
0532     return BIT(channel) << mc->soc->global_intstatus_channel_shift;
0533 }
0534 
0535 irqreturn_t tegra30_mc_handle_irq(int irq, void *data)
0536 {
0537     struct tegra_mc *mc = data;
0538     unsigned int bit, channel;
0539     unsigned long status;
0540 
0541     if (mc->soc->num_channels) {
0542         u32 global_status;
0543         int err;
0544 
0545         global_status = mc_ch_readl(mc, MC_BROADCAST_CHANNEL, MC_GLOBAL_INTSTATUS);
0546         err = mc_global_intstatus_to_channel(mc, global_status, &channel);
0547         if (err < 0) {
0548             dev_err_ratelimited(mc->dev, "unknown interrupt channel 0x%08x\n",
0549                         global_status);
0550             return IRQ_NONE;
0551         }
0552 
0553         /* mask all interrupts to avoid flooding */
0554         status = mc_ch_readl(mc, channel, MC_INTSTATUS) & mc->soc->intmask;
0555     } else {
0556         status = mc_readl(mc, MC_INTSTATUS) & mc->soc->intmask;
0557     }
0558 
0559     if (!status)
0560         return IRQ_NONE;
0561 
0562     for_each_set_bit(bit, &status, 32) {
0563         const char *error = tegra_mc_status_names[bit] ?: "unknown";
0564         const char *client = "unknown", *desc;
0565         const char *direction, *secure;
0566         u32 status_reg, addr_reg;
0567         u32 intmask = BIT(bit);
0568         phys_addr_t addr = 0;
0569 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0570         u32 addr_hi_reg = 0;
0571 #endif
0572         unsigned int i;
0573         char perm[7];
0574         u8 id, type;
0575         u32 value;
0576 
0577         switch (intmask) {
0578         case MC_INT_DECERR_VPR:
0579             status_reg = MC_ERR_VPR_STATUS;
0580             addr_reg = MC_ERR_VPR_ADR;
0581             break;
0582 
0583         case MC_INT_SECERR_SEC:
0584             status_reg = MC_ERR_SEC_STATUS;
0585             addr_reg = MC_ERR_SEC_ADR;
0586             break;
0587 
0588         case MC_INT_DECERR_MTS:
0589             status_reg = MC_ERR_MTS_STATUS;
0590             addr_reg = MC_ERR_MTS_ADR;
0591             break;
0592 
0593         case MC_INT_DECERR_GENERALIZED_CARVEOUT:
0594             status_reg = MC_ERR_GENERALIZED_CARVEOUT_STATUS;
0595             addr_reg = MC_ERR_GENERALIZED_CARVEOUT_ADR;
0596             break;
0597 
0598         case MC_INT_DECERR_ROUTE_SANITY:
0599             status_reg = MC_ERR_ROUTE_SANITY_STATUS;
0600             addr_reg = MC_ERR_ROUTE_SANITY_ADR;
0601             break;
0602 
0603         default:
0604             status_reg = MC_ERR_STATUS;
0605             addr_reg = MC_ERR_ADR;
0606 
0607 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0608             if (mc->soc->has_addr_hi_reg)
0609                 addr_hi_reg = MC_ERR_ADR_HI;
0610 #endif
0611             break;
0612         }
0613 
0614         if (mc->soc->num_channels)
0615             value = mc_ch_readl(mc, channel, status_reg);
0616         else
0617             value = mc_readl(mc, status_reg);
0618 
0619 #ifdef CONFIG_PHYS_ADDR_T_64BIT
0620         if (mc->soc->num_address_bits > 32) {
0621             if (addr_hi_reg) {
0622                 if (mc->soc->num_channels)
0623                     addr = mc_ch_readl(mc, channel, addr_hi_reg);
0624                 else
0625                     addr = mc_readl(mc, addr_hi_reg);
0626             } else {
0627                 addr = ((value >> MC_ERR_STATUS_ADR_HI_SHIFT) &
0628                     MC_ERR_STATUS_ADR_HI_MASK);
0629             }
0630             addr <<= 32;
0631         }
0632 #endif
0633 
0634         if (value & MC_ERR_STATUS_RW)
0635             direction = "write";
0636         else
0637             direction = "read";
0638 
0639         if (value & MC_ERR_STATUS_SECURITY)
0640             secure = "secure ";
0641         else
0642             secure = "";
0643 
0644         id = value & mc->soc->client_id_mask;
0645 
0646         for (i = 0; i < mc->soc->num_clients; i++) {
0647             if (mc->soc->clients[i].id == id) {
0648                 client = mc->soc->clients[i].name;
0649                 break;
0650             }
0651         }
0652 
0653         type = (value & MC_ERR_STATUS_TYPE_MASK) >>
0654                MC_ERR_STATUS_TYPE_SHIFT;
0655         desc = tegra_mc_error_names[type];
0656 
0657         switch (value & MC_ERR_STATUS_TYPE_MASK) {
0658         case MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE:
0659             perm[0] = ' ';
0660             perm[1] = '[';
0661 
0662             if (value & MC_ERR_STATUS_READABLE)
0663                 perm[2] = 'R';
0664             else
0665                 perm[2] = '-';
0666 
0667             if (value & MC_ERR_STATUS_WRITABLE)
0668                 perm[3] = 'W';
0669             else
0670                 perm[3] = '-';
0671 
0672             if (value & MC_ERR_STATUS_NONSECURE)
0673                 perm[4] = '-';
0674             else
0675                 perm[4] = 'S';
0676 
0677             perm[5] = ']';
0678             perm[6] = '\0';
0679             break;
0680 
0681         default:
0682             perm[0] = '\0';
0683             break;
0684         }
0685 
0686         if (mc->soc->num_channels)
0687             value = mc_ch_readl(mc, channel, addr_reg);
0688         else
0689             value = mc_readl(mc, addr_reg);
0690         addr |= value;
0691 
0692         dev_err_ratelimited(mc->dev, "%s: %s%s @%pa: %s (%s%s)\n",
0693                     client, secure, direction, &addr, error,
0694                     desc, perm);
0695     }
0696 
0697     /* clear interrupts */
0698     if (mc->soc->num_channels) {
0699         mc_ch_writel(mc, channel, status, MC_INTSTATUS);
0700         mc_ch_writel(mc, MC_BROADCAST_CHANNEL,
0701                  mc_channel_to_global_intstatus(mc, channel),
0702                  MC_GLOBAL_INTSTATUS);
0703     } else {
0704         mc_writel(mc, status, MC_INTSTATUS);
0705     }
0706 
0707     return IRQ_HANDLED;
0708 }
0709 
0710 const char *const tegra_mc_status_names[32] = {
0711     [ 1] = "External interrupt",
0712     [ 6] = "EMEM address decode error",
0713     [ 7] = "GART page fault",
0714     [ 8] = "Security violation",
0715     [ 9] = "EMEM arbitration error",
0716     [10] = "Page fault",
0717     [11] = "Invalid APB ASID update",
0718     [12] = "VPR violation",
0719     [13] = "Secure carveout violation",
0720     [16] = "MTS carveout violation",
0721     [17] = "Generalized carveout violation",
0722     [20] = "Route Sanity error",
0723 };
0724 
0725 const char *const tegra_mc_error_names[8] = {
0726     [2] = "EMEM decode error",
0727     [3] = "TrustZone violation",
0728     [4] = "Carveout violation",
0729     [6] = "SMMU translation error",
0730 };
0731 
0732 /*
0733  * Memory Controller (MC) has few Memory Clients that are issuing memory
0734  * bandwidth allocation requests to the MC interconnect provider. The MC
0735  * provider aggregates the requests and then sends the aggregated request
0736  * up to the External Memory Controller (EMC) interconnect provider which
0737  * re-configures hardware interface to External Memory (EMEM) in accordance
0738  * to the required bandwidth. Each MC interconnect node represents an
0739  * individual Memory Client.
0740  *
0741  * Memory interconnect topology:
0742  *
0743  *               +----+
0744  * +--------+    |    |
0745  * | TEXSRD +--->+    |
0746  * +--------+    |    |
0747  *               |    |    +-----+    +------+
0748  *    ...        | MC +--->+ EMC +--->+ EMEM |
0749  *               |    |    +-----+    +------+
0750  * +--------+    |    |
0751  * | DISP.. +--->+    |
0752  * +--------+    |    |
0753  *               +----+
0754  */
0755 static int tegra_mc_interconnect_setup(struct tegra_mc *mc)
0756 {
0757     struct icc_node *node;
0758     unsigned int i;
0759     int err;
0760 
0761     /* older device-trees don't have interconnect properties */
0762     if (!device_property_present(mc->dev, "#interconnect-cells") ||
0763         !mc->soc->icc_ops)
0764         return 0;
0765 
0766     mc->provider.dev = mc->dev;
0767     mc->provider.data = &mc->provider;
0768     mc->provider.set = mc->soc->icc_ops->set;
0769     mc->provider.aggregate = mc->soc->icc_ops->aggregate;
0770     mc->provider.xlate_extended = mc->soc->icc_ops->xlate_extended;
0771 
0772     err = icc_provider_add(&mc->provider);
0773     if (err)
0774         return err;
0775 
0776     /* create Memory Controller node */
0777     node = icc_node_create(TEGRA_ICC_MC);
0778     if (IS_ERR(node)) {
0779         err = PTR_ERR(node);
0780         goto del_provider;
0781     }
0782 
0783     node->name = "Memory Controller";
0784     icc_node_add(node, &mc->provider);
0785 
0786     /* link Memory Controller to External Memory Controller */
0787     err = icc_link_create(node, TEGRA_ICC_EMC);
0788     if (err)
0789         goto remove_nodes;
0790 
0791     for (i = 0; i < mc->soc->num_clients; i++) {
0792         /* create MC client node */
0793         node = icc_node_create(mc->soc->clients[i].id);
0794         if (IS_ERR(node)) {
0795             err = PTR_ERR(node);
0796             goto remove_nodes;
0797         }
0798 
0799         node->name = mc->soc->clients[i].name;
0800         icc_node_add(node, &mc->provider);
0801 
0802         /* link Memory Client to Memory Controller */
0803         err = icc_link_create(node, TEGRA_ICC_MC);
0804         if (err)
0805             goto remove_nodes;
0806     }
0807 
0808     return 0;
0809 
0810 remove_nodes:
0811     icc_nodes_remove(&mc->provider);
0812 del_provider:
0813     icc_provider_del(&mc->provider);
0814 
0815     return err;
0816 }
0817 
0818 static int tegra_mc_probe(struct platform_device *pdev)
0819 {
0820     struct tegra_mc *mc;
0821     u64 mask;
0822     int err;
0823 
0824     mc = devm_kzalloc(&pdev->dev, sizeof(*mc), GFP_KERNEL);
0825     if (!mc)
0826         return -ENOMEM;
0827 
0828     platform_set_drvdata(pdev, mc);
0829     spin_lock_init(&mc->lock);
0830     mc->soc = of_device_get_match_data(&pdev->dev);
0831     mc->dev = &pdev->dev;
0832 
0833     mask = DMA_BIT_MASK(mc->soc->num_address_bits);
0834 
0835     err = dma_coerce_mask_and_coherent(&pdev->dev, mask);
0836     if (err < 0) {
0837         dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
0838         return err;
0839     }
0840 
0841     /* length of MC tick in nanoseconds */
0842     mc->tick = 30;
0843 
0844     mc->regs = devm_platform_ioremap_resource(pdev, 0);
0845     if (IS_ERR(mc->regs))
0846         return PTR_ERR(mc->regs);
0847 
0848     mc->debugfs.root = debugfs_create_dir("mc", NULL);
0849 
0850     if (mc->soc->ops && mc->soc->ops->probe) {
0851         err = mc->soc->ops->probe(mc);
0852         if (err < 0)
0853             return err;
0854     }
0855 
0856     if (mc->soc->ops && mc->soc->ops->handle_irq) {
0857         mc->irq = platform_get_irq(pdev, 0);
0858         if (mc->irq < 0)
0859             return mc->irq;
0860 
0861         WARN(!mc->soc->client_id_mask, "missing client ID mask for this SoC\n");
0862 
0863         if (mc->soc->num_channels)
0864             mc_ch_writel(mc, MC_BROADCAST_CHANNEL, mc->soc->intmask,
0865                      MC_INTMASK);
0866         else
0867             mc_writel(mc, mc->soc->intmask, MC_INTMASK);
0868 
0869         err = devm_request_irq(&pdev->dev, mc->irq, mc->soc->ops->handle_irq, 0,
0870                        dev_name(&pdev->dev), mc);
0871         if (err < 0) {
0872             dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n", mc->irq,
0873                 err);
0874             return err;
0875         }
0876     }
0877 
0878     if (mc->soc->reset_ops) {
0879         err = tegra_mc_reset_setup(mc);
0880         if (err < 0)
0881             dev_err(&pdev->dev, "failed to register reset controller: %d\n", err);
0882     }
0883 
0884     err = tegra_mc_interconnect_setup(mc);
0885     if (err < 0)
0886         dev_err(&pdev->dev, "failed to initialize interconnect: %d\n",
0887             err);
0888 
0889     if (IS_ENABLED(CONFIG_TEGRA_IOMMU_SMMU) && mc->soc->smmu) {
0890         mc->smmu = tegra_smmu_probe(&pdev->dev, mc->soc->smmu, mc);
0891         if (IS_ERR(mc->smmu)) {
0892             dev_err(&pdev->dev, "failed to probe SMMU: %ld\n",
0893                 PTR_ERR(mc->smmu));
0894             mc->smmu = NULL;
0895         }
0896     }
0897 
0898     if (IS_ENABLED(CONFIG_TEGRA_IOMMU_GART) && !mc->soc->smmu) {
0899         mc->gart = tegra_gart_probe(&pdev->dev, mc);
0900         if (IS_ERR(mc->gart)) {
0901             dev_err(&pdev->dev, "failed to probe GART: %ld\n",
0902                 PTR_ERR(mc->gart));
0903             mc->gart = NULL;
0904         }
0905     }
0906 
0907     return 0;
0908 }
0909 
0910 static int __maybe_unused tegra_mc_suspend(struct device *dev)
0911 {
0912     struct tegra_mc *mc = dev_get_drvdata(dev);
0913 
0914     if (mc->soc->ops && mc->soc->ops->suspend)
0915         return mc->soc->ops->suspend(mc);
0916 
0917     return 0;
0918 }
0919 
0920 static int __maybe_unused tegra_mc_resume(struct device *dev)
0921 {
0922     struct tegra_mc *mc = dev_get_drvdata(dev);
0923 
0924     if (mc->soc->ops && mc->soc->ops->resume)
0925         return mc->soc->ops->resume(mc);
0926 
0927     return 0;
0928 }
0929 
0930 static void tegra_mc_sync_state(struct device *dev)
0931 {
0932     struct tegra_mc *mc = dev_get_drvdata(dev);
0933 
0934     /* check whether ICC provider is registered */
0935     if (mc->provider.dev == dev)
0936         icc_sync_state(dev);
0937 }
0938 
0939 static const struct dev_pm_ops tegra_mc_pm_ops = {
0940     SET_SYSTEM_SLEEP_PM_OPS(tegra_mc_suspend, tegra_mc_resume)
0941 };
0942 
0943 static struct platform_driver tegra_mc_driver = {
0944     .driver = {
0945         .name = "tegra-mc",
0946         .of_match_table = tegra_mc_of_match,
0947         .pm = &tegra_mc_pm_ops,
0948         .suppress_bind_attrs = true,
0949         .sync_state = tegra_mc_sync_state,
0950     },
0951     .prevent_deferred_probe = true,
0952     .probe = tegra_mc_probe,
0953 };
0954 
0955 static int tegra_mc_init(void)
0956 {
0957     return platform_driver_register(&tegra_mc_driver);
0958 }
0959 arch_initcall(tegra_mc_init);
0960 
0961 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
0962 MODULE_DESCRIPTION("NVIDIA Tegra Memory Controller driver");
0963 MODULE_LICENSE("GPL v2");
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