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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics 2020
0004  */
0005 
0006 #include <linux/bitfield.h>
0007 #include <linux/clk.h>
0008 #include <linux/mfd/syscon.h>
0009 #include <linux/module.h>
0010 #include <linux/of_platform.h>
0011 #include <linux/pinctrl/consumer.h>
0012 #include <linux/regmap.h>
0013 #include <linux/reset.h>
0014 
0015 /* FMC2 Controller Registers */
0016 #define FMC2_BCR1           0x0
0017 #define FMC2_BTR1           0x4
0018 #define FMC2_BCR(x)         ((x) * 0x8 + FMC2_BCR1)
0019 #define FMC2_BTR(x)         ((x) * 0x8 + FMC2_BTR1)
0020 #define FMC2_PCSCNTR            0x20
0021 #define FMC2_BWTR1          0x104
0022 #define FMC2_BWTR(x)            ((x) * 0x8 + FMC2_BWTR1)
0023 
0024 /* Register: FMC2_BCR1 */
0025 #define FMC2_BCR1_CCLKEN        BIT(20)
0026 #define FMC2_BCR1_FMC2EN        BIT(31)
0027 
0028 /* Register: FMC2_BCRx */
0029 #define FMC2_BCR_MBKEN          BIT(0)
0030 #define FMC2_BCR_MUXEN          BIT(1)
0031 #define FMC2_BCR_MTYP           GENMASK(3, 2)
0032 #define FMC2_BCR_MWID           GENMASK(5, 4)
0033 #define FMC2_BCR_FACCEN         BIT(6)
0034 #define FMC2_BCR_BURSTEN        BIT(8)
0035 #define FMC2_BCR_WAITPOL        BIT(9)
0036 #define FMC2_BCR_WAITCFG        BIT(11)
0037 #define FMC2_BCR_WREN           BIT(12)
0038 #define FMC2_BCR_WAITEN         BIT(13)
0039 #define FMC2_BCR_EXTMOD         BIT(14)
0040 #define FMC2_BCR_ASYNCWAIT      BIT(15)
0041 #define FMC2_BCR_CPSIZE         GENMASK(18, 16)
0042 #define FMC2_BCR_CBURSTRW       BIT(19)
0043 #define FMC2_BCR_NBLSET         GENMASK(23, 22)
0044 
0045 /* Register: FMC2_BTRx/FMC2_BWTRx */
0046 #define FMC2_BXTR_ADDSET        GENMASK(3, 0)
0047 #define FMC2_BXTR_ADDHLD        GENMASK(7, 4)
0048 #define FMC2_BXTR_DATAST        GENMASK(15, 8)
0049 #define FMC2_BXTR_BUSTURN       GENMASK(19, 16)
0050 #define FMC2_BTR_CLKDIV         GENMASK(23, 20)
0051 #define FMC2_BTR_DATLAT         GENMASK(27, 24)
0052 #define FMC2_BXTR_ACCMOD        GENMASK(29, 28)
0053 #define FMC2_BXTR_DATAHLD       GENMASK(31, 30)
0054 
0055 /* Register: FMC2_PCSCNTR */
0056 #define FMC2_PCSCNTR_CSCOUNT        GENMASK(15, 0)
0057 #define FMC2_PCSCNTR_CNTBEN(x)      BIT((x) + 16)
0058 
0059 #define FMC2_MAX_EBI_CE         4
0060 #define FMC2_MAX_BANKS          5
0061 
0062 #define FMC2_BCR_CPSIZE_0       0x0
0063 #define FMC2_BCR_CPSIZE_128     0x1
0064 #define FMC2_BCR_CPSIZE_256     0x2
0065 #define FMC2_BCR_CPSIZE_512     0x3
0066 #define FMC2_BCR_CPSIZE_1024        0x4
0067 
0068 #define FMC2_BCR_MWID_8         0x0
0069 #define FMC2_BCR_MWID_16        0x1
0070 
0071 #define FMC2_BCR_MTYP_SRAM      0x0
0072 #define FMC2_BCR_MTYP_PSRAM     0x1
0073 #define FMC2_BCR_MTYP_NOR       0x2
0074 
0075 #define FMC2_BXTR_EXTMOD_A      0x0
0076 #define FMC2_BXTR_EXTMOD_B      0x1
0077 #define FMC2_BXTR_EXTMOD_C      0x2
0078 #define FMC2_BXTR_EXTMOD_D      0x3
0079 
0080 #define FMC2_BCR_NBLSET_MAX     0x3
0081 #define FMC2_BXTR_ADDSET_MAX        0xf
0082 #define FMC2_BXTR_ADDHLD_MAX        0xf
0083 #define FMC2_BXTR_DATAST_MAX        0xff
0084 #define FMC2_BXTR_BUSTURN_MAX       0xf
0085 #define FMC2_BXTR_DATAHLD_MAX       0x3
0086 #define FMC2_BTR_CLKDIV_MAX     0xf
0087 #define FMC2_BTR_DATLAT_MAX     0xf
0088 #define FMC2_PCSCNTR_CSCOUNT_MAX    0xff
0089 
0090 enum stm32_fmc2_ebi_bank {
0091     FMC2_EBI1 = 0,
0092     FMC2_EBI2,
0093     FMC2_EBI3,
0094     FMC2_EBI4,
0095     FMC2_NAND
0096 };
0097 
0098 enum stm32_fmc2_ebi_register_type {
0099     FMC2_REG_BCR = 1,
0100     FMC2_REG_BTR,
0101     FMC2_REG_BWTR,
0102     FMC2_REG_PCSCNTR
0103 };
0104 
0105 enum stm32_fmc2_ebi_transaction_type {
0106     FMC2_ASYNC_MODE_1_SRAM = 0,
0107     FMC2_ASYNC_MODE_1_PSRAM,
0108     FMC2_ASYNC_MODE_A_SRAM,
0109     FMC2_ASYNC_MODE_A_PSRAM,
0110     FMC2_ASYNC_MODE_2_NOR,
0111     FMC2_ASYNC_MODE_B_NOR,
0112     FMC2_ASYNC_MODE_C_NOR,
0113     FMC2_ASYNC_MODE_D_NOR,
0114     FMC2_SYNC_READ_SYNC_WRITE_PSRAM,
0115     FMC2_SYNC_READ_ASYNC_WRITE_PSRAM,
0116     FMC2_SYNC_READ_SYNC_WRITE_NOR,
0117     FMC2_SYNC_READ_ASYNC_WRITE_NOR
0118 };
0119 
0120 enum stm32_fmc2_ebi_buswidth {
0121     FMC2_BUSWIDTH_8 = 8,
0122     FMC2_BUSWIDTH_16 = 16
0123 };
0124 
0125 enum stm32_fmc2_ebi_cpsize {
0126     FMC2_CPSIZE_0 = 0,
0127     FMC2_CPSIZE_128 = 128,
0128     FMC2_CPSIZE_256 = 256,
0129     FMC2_CPSIZE_512 = 512,
0130     FMC2_CPSIZE_1024 = 1024
0131 };
0132 
0133 struct stm32_fmc2_ebi {
0134     struct device *dev;
0135     struct clk *clk;
0136     struct regmap *regmap;
0137     u8 bank_assigned;
0138 
0139     u32 bcr[FMC2_MAX_EBI_CE];
0140     u32 btr[FMC2_MAX_EBI_CE];
0141     u32 bwtr[FMC2_MAX_EBI_CE];
0142     u32 pcscntr;
0143 };
0144 
0145 /*
0146  * struct stm32_fmc2_prop - STM32 FMC2 EBI property
0147  * @name: the device tree binding name of the property
0148  * @bprop: indicate that it is a boolean property
0149  * @mprop: indicate that it is a mandatory property
0150  * @reg_type: the register that have to be modified
0151  * @reg_mask: the bit that have to be modified in the selected register
0152  *            in case of it is a boolean property
0153  * @reset_val: the default value that have to be set in case the property
0154  *             has not been defined in the device tree
0155  * @check: this callback ckecks that the property is compliant with the
0156  *         transaction type selected
0157  * @calculate: this callback is called to calculate for exemple a timing
0158  *             set in nanoseconds in the device tree in clock cycles or in
0159  *             clock period
0160  * @set: this callback applies the values in the registers
0161  */
0162 struct stm32_fmc2_prop {
0163     const char *name;
0164     bool bprop;
0165     bool mprop;
0166     int reg_type;
0167     u32 reg_mask;
0168     u32 reset_val;
0169     int (*check)(struct stm32_fmc2_ebi *ebi,
0170              const struct stm32_fmc2_prop *prop, int cs);
0171     u32 (*calculate)(struct stm32_fmc2_ebi *ebi, int cs, u32 setup);
0172     int (*set)(struct stm32_fmc2_ebi *ebi,
0173            const struct stm32_fmc2_prop *prop,
0174            int cs, u32 setup);
0175 };
0176 
0177 static int stm32_fmc2_ebi_check_mux(struct stm32_fmc2_ebi *ebi,
0178                     const struct stm32_fmc2_prop *prop,
0179                     int cs)
0180 {
0181     u32 bcr;
0182 
0183     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0184 
0185     if (bcr & FMC2_BCR_MTYP)
0186         return 0;
0187 
0188     return -EINVAL;
0189 }
0190 
0191 static int stm32_fmc2_ebi_check_waitcfg(struct stm32_fmc2_ebi *ebi,
0192                     const struct stm32_fmc2_prop *prop,
0193                     int cs)
0194 {
0195     u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0196 
0197     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0198 
0199     if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
0200         return 0;
0201 
0202     return -EINVAL;
0203 }
0204 
0205 static int stm32_fmc2_ebi_check_sync_trans(struct stm32_fmc2_ebi *ebi,
0206                        const struct stm32_fmc2_prop *prop,
0207                        int cs)
0208 {
0209     u32 bcr;
0210 
0211     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0212 
0213     if (bcr & FMC2_BCR_BURSTEN)
0214         return 0;
0215 
0216     return -EINVAL;
0217 }
0218 
0219 static int stm32_fmc2_ebi_check_async_trans(struct stm32_fmc2_ebi *ebi,
0220                         const struct stm32_fmc2_prop *prop,
0221                         int cs)
0222 {
0223     u32 bcr;
0224 
0225     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0226 
0227     if (!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW))
0228         return 0;
0229 
0230     return -EINVAL;
0231 }
0232 
0233 static int stm32_fmc2_ebi_check_cpsize(struct stm32_fmc2_ebi *ebi,
0234                        const struct stm32_fmc2_prop *prop,
0235                        int cs)
0236 {
0237     u32 bcr, val = FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
0238 
0239     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0240 
0241     if ((bcr & FMC2_BCR_MTYP) == val && bcr & FMC2_BCR_BURSTEN)
0242         return 0;
0243 
0244     return -EINVAL;
0245 }
0246 
0247 static int stm32_fmc2_ebi_check_address_hold(struct stm32_fmc2_ebi *ebi,
0248                          const struct stm32_fmc2_prop *prop,
0249                          int cs)
0250 {
0251     u32 bcr, bxtr, val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
0252 
0253     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0254     if (prop->reg_type == FMC2_REG_BWTR)
0255         regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
0256     else
0257         regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
0258 
0259     if ((!(bcr & FMC2_BCR_BURSTEN) || !(bcr & FMC2_BCR_CBURSTRW)) &&
0260         ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN))
0261         return 0;
0262 
0263     return -EINVAL;
0264 }
0265 
0266 static int stm32_fmc2_ebi_check_clk_period(struct stm32_fmc2_ebi *ebi,
0267                        const struct stm32_fmc2_prop *prop,
0268                        int cs)
0269 {
0270     u32 bcr, bcr1;
0271 
0272     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0273     if (cs)
0274         regmap_read(ebi->regmap, FMC2_BCR1, &bcr1);
0275     else
0276         bcr1 = bcr;
0277 
0278     if (bcr & FMC2_BCR_BURSTEN && (!cs || !(bcr1 & FMC2_BCR1_CCLKEN)))
0279         return 0;
0280 
0281     return -EINVAL;
0282 }
0283 
0284 static int stm32_fmc2_ebi_check_cclk(struct stm32_fmc2_ebi *ebi,
0285                      const struct stm32_fmc2_prop *prop,
0286                      int cs)
0287 {
0288     if (cs)
0289         return -EINVAL;
0290 
0291     return stm32_fmc2_ebi_check_sync_trans(ebi, prop, cs);
0292 }
0293 
0294 static u32 stm32_fmc2_ebi_ns_to_clock_cycles(struct stm32_fmc2_ebi *ebi,
0295                          int cs, u32 setup)
0296 {
0297     unsigned long hclk = clk_get_rate(ebi->clk);
0298     unsigned long hclkp = NSEC_PER_SEC / (hclk / 1000);
0299 
0300     return DIV_ROUND_UP(setup * 1000, hclkp);
0301 }
0302 
0303 static u32 stm32_fmc2_ebi_ns_to_clk_period(struct stm32_fmc2_ebi *ebi,
0304                        int cs, u32 setup)
0305 {
0306     u32 nb_clk_cycles = stm32_fmc2_ebi_ns_to_clock_cycles(ebi, cs, setup);
0307     u32 bcr, btr, clk_period;
0308 
0309     regmap_read(ebi->regmap, FMC2_BCR1, &bcr);
0310     if (bcr & FMC2_BCR1_CCLKEN || !cs)
0311         regmap_read(ebi->regmap, FMC2_BTR1, &btr);
0312     else
0313         regmap_read(ebi->regmap, FMC2_BTR(cs), &btr);
0314 
0315     clk_period = FIELD_GET(FMC2_BTR_CLKDIV, btr) + 1;
0316 
0317     return DIV_ROUND_UP(nb_clk_cycles, clk_period);
0318 }
0319 
0320 static int stm32_fmc2_ebi_get_reg(int reg_type, int cs, u32 *reg)
0321 {
0322     switch (reg_type) {
0323     case FMC2_REG_BCR:
0324         *reg = FMC2_BCR(cs);
0325         break;
0326     case FMC2_REG_BTR:
0327         *reg = FMC2_BTR(cs);
0328         break;
0329     case FMC2_REG_BWTR:
0330         *reg = FMC2_BWTR(cs);
0331         break;
0332     case FMC2_REG_PCSCNTR:
0333         *reg = FMC2_PCSCNTR;
0334         break;
0335     default:
0336         return -EINVAL;
0337     }
0338 
0339     return 0;
0340 }
0341 
0342 static int stm32_fmc2_ebi_set_bit_field(struct stm32_fmc2_ebi *ebi,
0343                     const struct stm32_fmc2_prop *prop,
0344                     int cs, u32 setup)
0345 {
0346     u32 reg;
0347     int ret;
0348 
0349     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0350     if (ret)
0351         return ret;
0352 
0353     regmap_update_bits(ebi->regmap, reg, prop->reg_mask,
0354                setup ? prop->reg_mask : 0);
0355 
0356     return 0;
0357 }
0358 
0359 static int stm32_fmc2_ebi_set_trans_type(struct stm32_fmc2_ebi *ebi,
0360                      const struct stm32_fmc2_prop *prop,
0361                      int cs, u32 setup)
0362 {
0363     u32 bcr_mask, bcr = FMC2_BCR_WREN;
0364     u32 btr_mask, btr = 0;
0365     u32 bwtr_mask, bwtr = 0;
0366 
0367     bwtr_mask = FMC2_BXTR_ACCMOD;
0368     btr_mask = FMC2_BXTR_ACCMOD;
0369     bcr_mask = FMC2_BCR_MUXEN | FMC2_BCR_MTYP | FMC2_BCR_FACCEN |
0370            FMC2_BCR_WREN | FMC2_BCR_WAITEN | FMC2_BCR_BURSTEN |
0371            FMC2_BCR_EXTMOD | FMC2_BCR_CBURSTRW;
0372 
0373     switch (setup) {
0374     case FMC2_ASYNC_MODE_1_SRAM:
0375         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
0376         /*
0377          * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
0378          * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
0379          */
0380         break;
0381     case FMC2_ASYNC_MODE_1_PSRAM:
0382         /*
0383          * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
0384          * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
0385          */
0386         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
0387         break;
0388     case FMC2_ASYNC_MODE_A_SRAM:
0389         /*
0390          * MUXEN = 0, MTYP = 0, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
0391          * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
0392          */
0393         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_SRAM);
0394         bcr |= FMC2_BCR_EXTMOD;
0395         btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
0396         bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
0397         break;
0398     case FMC2_ASYNC_MODE_A_PSRAM:
0399         /*
0400          * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 0, WAITEN = 0,
0401          * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 0
0402          */
0403         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
0404         bcr |= FMC2_BCR_EXTMOD;
0405         btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
0406         bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_A);
0407         break;
0408     case FMC2_ASYNC_MODE_2_NOR:
0409         /*
0410          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
0411          * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
0412          */
0413         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0414         bcr |= FMC2_BCR_FACCEN;
0415         break;
0416     case FMC2_ASYNC_MODE_B_NOR:
0417         /*
0418          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
0419          * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 1
0420          */
0421         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0422         bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
0423         btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
0424         bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_B);
0425         break;
0426     case FMC2_ASYNC_MODE_C_NOR:
0427         /*
0428          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
0429          * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 2
0430          */
0431         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0432         bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
0433         btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
0434         bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_C);
0435         break;
0436     case FMC2_ASYNC_MODE_D_NOR:
0437         /*
0438          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 0, WAITEN = 0,
0439          * WREN = 1, EXTMOD = 1, CBURSTRW = 0, ACCMOD = 3
0440          */
0441         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0442         bcr |= FMC2_BCR_FACCEN | FMC2_BCR_EXTMOD;
0443         btr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
0444         bwtr |= FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
0445         break;
0446     case FMC2_SYNC_READ_SYNC_WRITE_PSRAM:
0447         /*
0448          * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
0449          * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
0450          */
0451         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
0452         bcr |= FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
0453         break;
0454     case FMC2_SYNC_READ_ASYNC_WRITE_PSRAM:
0455         /*
0456          * MUXEN = 0, MTYP = 1, FACCEN = 0, BURSTEN = 1, WAITEN = 0,
0457          * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
0458          */
0459         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_PSRAM);
0460         bcr |= FMC2_BCR_BURSTEN;
0461         break;
0462     case FMC2_SYNC_READ_SYNC_WRITE_NOR:
0463         /*
0464          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
0465          * WREN = 1, EXTMOD = 0, CBURSTRW = 1, ACCMOD = 0
0466          */
0467         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0468         bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN | FMC2_BCR_CBURSTRW;
0469         break;
0470     case FMC2_SYNC_READ_ASYNC_WRITE_NOR:
0471         /*
0472          * MUXEN = 0, MTYP = 2, FACCEN = 1, BURSTEN = 1, WAITEN = 0,
0473          * WREN = 1, EXTMOD = 0, CBURSTRW = 0, ACCMOD = 0
0474          */
0475         bcr |= FIELD_PREP(FMC2_BCR_MTYP, FMC2_BCR_MTYP_NOR);
0476         bcr |= FMC2_BCR_FACCEN | FMC2_BCR_BURSTEN;
0477         break;
0478     default:
0479         /* Type of transaction not supported */
0480         return -EINVAL;
0481     }
0482 
0483     if (bcr & FMC2_BCR_EXTMOD)
0484         regmap_update_bits(ebi->regmap, FMC2_BWTR(cs),
0485                    bwtr_mask, bwtr);
0486     regmap_update_bits(ebi->regmap, FMC2_BTR(cs), btr_mask, btr);
0487     regmap_update_bits(ebi->regmap, FMC2_BCR(cs), bcr_mask, bcr);
0488 
0489     return 0;
0490 }
0491 
0492 static int stm32_fmc2_ebi_set_buswidth(struct stm32_fmc2_ebi *ebi,
0493                        const struct stm32_fmc2_prop *prop,
0494                        int cs, u32 setup)
0495 {
0496     u32 val;
0497 
0498     switch (setup) {
0499     case FMC2_BUSWIDTH_8:
0500         val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_8);
0501         break;
0502     case FMC2_BUSWIDTH_16:
0503         val = FIELD_PREP(FMC2_BCR_MWID, FMC2_BCR_MWID_16);
0504         break;
0505     default:
0506         /* Buswidth not supported */
0507         return -EINVAL;
0508     }
0509 
0510     regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MWID, val);
0511 
0512     return 0;
0513 }
0514 
0515 static int stm32_fmc2_ebi_set_cpsize(struct stm32_fmc2_ebi *ebi,
0516                      const struct stm32_fmc2_prop *prop,
0517                      int cs, u32 setup)
0518 {
0519     u32 val;
0520 
0521     switch (setup) {
0522     case FMC2_CPSIZE_0:
0523         val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_0);
0524         break;
0525     case FMC2_CPSIZE_128:
0526         val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_128);
0527         break;
0528     case FMC2_CPSIZE_256:
0529         val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_256);
0530         break;
0531     case FMC2_CPSIZE_512:
0532         val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_512);
0533         break;
0534     case FMC2_CPSIZE_1024:
0535         val = FIELD_PREP(FMC2_BCR_CPSIZE, FMC2_BCR_CPSIZE_1024);
0536         break;
0537     default:
0538         /* Cpsize not supported */
0539         return -EINVAL;
0540     }
0541 
0542     regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_CPSIZE, val);
0543 
0544     return 0;
0545 }
0546 
0547 static int stm32_fmc2_ebi_set_bl_setup(struct stm32_fmc2_ebi *ebi,
0548                        const struct stm32_fmc2_prop *prop,
0549                        int cs, u32 setup)
0550 {
0551     u32 val;
0552 
0553     val = min_t(u32, setup, FMC2_BCR_NBLSET_MAX);
0554     val = FIELD_PREP(FMC2_BCR_NBLSET, val);
0555     regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_NBLSET, val);
0556 
0557     return 0;
0558 }
0559 
0560 static int stm32_fmc2_ebi_set_address_setup(struct stm32_fmc2_ebi *ebi,
0561                         const struct stm32_fmc2_prop *prop,
0562                         int cs, u32 setup)
0563 {
0564     u32 bcr, bxtr, reg;
0565     u32 val = FIELD_PREP(FMC2_BXTR_ACCMOD, FMC2_BXTR_EXTMOD_D);
0566     int ret;
0567 
0568     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0569     if (ret)
0570         return ret;
0571 
0572     regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0573     if (prop->reg_type == FMC2_REG_BWTR)
0574         regmap_read(ebi->regmap, FMC2_BWTR(cs), &bxtr);
0575     else
0576         regmap_read(ebi->regmap, FMC2_BTR(cs), &bxtr);
0577 
0578     if ((bxtr & FMC2_BXTR_ACCMOD) == val || bcr & FMC2_BCR_MUXEN)
0579         val = clamp_val(setup, 1, FMC2_BXTR_ADDSET_MAX);
0580     else
0581         val = min_t(u32, setup, FMC2_BXTR_ADDSET_MAX);
0582     val = FIELD_PREP(FMC2_BXTR_ADDSET, val);
0583     regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDSET, val);
0584 
0585     return 0;
0586 }
0587 
0588 static int stm32_fmc2_ebi_set_address_hold(struct stm32_fmc2_ebi *ebi,
0589                        const struct stm32_fmc2_prop *prop,
0590                        int cs, u32 setup)
0591 {
0592     u32 val, reg;
0593     int ret;
0594 
0595     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0596     if (ret)
0597         return ret;
0598 
0599     val = clamp_val(setup, 1, FMC2_BXTR_ADDHLD_MAX);
0600     val = FIELD_PREP(FMC2_BXTR_ADDHLD, val);
0601     regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_ADDHLD, val);
0602 
0603     return 0;
0604 }
0605 
0606 static int stm32_fmc2_ebi_set_data_setup(struct stm32_fmc2_ebi *ebi,
0607                      const struct stm32_fmc2_prop *prop,
0608                      int cs, u32 setup)
0609 {
0610     u32 val, reg;
0611     int ret;
0612 
0613     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0614     if (ret)
0615         return ret;
0616 
0617     val = clamp_val(setup, 1, FMC2_BXTR_DATAST_MAX);
0618     val = FIELD_PREP(FMC2_BXTR_DATAST, val);
0619     regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAST, val);
0620 
0621     return 0;
0622 }
0623 
0624 static int stm32_fmc2_ebi_set_bus_turnaround(struct stm32_fmc2_ebi *ebi,
0625                          const struct stm32_fmc2_prop *prop,
0626                          int cs, u32 setup)
0627 {
0628     u32 val, reg;
0629     int ret;
0630 
0631     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0632     if (ret)
0633         return ret;
0634 
0635     val = setup ? min_t(u32, setup - 1, FMC2_BXTR_BUSTURN_MAX) : 0;
0636     val = FIELD_PREP(FMC2_BXTR_BUSTURN, val);
0637     regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_BUSTURN, val);
0638 
0639     return 0;
0640 }
0641 
0642 static int stm32_fmc2_ebi_set_data_hold(struct stm32_fmc2_ebi *ebi,
0643                     const struct stm32_fmc2_prop *prop,
0644                     int cs, u32 setup)
0645 {
0646     u32 val, reg;
0647     int ret;
0648 
0649     ret = stm32_fmc2_ebi_get_reg(prop->reg_type, cs, &reg);
0650     if (ret)
0651         return ret;
0652 
0653     if (prop->reg_type == FMC2_REG_BWTR)
0654         val = setup ? min_t(u32, setup - 1, FMC2_BXTR_DATAHLD_MAX) : 0;
0655     else
0656         val = min_t(u32, setup, FMC2_BXTR_DATAHLD_MAX);
0657     val = FIELD_PREP(FMC2_BXTR_DATAHLD, val);
0658     regmap_update_bits(ebi->regmap, reg, FMC2_BXTR_DATAHLD, val);
0659 
0660     return 0;
0661 }
0662 
0663 static int stm32_fmc2_ebi_set_clk_period(struct stm32_fmc2_ebi *ebi,
0664                      const struct stm32_fmc2_prop *prop,
0665                      int cs, u32 setup)
0666 {
0667     u32 val;
0668 
0669     val = setup ? clamp_val(setup - 1, 1, FMC2_BTR_CLKDIV_MAX) : 1;
0670     val = FIELD_PREP(FMC2_BTR_CLKDIV, val);
0671     regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_CLKDIV, val);
0672 
0673     return 0;
0674 }
0675 
0676 static int stm32_fmc2_ebi_set_data_latency(struct stm32_fmc2_ebi *ebi,
0677                        const struct stm32_fmc2_prop *prop,
0678                        int cs, u32 setup)
0679 {
0680     u32 val;
0681 
0682     val = setup > 1 ? min_t(u32, setup - 2, FMC2_BTR_DATLAT_MAX) : 0;
0683     val = FIELD_PREP(FMC2_BTR_DATLAT, val);
0684     regmap_update_bits(ebi->regmap, FMC2_BTR(cs), FMC2_BTR_DATLAT, val);
0685 
0686     return 0;
0687 }
0688 
0689 static int stm32_fmc2_ebi_set_max_low_pulse(struct stm32_fmc2_ebi *ebi,
0690                         const struct stm32_fmc2_prop *prop,
0691                         int cs, u32 setup)
0692 {
0693     u32 old_val, new_val, pcscntr;
0694 
0695     if (setup < 1)
0696         return 0;
0697 
0698     regmap_read(ebi->regmap, FMC2_PCSCNTR, &pcscntr);
0699 
0700     /* Enable counter for the bank */
0701     regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
0702                FMC2_PCSCNTR_CNTBEN(cs),
0703                FMC2_PCSCNTR_CNTBEN(cs));
0704 
0705     new_val = min_t(u32, setup - 1, FMC2_PCSCNTR_CSCOUNT_MAX);
0706     old_val = FIELD_GET(FMC2_PCSCNTR_CSCOUNT, pcscntr);
0707     if (old_val && new_val > old_val)
0708         /* Keep current counter value */
0709         return 0;
0710 
0711     new_val = FIELD_PREP(FMC2_PCSCNTR_CSCOUNT, new_val);
0712     regmap_update_bits(ebi->regmap, FMC2_PCSCNTR,
0713                FMC2_PCSCNTR_CSCOUNT, new_val);
0714 
0715     return 0;
0716 }
0717 
0718 static const struct stm32_fmc2_prop stm32_fmc2_child_props[] = {
0719     /* st,fmc2-ebi-cs-trans-type must be the first property */
0720     {
0721         .name = "st,fmc2-ebi-cs-transaction-type",
0722         .mprop = true,
0723         .set = stm32_fmc2_ebi_set_trans_type,
0724     },
0725     {
0726         .name = "st,fmc2-ebi-cs-cclk-enable",
0727         .bprop = true,
0728         .reg_type = FMC2_REG_BCR,
0729         .reg_mask = FMC2_BCR1_CCLKEN,
0730         .check = stm32_fmc2_ebi_check_cclk,
0731         .set = stm32_fmc2_ebi_set_bit_field,
0732     },
0733     {
0734         .name = "st,fmc2-ebi-cs-mux-enable",
0735         .bprop = true,
0736         .reg_type = FMC2_REG_BCR,
0737         .reg_mask = FMC2_BCR_MUXEN,
0738         .check = stm32_fmc2_ebi_check_mux,
0739         .set = stm32_fmc2_ebi_set_bit_field,
0740     },
0741     {
0742         .name = "st,fmc2-ebi-cs-buswidth",
0743         .reset_val = FMC2_BUSWIDTH_16,
0744         .set = stm32_fmc2_ebi_set_buswidth,
0745     },
0746     {
0747         .name = "st,fmc2-ebi-cs-waitpol-high",
0748         .bprop = true,
0749         .reg_type = FMC2_REG_BCR,
0750         .reg_mask = FMC2_BCR_WAITPOL,
0751         .set = stm32_fmc2_ebi_set_bit_field,
0752     },
0753     {
0754         .name = "st,fmc2-ebi-cs-waitcfg-enable",
0755         .bprop = true,
0756         .reg_type = FMC2_REG_BCR,
0757         .reg_mask = FMC2_BCR_WAITCFG,
0758         .check = stm32_fmc2_ebi_check_waitcfg,
0759         .set = stm32_fmc2_ebi_set_bit_field,
0760     },
0761     {
0762         .name = "st,fmc2-ebi-cs-wait-enable",
0763         .bprop = true,
0764         .reg_type = FMC2_REG_BCR,
0765         .reg_mask = FMC2_BCR_WAITEN,
0766         .check = stm32_fmc2_ebi_check_sync_trans,
0767         .set = stm32_fmc2_ebi_set_bit_field,
0768     },
0769     {
0770         .name = "st,fmc2-ebi-cs-asyncwait-enable",
0771         .bprop = true,
0772         .reg_type = FMC2_REG_BCR,
0773         .reg_mask = FMC2_BCR_ASYNCWAIT,
0774         .check = stm32_fmc2_ebi_check_async_trans,
0775         .set = stm32_fmc2_ebi_set_bit_field,
0776     },
0777     {
0778         .name = "st,fmc2-ebi-cs-cpsize",
0779         .check = stm32_fmc2_ebi_check_cpsize,
0780         .set = stm32_fmc2_ebi_set_cpsize,
0781     },
0782     {
0783         .name = "st,fmc2-ebi-cs-byte-lane-setup-ns",
0784         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0785         .set = stm32_fmc2_ebi_set_bl_setup,
0786     },
0787     {
0788         .name = "st,fmc2-ebi-cs-address-setup-ns",
0789         .reg_type = FMC2_REG_BTR,
0790         .reset_val = FMC2_BXTR_ADDSET_MAX,
0791         .check = stm32_fmc2_ebi_check_async_trans,
0792         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0793         .set = stm32_fmc2_ebi_set_address_setup,
0794     },
0795     {
0796         .name = "st,fmc2-ebi-cs-address-hold-ns",
0797         .reg_type = FMC2_REG_BTR,
0798         .reset_val = FMC2_BXTR_ADDHLD_MAX,
0799         .check = stm32_fmc2_ebi_check_address_hold,
0800         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0801         .set = stm32_fmc2_ebi_set_address_hold,
0802     },
0803     {
0804         .name = "st,fmc2-ebi-cs-data-setup-ns",
0805         .reg_type = FMC2_REG_BTR,
0806         .reset_val = FMC2_BXTR_DATAST_MAX,
0807         .check = stm32_fmc2_ebi_check_async_trans,
0808         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0809         .set = stm32_fmc2_ebi_set_data_setup,
0810     },
0811     {
0812         .name = "st,fmc2-ebi-cs-bus-turnaround-ns",
0813         .reg_type = FMC2_REG_BTR,
0814         .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
0815         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0816         .set = stm32_fmc2_ebi_set_bus_turnaround,
0817     },
0818     {
0819         .name = "st,fmc2-ebi-cs-data-hold-ns",
0820         .reg_type = FMC2_REG_BTR,
0821         .check = stm32_fmc2_ebi_check_async_trans,
0822         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0823         .set = stm32_fmc2_ebi_set_data_hold,
0824     },
0825     {
0826         .name = "st,fmc2-ebi-cs-clk-period-ns",
0827         .reset_val = FMC2_BTR_CLKDIV_MAX + 1,
0828         .check = stm32_fmc2_ebi_check_clk_period,
0829         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0830         .set = stm32_fmc2_ebi_set_clk_period,
0831     },
0832     {
0833         .name = "st,fmc2-ebi-cs-data-latency-ns",
0834         .check = stm32_fmc2_ebi_check_sync_trans,
0835         .calculate = stm32_fmc2_ebi_ns_to_clk_period,
0836         .set = stm32_fmc2_ebi_set_data_latency,
0837     },
0838     {
0839         .name = "st,fmc2-ebi-cs-write-address-setup-ns",
0840         .reg_type = FMC2_REG_BWTR,
0841         .reset_val = FMC2_BXTR_ADDSET_MAX,
0842         .check = stm32_fmc2_ebi_check_async_trans,
0843         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0844         .set = stm32_fmc2_ebi_set_address_setup,
0845     },
0846     {
0847         .name = "st,fmc2-ebi-cs-write-address-hold-ns",
0848         .reg_type = FMC2_REG_BWTR,
0849         .reset_val = FMC2_BXTR_ADDHLD_MAX,
0850         .check = stm32_fmc2_ebi_check_address_hold,
0851         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0852         .set = stm32_fmc2_ebi_set_address_hold,
0853     },
0854     {
0855         .name = "st,fmc2-ebi-cs-write-data-setup-ns",
0856         .reg_type = FMC2_REG_BWTR,
0857         .reset_val = FMC2_BXTR_DATAST_MAX,
0858         .check = stm32_fmc2_ebi_check_async_trans,
0859         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0860         .set = stm32_fmc2_ebi_set_data_setup,
0861     },
0862     {
0863         .name = "st,fmc2-ebi-cs-write-bus-turnaround-ns",
0864         .reg_type = FMC2_REG_BWTR,
0865         .reset_val = FMC2_BXTR_BUSTURN_MAX + 1,
0866         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0867         .set = stm32_fmc2_ebi_set_bus_turnaround,
0868     },
0869     {
0870         .name = "st,fmc2-ebi-cs-write-data-hold-ns",
0871         .reg_type = FMC2_REG_BWTR,
0872         .check = stm32_fmc2_ebi_check_async_trans,
0873         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0874         .set = stm32_fmc2_ebi_set_data_hold,
0875     },
0876     {
0877         .name = "st,fmc2-ebi-cs-max-low-pulse-ns",
0878         .calculate = stm32_fmc2_ebi_ns_to_clock_cycles,
0879         .set = stm32_fmc2_ebi_set_max_low_pulse,
0880     },
0881 };
0882 
0883 static int stm32_fmc2_ebi_parse_prop(struct stm32_fmc2_ebi *ebi,
0884                      struct device_node *dev_node,
0885                      const struct stm32_fmc2_prop *prop,
0886                      int cs)
0887 {
0888     struct device *dev = ebi->dev;
0889     u32 setup = 0;
0890 
0891     if (!prop->set) {
0892         dev_err(dev, "property %s is not well defined\n", prop->name);
0893         return -EINVAL;
0894     }
0895 
0896     if (prop->check && prop->check(ebi, prop, cs))
0897         /* Skeep this property */
0898         return 0;
0899 
0900     if (prop->bprop) {
0901         bool bprop;
0902 
0903         bprop = of_property_read_bool(dev_node, prop->name);
0904         if (prop->mprop && !bprop) {
0905             dev_err(dev, "mandatory property %s not defined in the device tree\n",
0906                 prop->name);
0907             return -EINVAL;
0908         }
0909 
0910         if (bprop)
0911             setup = 1;
0912     } else {
0913         u32 val;
0914         int ret;
0915 
0916         ret = of_property_read_u32(dev_node, prop->name, &val);
0917         if (prop->mprop && ret) {
0918             dev_err(dev, "mandatory property %s not defined in the device tree\n",
0919                 prop->name);
0920             return ret;
0921         }
0922 
0923         if (ret)
0924             setup = prop->reset_val;
0925         else if (prop->calculate)
0926             setup = prop->calculate(ebi, cs, val);
0927         else
0928             setup = val;
0929     }
0930 
0931     return prop->set(ebi, prop, cs, setup);
0932 }
0933 
0934 static void stm32_fmc2_ebi_enable_bank(struct stm32_fmc2_ebi *ebi, int cs)
0935 {
0936     regmap_update_bits(ebi->regmap, FMC2_BCR(cs),
0937                FMC2_BCR_MBKEN, FMC2_BCR_MBKEN);
0938 }
0939 
0940 static void stm32_fmc2_ebi_disable_bank(struct stm32_fmc2_ebi *ebi, int cs)
0941 {
0942     regmap_update_bits(ebi->regmap, FMC2_BCR(cs), FMC2_BCR_MBKEN, 0);
0943 }
0944 
0945 static void stm32_fmc2_ebi_save_setup(struct stm32_fmc2_ebi *ebi)
0946 {
0947     unsigned int cs;
0948 
0949     for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
0950         regmap_read(ebi->regmap, FMC2_BCR(cs), &ebi->bcr[cs]);
0951         regmap_read(ebi->regmap, FMC2_BTR(cs), &ebi->btr[cs]);
0952         regmap_read(ebi->regmap, FMC2_BWTR(cs), &ebi->bwtr[cs]);
0953     }
0954 
0955     regmap_read(ebi->regmap, FMC2_PCSCNTR, &ebi->pcscntr);
0956 }
0957 
0958 static void stm32_fmc2_ebi_set_setup(struct stm32_fmc2_ebi *ebi)
0959 {
0960     unsigned int cs;
0961 
0962     for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
0963         regmap_write(ebi->regmap, FMC2_BCR(cs), ebi->bcr[cs]);
0964         regmap_write(ebi->regmap, FMC2_BTR(cs), ebi->btr[cs]);
0965         regmap_write(ebi->regmap, FMC2_BWTR(cs), ebi->bwtr[cs]);
0966     }
0967 
0968     regmap_write(ebi->regmap, FMC2_PCSCNTR, ebi->pcscntr);
0969 }
0970 
0971 static void stm32_fmc2_ebi_disable_banks(struct stm32_fmc2_ebi *ebi)
0972 {
0973     unsigned int cs;
0974 
0975     for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
0976         if (!(ebi->bank_assigned & BIT(cs)))
0977             continue;
0978 
0979         stm32_fmc2_ebi_disable_bank(ebi, cs);
0980     }
0981 }
0982 
0983 /* NWAIT signal can not be connected to EBI controller and NAND controller */
0984 static bool stm32_fmc2_ebi_nwait_used_by_ctrls(struct stm32_fmc2_ebi *ebi)
0985 {
0986     unsigned int cs;
0987     u32 bcr;
0988 
0989     for (cs = 0; cs < FMC2_MAX_EBI_CE; cs++) {
0990         if (!(ebi->bank_assigned & BIT(cs)))
0991             continue;
0992 
0993         regmap_read(ebi->regmap, FMC2_BCR(cs), &bcr);
0994         if ((bcr & FMC2_BCR_WAITEN || bcr & FMC2_BCR_ASYNCWAIT) &&
0995             ebi->bank_assigned & BIT(FMC2_NAND))
0996             return true;
0997     }
0998 
0999     return false;
1000 }
1001 
1002 static void stm32_fmc2_ebi_enable(struct stm32_fmc2_ebi *ebi)
1003 {
1004     regmap_update_bits(ebi->regmap, FMC2_BCR1,
1005                FMC2_BCR1_FMC2EN, FMC2_BCR1_FMC2EN);
1006 }
1007 
1008 static void stm32_fmc2_ebi_disable(struct stm32_fmc2_ebi *ebi)
1009 {
1010     regmap_update_bits(ebi->regmap, FMC2_BCR1, FMC2_BCR1_FMC2EN, 0);
1011 }
1012 
1013 static int stm32_fmc2_ebi_setup_cs(struct stm32_fmc2_ebi *ebi,
1014                    struct device_node *dev_node,
1015                    u32 cs)
1016 {
1017     unsigned int i;
1018     int ret;
1019 
1020     stm32_fmc2_ebi_disable_bank(ebi, cs);
1021 
1022     for (i = 0; i < ARRAY_SIZE(stm32_fmc2_child_props); i++) {
1023         const struct stm32_fmc2_prop *p = &stm32_fmc2_child_props[i];
1024 
1025         ret = stm32_fmc2_ebi_parse_prop(ebi, dev_node, p, cs);
1026         if (ret) {
1027             dev_err(ebi->dev, "property %s could not be set: %d\n",
1028                 p->name, ret);
1029             return ret;
1030         }
1031     }
1032 
1033     stm32_fmc2_ebi_enable_bank(ebi, cs);
1034 
1035     return 0;
1036 }
1037 
1038 static int stm32_fmc2_ebi_parse_dt(struct stm32_fmc2_ebi *ebi)
1039 {
1040     struct device *dev = ebi->dev;
1041     struct device_node *child;
1042     bool child_found = false;
1043     u32 bank;
1044     int ret;
1045 
1046     for_each_available_child_of_node(dev->of_node, child) {
1047         ret = of_property_read_u32(child, "reg", &bank);
1048         if (ret) {
1049             dev_err(dev, "could not retrieve reg property: %d\n",
1050                 ret);
1051             of_node_put(child);
1052             return ret;
1053         }
1054 
1055         if (bank >= FMC2_MAX_BANKS) {
1056             dev_err(dev, "invalid reg value: %d\n", bank);
1057             of_node_put(child);
1058             return -EINVAL;
1059         }
1060 
1061         if (ebi->bank_assigned & BIT(bank)) {
1062             dev_err(dev, "bank already assigned: %d\n", bank);
1063             of_node_put(child);
1064             return -EINVAL;
1065         }
1066 
1067         if (bank < FMC2_MAX_EBI_CE) {
1068             ret = stm32_fmc2_ebi_setup_cs(ebi, child, bank);
1069             if (ret) {
1070                 dev_err(dev, "setup chip select %d failed: %d\n",
1071                     bank, ret);
1072                 of_node_put(child);
1073                 return ret;
1074             }
1075         }
1076 
1077         ebi->bank_assigned |= BIT(bank);
1078         child_found = true;
1079     }
1080 
1081     if (!child_found) {
1082         dev_warn(dev, "no subnodes found, disable the driver.\n");
1083         return -ENODEV;
1084     }
1085 
1086     if (stm32_fmc2_ebi_nwait_used_by_ctrls(ebi)) {
1087         dev_err(dev, "NWAIT signal connected to EBI and NAND controllers\n");
1088         return -EINVAL;
1089     }
1090 
1091     stm32_fmc2_ebi_enable(ebi);
1092 
1093     return of_platform_populate(dev->of_node, NULL, NULL, dev);
1094 }
1095 
1096 static int stm32_fmc2_ebi_probe(struct platform_device *pdev)
1097 {
1098     struct device *dev = &pdev->dev;
1099     struct stm32_fmc2_ebi *ebi;
1100     struct reset_control *rstc;
1101     int ret;
1102 
1103     ebi = devm_kzalloc(&pdev->dev, sizeof(*ebi), GFP_KERNEL);
1104     if (!ebi)
1105         return -ENOMEM;
1106 
1107     ebi->dev = dev;
1108 
1109     ebi->regmap = device_node_to_regmap(dev->of_node);
1110     if (IS_ERR(ebi->regmap))
1111         return PTR_ERR(ebi->regmap);
1112 
1113     ebi->clk = devm_clk_get(dev, NULL);
1114     if (IS_ERR(ebi->clk))
1115         return PTR_ERR(ebi->clk);
1116 
1117     rstc = devm_reset_control_get(dev, NULL);
1118     if (PTR_ERR(rstc) == -EPROBE_DEFER)
1119         return -EPROBE_DEFER;
1120 
1121     ret = clk_prepare_enable(ebi->clk);
1122     if (ret)
1123         return ret;
1124 
1125     if (!IS_ERR(rstc)) {
1126         reset_control_assert(rstc);
1127         reset_control_deassert(rstc);
1128     }
1129 
1130     ret = stm32_fmc2_ebi_parse_dt(ebi);
1131     if (ret)
1132         goto err_release;
1133 
1134     stm32_fmc2_ebi_save_setup(ebi);
1135     platform_set_drvdata(pdev, ebi);
1136 
1137     return 0;
1138 
1139 err_release:
1140     stm32_fmc2_ebi_disable_banks(ebi);
1141     stm32_fmc2_ebi_disable(ebi);
1142     clk_disable_unprepare(ebi->clk);
1143 
1144     return ret;
1145 }
1146 
1147 static int stm32_fmc2_ebi_remove(struct platform_device *pdev)
1148 {
1149     struct stm32_fmc2_ebi *ebi = platform_get_drvdata(pdev);
1150 
1151     of_platform_depopulate(&pdev->dev);
1152     stm32_fmc2_ebi_disable_banks(ebi);
1153     stm32_fmc2_ebi_disable(ebi);
1154     clk_disable_unprepare(ebi->clk);
1155 
1156     return 0;
1157 }
1158 
1159 static int __maybe_unused stm32_fmc2_ebi_suspend(struct device *dev)
1160 {
1161     struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1162 
1163     stm32_fmc2_ebi_disable(ebi);
1164     clk_disable_unprepare(ebi->clk);
1165     pinctrl_pm_select_sleep_state(dev);
1166 
1167     return 0;
1168 }
1169 
1170 static int __maybe_unused stm32_fmc2_ebi_resume(struct device *dev)
1171 {
1172     struct stm32_fmc2_ebi *ebi = dev_get_drvdata(dev);
1173     int ret;
1174 
1175     pinctrl_pm_select_default_state(dev);
1176 
1177     ret = clk_prepare_enable(ebi->clk);
1178     if (ret)
1179         return ret;
1180 
1181     stm32_fmc2_ebi_set_setup(ebi);
1182     stm32_fmc2_ebi_enable(ebi);
1183 
1184     return 0;
1185 }
1186 
1187 static SIMPLE_DEV_PM_OPS(stm32_fmc2_ebi_pm_ops, stm32_fmc2_ebi_suspend,
1188              stm32_fmc2_ebi_resume);
1189 
1190 static const struct of_device_id stm32_fmc2_ebi_match[] = {
1191     {.compatible = "st,stm32mp1-fmc2-ebi"},
1192     {}
1193 };
1194 MODULE_DEVICE_TABLE(of, stm32_fmc2_ebi_match);
1195 
1196 static struct platform_driver stm32_fmc2_ebi_driver = {
1197     .probe  = stm32_fmc2_ebi_probe,
1198     .remove = stm32_fmc2_ebi_remove,
1199     .driver = {
1200         .name = "stm32_fmc2_ebi",
1201         .of_match_table = stm32_fmc2_ebi_match,
1202         .pm = &stm32_fmc2_ebi_pm_ops,
1203     },
1204 };
1205 module_platform_driver(stm32_fmc2_ebi_driver);
1206 
1207 MODULE_ALIAS("platform:stm32_fmc2_ebi");
1208 MODULE_AUTHOR("Christophe Kerello <christophe.kerello@st.com>");
1209 MODULE_DESCRIPTION("STMicroelectronics STM32 FMC2 ebi driver");
1210 MODULE_LICENSE("GPL v2");
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