memory/samsung/exynos-srom.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2015 Samsung Electronics Co., Ltd.
0004  *      http://www.samsung.com
0005  *
0006  * Exynos SROMC register definitions
0007  */
0008
0009 #ifndef __EXYNOS_SROM_H
0010 #define __EXYNOS_SROM_H __FILE__
0011
0012 #define EXYNOS_SROMREG(x)       (x)
0013
0014 #define EXYNOS_SROM_BW      EXYNOS_SROMREG(0x0)
0015 #define EXYNOS_SROM_BC0     EXYNOS_SROMREG(0x4)
0016 #define EXYNOS_SROM_BC1     EXYNOS_SROMREG(0x8)
0017 #define EXYNOS_SROM_BC2     EXYNOS_SROMREG(0xc)
0018 #define EXYNOS_SROM_BC3     EXYNOS_SROMREG(0x10)
0019 #define EXYNOS_SROM_BC4     EXYNOS_SROMREG(0x14)
0020 #define EXYNOS_SROM_BC5     EXYNOS_SROMREG(0x18)
0021
0022 /* one register BW holds 4 x 4-bit packed settings for NCS0 - NCS3 */
0023
0024 #define EXYNOS_SROM_BW__DATAWIDTH__SHIFT    0
0025 #define EXYNOS_SROM_BW__ADDRMODE__SHIFT     1
0026 #define EXYNOS_SROM_BW__WAITENABLE__SHIFT   2
0027 #define EXYNOS_SROM_BW__BYTEENABLE__SHIFT   3
0028
0029 #define EXYNOS_SROM_BW__CS_MASK         0xf
0030
0031 #define EXYNOS_SROM_BW__NCS0__SHIFT     0
0032 #define EXYNOS_SROM_BW__NCS1__SHIFT     4
0033 #define EXYNOS_SROM_BW__NCS2__SHIFT     8
0034 #define EXYNOS_SROM_BW__NCS3__SHIFT     12
0035 #define EXYNOS_SROM_BW__NCS4__SHIFT     16
0036 #define EXYNOS_SROM_BW__NCS5__SHIFT     20
0037
0038 /* applies to same to BCS0 - BCS3 */
0039
0040 #define EXYNOS_SROM_BCX__PMC__SHIFT     0
0041 #define EXYNOS_SROM_BCX__TACP__SHIFT        4
0042 #define EXYNOS_SROM_BCX__TCAH__SHIFT        8
0043 #define EXYNOS_SROM_BCX__TCOH__SHIFT        12
0044 #define EXYNOS_SROM_BCX__TACC__SHIFT        16
0045 #define EXYNOS_SROM_BCX__TCOS__SHIFT        24
0046 #define EXYNOS_SROM_BCX__TACS__SHIFT        28
0047
0048 #endif /* __EXYNOS_SROM_H */