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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Renesas RPC-IF core driver
0004  *
0005  * Copyright (C) 2018-2019 Renesas Solutions Corp.
0006  * Copyright (C) 2019 Macronix International Co., Ltd.
0007  * Copyright (C) 2019-2020 Cogent Embedded, Inc.
0008  */
0009 
0010 #include <linux/clk.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/of.h>
0015 #include <linux/of_device.h>
0016 #include <linux/regmap.h>
0017 #include <linux/reset.h>
0018 
0019 #include <memory/renesas-rpc-if.h>
0020 
0021 #define RPCIF_CMNCR     0x0000  /* R/W */
0022 #define RPCIF_CMNCR_MD      BIT(31)
0023 #define RPCIF_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
0024 #define RPCIF_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
0025 #define RPCIF_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
0026 #define RPCIF_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
0027 #define RPCIF_CMNCR_MOIIO(val)  (RPCIF_CMNCR_MOIIO0(val) | RPCIF_CMNCR_MOIIO1(val) | \
0028                  RPCIF_CMNCR_MOIIO2(val) | RPCIF_CMNCR_MOIIO3(val))
0029 #define RPCIF_CMNCR_IO3FV(val)  (((val) & 0x3) << 14) /* documented for RZ/G2L */
0030 #define RPCIF_CMNCR_IO2FV(val)  (((val) & 0x3) << 12) /* documented for RZ/G2L */
0031 #define RPCIF_CMNCR_IO0FV(val)  (((val) & 0x3) << 8)
0032 #define RPCIF_CMNCR_IOFV(val)   (RPCIF_CMNCR_IO0FV(val) | RPCIF_CMNCR_IO2FV(val) | \
0033                  RPCIF_CMNCR_IO3FV(val))
0034 #define RPCIF_CMNCR_BSZ(val)    (((val) & 0x3) << 0)
0035 
0036 #define RPCIF_SSLDR     0x0004  /* R/W */
0037 #define RPCIF_SSLDR_SPNDL(d)    (((d) & 0x7) << 16)
0038 #define RPCIF_SSLDR_SLNDL(d)    (((d) & 0x7) << 8)
0039 #define RPCIF_SSLDR_SCKDL(d)    (((d) & 0x7) << 0)
0040 
0041 #define RPCIF_DRCR      0x000C  /* R/W */
0042 #define RPCIF_DRCR_SSLN     BIT(24)
0043 #define RPCIF_DRCR_RBURST(v)    ((((v) - 1) & 0x1F) << 16)
0044 #define RPCIF_DRCR_RCF      BIT(9)
0045 #define RPCIF_DRCR_RBE      BIT(8)
0046 #define RPCIF_DRCR_SSLE     BIT(0)
0047 
0048 #define RPCIF_DRCMR     0x0010  /* R/W */
0049 #define RPCIF_DRCMR_CMD(c)  (((c) & 0xFF) << 16)
0050 #define RPCIF_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
0051 
0052 #define RPCIF_DREAR     0x0014  /* R/W */
0053 #define RPCIF_DREAR_EAV(c)  (((c) & 0xF) << 16)
0054 #define RPCIF_DREAR_EAC(c)  (((c) & 0x7) << 0)
0055 
0056 #define RPCIF_DROPR     0x0018  /* R/W */
0057 
0058 #define RPCIF_DRENR     0x001C  /* R/W */
0059 #define RPCIF_DRENR_CDB(o)  (u32)((((o) & 0x3) << 30))
0060 #define RPCIF_DRENR_OCDB(o) (((o) & 0x3) << 28)
0061 #define RPCIF_DRENR_ADB(o)  (((o) & 0x3) << 24)
0062 #define RPCIF_DRENR_OPDB(o) (((o) & 0x3) << 20)
0063 #define RPCIF_DRENR_DRDB(o) (((o) & 0x3) << 16)
0064 #define RPCIF_DRENR_DME     BIT(15)
0065 #define RPCIF_DRENR_CDE     BIT(14)
0066 #define RPCIF_DRENR_OCDE    BIT(12)
0067 #define RPCIF_DRENR_ADE(v)  (((v) & 0xF) << 8)
0068 #define RPCIF_DRENR_OPDE(v) (((v) & 0xF) << 4)
0069 
0070 #define RPCIF_SMCR      0x0020  /* R/W */
0071 #define RPCIF_SMCR_SSLKP    BIT(8)
0072 #define RPCIF_SMCR_SPIRE    BIT(2)
0073 #define RPCIF_SMCR_SPIWE    BIT(1)
0074 #define RPCIF_SMCR_SPIE     BIT(0)
0075 
0076 #define RPCIF_SMCMR     0x0024  /* R/W */
0077 #define RPCIF_SMCMR_CMD(c)  (((c) & 0xFF) << 16)
0078 #define RPCIF_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
0079 
0080 #define RPCIF_SMADR     0x0028  /* R/W */
0081 
0082 #define RPCIF_SMOPR     0x002C  /* R/W */
0083 #define RPCIF_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
0084 #define RPCIF_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
0085 #define RPCIF_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
0086 #define RPCIF_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
0087 
0088 #define RPCIF_SMENR     0x0030  /* R/W */
0089 #define RPCIF_SMENR_CDB(o)  (((o) & 0x3) << 30)
0090 #define RPCIF_SMENR_OCDB(o) (((o) & 0x3) << 28)
0091 #define RPCIF_SMENR_ADB(o)  (((o) & 0x3) << 24)
0092 #define RPCIF_SMENR_OPDB(o) (((o) & 0x3) << 20)
0093 #define RPCIF_SMENR_SPIDB(o)    (((o) & 0x3) << 16)
0094 #define RPCIF_SMENR_DME     BIT(15)
0095 #define RPCIF_SMENR_CDE     BIT(14)
0096 #define RPCIF_SMENR_OCDE    BIT(12)
0097 #define RPCIF_SMENR_ADE(v)  (((v) & 0xF) << 8)
0098 #define RPCIF_SMENR_OPDE(v) (((v) & 0xF) << 4)
0099 #define RPCIF_SMENR_SPIDE(v)    (((v) & 0xF) << 0)
0100 
0101 #define RPCIF_SMRDR0        0x0038  /* R */
0102 #define RPCIF_SMRDR1        0x003C  /* R */
0103 #define RPCIF_SMWDR0        0x0040  /* W */
0104 #define RPCIF_SMWDR1        0x0044  /* W */
0105 
0106 #define RPCIF_CMNSR     0x0048  /* R */
0107 #define RPCIF_CMNSR_SSLF    BIT(1)
0108 #define RPCIF_CMNSR_TEND    BIT(0)
0109 
0110 #define RPCIF_DRDMCR        0x0058  /* R/W */
0111 #define RPCIF_DMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
0112 
0113 #define RPCIF_DRDRENR       0x005C  /* R/W */
0114 #define RPCIF_DRDRENR_HYPE(v)   (((v) & 0x7) << 12)
0115 #define RPCIF_DRDRENR_ADDRE BIT(8)
0116 #define RPCIF_DRDRENR_OPDRE BIT(4)
0117 #define RPCIF_DRDRENR_DRDRE BIT(0)
0118 
0119 #define RPCIF_SMDMCR        0x0060  /* R/W */
0120 #define RPCIF_SMDMCR_DMCYC(v)   ((((v) - 1) & 0x1F) << 0)
0121 
0122 #define RPCIF_SMDRENR       0x0064  /* R/W */
0123 #define RPCIF_SMDRENR_HYPE(v)   (((v) & 0x7) << 12)
0124 #define RPCIF_SMDRENR_ADDRE BIT(8)
0125 #define RPCIF_SMDRENR_OPDRE BIT(4)
0126 #define RPCIF_SMDRENR_SPIDRE    BIT(0)
0127 
0128 #define RPCIF_PHYADD        0x0070  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
0129 #define RPCIF_PHYWR     0x0074  /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
0130 
0131 #define RPCIF_PHYCNT        0x007C  /* R/W */
0132 #define RPCIF_PHYCNT_CAL    BIT(31)
0133 #define RPCIF_PHYCNT_OCTA(v)    (((v) & 0x3) << 22)
0134 #define RPCIF_PHYCNT_EXDS   BIT(21)
0135 #define RPCIF_PHYCNT_OCT    BIT(20)
0136 #define RPCIF_PHYCNT_DDRCAL BIT(19)
0137 #define RPCIF_PHYCNT_HS     BIT(18)
0138 #define RPCIF_PHYCNT_CKSEL(v)   (((v) & 0x3) << 16) /* valid only for RZ/G2L */
0139 #define RPCIF_PHYCNT_STRTIM(v)  (((v) & 0x7) << 15) /* valid for R-Car and RZ/G2{E,H,M,N} */
0140 #define RPCIF_PHYCNT_WBUF2  BIT(4)
0141 #define RPCIF_PHYCNT_WBUF   BIT(2)
0142 #define RPCIF_PHYCNT_PHYMEM(v)  (((v) & 0x3) << 0)
0143 #define RPCIF_PHYCNT_PHYMEM_MASK GENMASK(1, 0)
0144 
0145 #define RPCIF_PHYOFFSET1    0x0080  /* R/W */
0146 #define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
0147 
0148 #define RPCIF_PHYOFFSET2    0x0084  /* R/W */
0149 #define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
0150 
0151 #define RPCIF_PHYINT        0x0088  /* R/W */
0152 #define RPCIF_PHYINT_WPVAL  BIT(1)
0153 
0154 static const struct regmap_range rpcif_volatile_ranges[] = {
0155     regmap_reg_range(RPCIF_SMRDR0, RPCIF_SMRDR1),
0156     regmap_reg_range(RPCIF_SMWDR0, RPCIF_SMWDR1),
0157     regmap_reg_range(RPCIF_CMNSR, RPCIF_CMNSR),
0158 };
0159 
0160 static const struct regmap_access_table rpcif_volatile_table = {
0161     .yes_ranges = rpcif_volatile_ranges,
0162     .n_yes_ranges   = ARRAY_SIZE(rpcif_volatile_ranges),
0163 };
0164 
0165 
0166 /*
0167  * Custom accessor functions to ensure SM[RW]DR[01] are always accessed with
0168  * proper width.  Requires rpcif.xfer_size to be correctly set before!
0169  */
0170 static int rpcif_reg_read(void *context, unsigned int reg, unsigned int *val)
0171 {
0172     struct rpcif *rpc = context;
0173 
0174     switch (reg) {
0175     case RPCIF_SMRDR0:
0176     case RPCIF_SMWDR0:
0177         switch (rpc->xfer_size) {
0178         case 1:
0179             *val = readb(rpc->base + reg);
0180             return 0;
0181 
0182         case 2:
0183             *val = readw(rpc->base + reg);
0184             return 0;
0185 
0186         case 4:
0187         case 8:
0188             *val = readl(rpc->base + reg);
0189             return 0;
0190 
0191         default:
0192             return -EILSEQ;
0193         }
0194 
0195     case RPCIF_SMRDR1:
0196     case RPCIF_SMWDR1:
0197         if (rpc->xfer_size != 8)
0198             return -EILSEQ;
0199         break;
0200     }
0201 
0202     *val = readl(rpc->base + reg);
0203     return 0;
0204 }
0205 
0206 static int rpcif_reg_write(void *context, unsigned int reg, unsigned int val)
0207 {
0208     struct rpcif *rpc = context;
0209 
0210     switch (reg) {
0211     case RPCIF_SMWDR0:
0212         switch (rpc->xfer_size) {
0213         case 1:
0214             writeb(val, rpc->base + reg);
0215             return 0;
0216 
0217         case 2:
0218             writew(val, rpc->base + reg);
0219             return 0;
0220 
0221         case 4:
0222         case 8:
0223             writel(val, rpc->base + reg);
0224             return 0;
0225 
0226         default:
0227             return -EILSEQ;
0228         }
0229 
0230     case RPCIF_SMWDR1:
0231         if (rpc->xfer_size != 8)
0232             return -EILSEQ;
0233         break;
0234 
0235     case RPCIF_SMRDR0:
0236     case RPCIF_SMRDR1:
0237         return -EPERM;
0238     }
0239 
0240     writel(val, rpc->base + reg);
0241     return 0;
0242 }
0243 
0244 static const struct regmap_config rpcif_regmap_config = {
0245     .reg_bits   = 32,
0246     .val_bits   = 32,
0247     .reg_stride = 4,
0248     .reg_read   = rpcif_reg_read,
0249     .reg_write  = rpcif_reg_write,
0250     .fast_io    = true,
0251     .max_register   = RPCIF_PHYINT,
0252     .volatile_table = &rpcif_volatile_table,
0253 };
0254 
0255 int rpcif_sw_init(struct rpcif *rpc, struct device *dev)
0256 {
0257     struct platform_device *pdev = to_platform_device(dev);
0258     struct resource *res;
0259 
0260     rpc->dev = dev;
0261 
0262     rpc->base = devm_platform_ioremap_resource_byname(pdev, "regs");
0263     if (IS_ERR(rpc->base))
0264         return PTR_ERR(rpc->base);
0265 
0266     rpc->regmap = devm_regmap_init(&pdev->dev, NULL, rpc, &rpcif_regmap_config);
0267     if (IS_ERR(rpc->regmap)) {
0268         dev_err(&pdev->dev,
0269             "failed to init regmap for rpcif, error %ld\n",
0270             PTR_ERR(rpc->regmap));
0271         return  PTR_ERR(rpc->regmap);
0272     }
0273 
0274     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dirmap");
0275     rpc->dirmap = devm_ioremap_resource(&pdev->dev, res);
0276     if (IS_ERR(rpc->dirmap))
0277         return PTR_ERR(rpc->dirmap);
0278     rpc->size = resource_size(res);
0279 
0280     rpc->type = (uintptr_t)of_device_get_match_data(dev);
0281     rpc->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
0282 
0283     return PTR_ERR_OR_ZERO(rpc->rstc);
0284 }
0285 EXPORT_SYMBOL(rpcif_sw_init);
0286 
0287 static void rpcif_rzg2l_timing_adjust_sdr(struct rpcif *rpc)
0288 {
0289     regmap_write(rpc->regmap, RPCIF_PHYWR, 0xa5390000);
0290     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000000);
0291     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
0292     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000022);
0293     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00008080);
0294     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000024);
0295     regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_CKSEL(3),
0296                RPCIF_PHYCNT_CKSEL(3));
0297     regmap_write(rpc->regmap, RPCIF_PHYWR, 0x00000030);
0298     regmap_write(rpc->regmap, RPCIF_PHYADD, 0x80000032);
0299 }
0300 
0301 int rpcif_hw_init(struct rpcif *rpc, bool hyperflash)
0302 {
0303     u32 dummy;
0304 
0305     pm_runtime_get_sync(rpc->dev);
0306 
0307     if (rpc->type == RPCIF_RZ_G2L) {
0308         int ret;
0309 
0310         ret = reset_control_reset(rpc->rstc);
0311         if (ret)
0312             return ret;
0313         usleep_range(200, 300);
0314         rpcif_rzg2l_timing_adjust_sdr(rpc);
0315     }
0316 
0317     regmap_update_bits(rpc->regmap, RPCIF_PHYCNT, RPCIF_PHYCNT_PHYMEM_MASK,
0318                RPCIF_PHYCNT_PHYMEM(hyperflash ? 3 : 0));
0319 
0320     if (rpc->type == RPCIF_RCAR_GEN3)
0321         regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
0322                    RPCIF_PHYCNT_STRTIM(7), RPCIF_PHYCNT_STRTIM(7));
0323 
0324     regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET1, RPCIF_PHYOFFSET1_DDRTMG(3),
0325                RPCIF_PHYOFFSET1_DDRTMG(3));
0326     regmap_update_bits(rpc->regmap, RPCIF_PHYOFFSET2, RPCIF_PHYOFFSET2_OCTTMG(7),
0327                RPCIF_PHYOFFSET2_OCTTMG(4));
0328 
0329     if (hyperflash)
0330         regmap_update_bits(rpc->regmap, RPCIF_PHYINT,
0331                    RPCIF_PHYINT_WPVAL, 0);
0332 
0333     if (rpc->type == RPCIF_RCAR_GEN3)
0334         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
0335                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_BSZ(3),
0336                    RPCIF_CMNCR_MOIIO(3) |
0337                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
0338     else
0339         regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
0340                    RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) |
0341                    RPCIF_CMNCR_BSZ(3),
0342                    RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) |
0343                    RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0));
0344 
0345     /* Set RCF after BSZ update */
0346     regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
0347     /* Dummy read according to spec */
0348     regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
0349     regmap_write(rpc->regmap, RPCIF_SSLDR, RPCIF_SSLDR_SPNDL(7) |
0350              RPCIF_SSLDR_SLNDL(7) | RPCIF_SSLDR_SCKDL(7));
0351 
0352     pm_runtime_put(rpc->dev);
0353 
0354     rpc->bus_size = hyperflash ? 2 : 1;
0355 
0356     return 0;
0357 }
0358 EXPORT_SYMBOL(rpcif_hw_init);
0359 
0360 static int wait_msg_xfer_end(struct rpcif *rpc)
0361 {
0362     u32 sts;
0363 
0364     return regmap_read_poll_timeout(rpc->regmap, RPCIF_CMNSR, sts,
0365                     sts & RPCIF_CMNSR_TEND, 0,
0366                     USEC_PER_SEC);
0367 }
0368 
0369 static u8 rpcif_bits_set(struct rpcif *rpc, u32 nbytes)
0370 {
0371     if (rpc->bus_size == 2)
0372         nbytes /= 2;
0373     nbytes = clamp(nbytes, 1U, 4U);
0374     return GENMASK(3, 4 - nbytes);
0375 }
0376 
0377 static u8 rpcif_bit_size(u8 buswidth)
0378 {
0379     return buswidth > 4 ? 2 : ilog2(buswidth);
0380 }
0381 
0382 void rpcif_prepare(struct rpcif *rpc, const struct rpcif_op *op, u64 *offs,
0383            size_t *len)
0384 {
0385     rpc->smcr = 0;
0386     rpc->smadr = 0;
0387     rpc->enable = 0;
0388     rpc->command = 0;
0389     rpc->option = 0;
0390     rpc->dummy = 0;
0391     rpc->ddr = 0;
0392     rpc->xferlen = 0;
0393 
0394     if (op->cmd.buswidth) {
0395         rpc->enable  = RPCIF_SMENR_CDE |
0396             RPCIF_SMENR_CDB(rpcif_bit_size(op->cmd.buswidth));
0397         rpc->command = RPCIF_SMCMR_CMD(op->cmd.opcode);
0398         if (op->cmd.ddr)
0399             rpc->ddr = RPCIF_SMDRENR_HYPE(0x5);
0400     }
0401     if (op->ocmd.buswidth) {
0402         rpc->enable  |= RPCIF_SMENR_OCDE |
0403             RPCIF_SMENR_OCDB(rpcif_bit_size(op->ocmd.buswidth));
0404         rpc->command |= RPCIF_SMCMR_OCMD(op->ocmd.opcode);
0405     }
0406 
0407     if (op->addr.buswidth) {
0408         rpc->enable |=
0409             RPCIF_SMENR_ADB(rpcif_bit_size(op->addr.buswidth));
0410         if (op->addr.nbytes == 4)
0411             rpc->enable |= RPCIF_SMENR_ADE(0xF);
0412         else
0413             rpc->enable |= RPCIF_SMENR_ADE(GENMASK(
0414                         2, 3 - op->addr.nbytes));
0415         if (op->addr.ddr)
0416             rpc->ddr |= RPCIF_SMDRENR_ADDRE;
0417 
0418         if (offs && len)
0419             rpc->smadr = *offs;
0420         else
0421             rpc->smadr = op->addr.val;
0422     }
0423 
0424     if (op->dummy.buswidth) {
0425         rpc->enable |= RPCIF_SMENR_DME;
0426         rpc->dummy = RPCIF_SMDMCR_DMCYC(op->dummy.ncycles /
0427                         op->dummy.buswidth);
0428     }
0429 
0430     if (op->option.buswidth) {
0431         rpc->enable |= RPCIF_SMENR_OPDE(
0432             rpcif_bits_set(rpc, op->option.nbytes)) |
0433             RPCIF_SMENR_OPDB(rpcif_bit_size(op->option.buswidth));
0434         if (op->option.ddr)
0435             rpc->ddr |= RPCIF_SMDRENR_OPDRE;
0436         rpc->option = op->option.val;
0437     }
0438 
0439     rpc->dir = op->data.dir;
0440     if (op->data.buswidth) {
0441         u32 nbytes;
0442 
0443         rpc->buffer = op->data.buf.in;
0444         switch (op->data.dir) {
0445         case RPCIF_DATA_IN:
0446             rpc->smcr = RPCIF_SMCR_SPIRE;
0447             break;
0448         case RPCIF_DATA_OUT:
0449             rpc->smcr = RPCIF_SMCR_SPIWE;
0450             break;
0451         default:
0452             break;
0453         }
0454         if (op->data.ddr)
0455             rpc->ddr |= RPCIF_SMDRENR_SPIDRE;
0456 
0457         if (offs && len)
0458             nbytes = *len;
0459         else
0460             nbytes = op->data.nbytes;
0461         rpc->xferlen = nbytes;
0462 
0463         rpc->enable |= RPCIF_SMENR_SPIDB(rpcif_bit_size(op->data.buswidth));
0464     }
0465 }
0466 EXPORT_SYMBOL(rpcif_prepare);
0467 
0468 int rpcif_manual_xfer(struct rpcif *rpc)
0469 {
0470     u32 smenr, smcr, pos = 0, max = rpc->bus_size == 2 ? 8 : 4;
0471     int ret = 0;
0472 
0473     pm_runtime_get_sync(rpc->dev);
0474 
0475     regmap_update_bits(rpc->regmap, RPCIF_PHYCNT,
0476                RPCIF_PHYCNT_CAL, RPCIF_PHYCNT_CAL);
0477     regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
0478                RPCIF_CMNCR_MD, RPCIF_CMNCR_MD);
0479     regmap_write(rpc->regmap, RPCIF_SMCMR, rpc->command);
0480     regmap_write(rpc->regmap, RPCIF_SMOPR, rpc->option);
0481     regmap_write(rpc->regmap, RPCIF_SMDMCR, rpc->dummy);
0482     regmap_write(rpc->regmap, RPCIF_SMDRENR, rpc->ddr);
0483     regmap_write(rpc->regmap, RPCIF_SMADR, rpc->smadr);
0484     smenr = rpc->enable;
0485 
0486     switch (rpc->dir) {
0487     case RPCIF_DATA_OUT:
0488         while (pos < rpc->xferlen) {
0489             u32 bytes_left = rpc->xferlen - pos;
0490             u32 nbytes, data[2], *p = data;
0491 
0492             smcr = rpc->smcr | RPCIF_SMCR_SPIE;
0493 
0494             /* nbytes may only be 1, 2, 4, or 8 */
0495             nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
0496             if (bytes_left > nbytes)
0497                 smcr |= RPCIF_SMCR_SSLKP;
0498 
0499             smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
0500             regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
0501             rpc->xfer_size = nbytes;
0502 
0503             memcpy(data, rpc->buffer + pos, nbytes);
0504             if (nbytes == 8)
0505                 regmap_write(rpc->regmap, RPCIF_SMWDR1, *p++);
0506             regmap_write(rpc->regmap, RPCIF_SMWDR0, *p);
0507 
0508             regmap_write(rpc->regmap, RPCIF_SMCR, smcr);
0509             ret = wait_msg_xfer_end(rpc);
0510             if (ret)
0511                 goto err_out;
0512 
0513             pos += nbytes;
0514             smenr = rpc->enable &
0515                 ~RPCIF_SMENR_CDE & ~RPCIF_SMENR_ADE(0xF);
0516         }
0517         break;
0518     case RPCIF_DATA_IN:
0519         /*
0520          * RPC-IF spoils the data for the commands without an address
0521          * phase (like RDID) in the manual mode, so we'll have to work
0522          * around this issue by using the external address space read
0523          * mode instead.
0524          */
0525         if (!(smenr & RPCIF_SMENR_ADE(0xF)) && rpc->dirmap) {
0526             u32 dummy;
0527 
0528             regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
0529                        RPCIF_CMNCR_MD, 0);
0530             regmap_write(rpc->regmap, RPCIF_DRCR,
0531                      RPCIF_DRCR_RBURST(32) | RPCIF_DRCR_RBE);
0532             regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
0533             regmap_write(rpc->regmap, RPCIF_DREAR,
0534                      RPCIF_DREAR_EAC(1));
0535             regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
0536             regmap_write(rpc->regmap, RPCIF_DRENR,
0537                      smenr & ~RPCIF_SMENR_SPIDE(0xF));
0538             regmap_write(rpc->regmap, RPCIF_DRDMCR,  rpc->dummy);
0539             regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
0540             memcpy_fromio(rpc->buffer, rpc->dirmap, rpc->xferlen);
0541             regmap_write(rpc->regmap, RPCIF_DRCR, RPCIF_DRCR_RCF);
0542             /* Dummy read according to spec */
0543             regmap_read(rpc->regmap, RPCIF_DRCR, &dummy);
0544             break;
0545         }
0546         while (pos < rpc->xferlen) {
0547             u32 bytes_left = rpc->xferlen - pos;
0548             u32 nbytes, data[2], *p = data;
0549 
0550             /* nbytes may only be 1, 2, 4, or 8 */
0551             nbytes = bytes_left >= max ? max : (1 << ilog2(bytes_left));
0552 
0553             regmap_write(rpc->regmap, RPCIF_SMADR,
0554                      rpc->smadr + pos);
0555             smenr &= ~RPCIF_SMENR_SPIDE(0xF);
0556             smenr |= RPCIF_SMENR_SPIDE(rpcif_bits_set(rpc, nbytes));
0557             regmap_write(rpc->regmap, RPCIF_SMENR, smenr);
0558             regmap_write(rpc->regmap, RPCIF_SMCR,
0559                      rpc->smcr | RPCIF_SMCR_SPIE);
0560             rpc->xfer_size = nbytes;
0561             ret = wait_msg_xfer_end(rpc);
0562             if (ret)
0563                 goto err_out;
0564 
0565             if (nbytes == 8)
0566                 regmap_read(rpc->regmap, RPCIF_SMRDR1, p++);
0567             regmap_read(rpc->regmap, RPCIF_SMRDR0, p);
0568             memcpy(rpc->buffer + pos, data, nbytes);
0569 
0570             pos += nbytes;
0571         }
0572         break;
0573     default:
0574         regmap_write(rpc->regmap, RPCIF_SMENR, rpc->enable);
0575         regmap_write(rpc->regmap, RPCIF_SMCR,
0576                  rpc->smcr | RPCIF_SMCR_SPIE);
0577         ret = wait_msg_xfer_end(rpc);
0578         if (ret)
0579             goto err_out;
0580     }
0581 
0582 exit:
0583     pm_runtime_put(rpc->dev);
0584     return ret;
0585 
0586 err_out:
0587     if (reset_control_reset(rpc->rstc))
0588         dev_err(rpc->dev, "Failed to reset HW\n");
0589     rpcif_hw_init(rpc, rpc->bus_size == 2);
0590     goto exit;
0591 }
0592 EXPORT_SYMBOL(rpcif_manual_xfer);
0593 
0594 static void memcpy_fromio_readw(void *to,
0595                 const void __iomem *from,
0596                 size_t count)
0597 {
0598     const int maxw = (IS_ENABLED(CONFIG_64BIT)) ? 8 : 4;
0599     u8 buf[2];
0600 
0601     if (count && ((unsigned long)from & 1)) {
0602         *(u16 *)buf = __raw_readw((void __iomem *)((unsigned long)from & ~1));
0603         *(u8 *)to = buf[1];
0604         from++;
0605         to++;
0606         count--;
0607     }
0608     while (count >= 2 && !IS_ALIGNED((unsigned long)from, maxw)) {
0609         *(u16 *)to = __raw_readw(from);
0610         from += 2;
0611         to += 2;
0612         count -= 2;
0613     }
0614     while (count >= maxw) {
0615 #ifdef CONFIG_64BIT
0616         *(u64 *)to = __raw_readq(from);
0617 #else
0618         *(u32 *)to = __raw_readl(from);
0619 #endif
0620         from += maxw;
0621         to += maxw;
0622         count -= maxw;
0623     }
0624     while (count >= 2) {
0625         *(u16 *)to = __raw_readw(from);
0626         from += 2;
0627         to += 2;
0628         count -= 2;
0629     }
0630     if (count) {
0631         *(u16 *)buf = __raw_readw(from);
0632         *(u8 *)to = buf[0];
0633     }
0634 }
0635 
0636 ssize_t rpcif_dirmap_read(struct rpcif *rpc, u64 offs, size_t len, void *buf)
0637 {
0638     loff_t from = offs & (rpc->size - 1);
0639     size_t size = rpc->size - from;
0640 
0641     if (len > size)
0642         len = size;
0643 
0644     pm_runtime_get_sync(rpc->dev);
0645 
0646     regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MD, 0);
0647     regmap_write(rpc->regmap, RPCIF_DRCR, 0);
0648     regmap_write(rpc->regmap, RPCIF_DRCMR, rpc->command);
0649     regmap_write(rpc->regmap, RPCIF_DREAR,
0650              RPCIF_DREAR_EAV(offs >> 25) | RPCIF_DREAR_EAC(1));
0651     regmap_write(rpc->regmap, RPCIF_DROPR, rpc->option);
0652     regmap_write(rpc->regmap, RPCIF_DRENR,
0653              rpc->enable & ~RPCIF_SMENR_SPIDE(0xF));
0654     regmap_write(rpc->regmap, RPCIF_DRDMCR, rpc->dummy);
0655     regmap_write(rpc->regmap, RPCIF_DRDRENR, rpc->ddr);
0656 
0657     if (rpc->bus_size == 2)
0658         memcpy_fromio_readw(buf, rpc->dirmap + from, len);
0659     else
0660         memcpy_fromio(buf, rpc->dirmap + from, len);
0661 
0662     pm_runtime_put(rpc->dev);
0663 
0664     return len;
0665 }
0666 EXPORT_SYMBOL(rpcif_dirmap_read);
0667 
0668 static int rpcif_probe(struct platform_device *pdev)
0669 {
0670     struct platform_device *vdev;
0671     struct device_node *flash;
0672     const char *name;
0673     int ret;
0674 
0675     flash = of_get_next_child(pdev->dev.of_node, NULL);
0676     if (!flash) {
0677         dev_warn(&pdev->dev, "no flash node found\n");
0678         return -ENODEV;
0679     }
0680 
0681     if (of_device_is_compatible(flash, "jedec,spi-nor")) {
0682         name = "rpc-if-spi";
0683     } else if (of_device_is_compatible(flash, "cfi-flash")) {
0684         name = "rpc-if-hyperflash";
0685     } else  {
0686         of_node_put(flash);
0687         dev_warn(&pdev->dev, "unknown flash type\n");
0688         return -ENODEV;
0689     }
0690     of_node_put(flash);
0691 
0692     vdev = platform_device_alloc(name, pdev->id);
0693     if (!vdev)
0694         return -ENOMEM;
0695     vdev->dev.parent = &pdev->dev;
0696     platform_set_drvdata(pdev, vdev);
0697 
0698     ret = platform_device_add(vdev);
0699     if (ret) {
0700         platform_device_put(vdev);
0701         return ret;
0702     }
0703 
0704     return 0;
0705 }
0706 
0707 static int rpcif_remove(struct platform_device *pdev)
0708 {
0709     struct platform_device *vdev = platform_get_drvdata(pdev);
0710 
0711     platform_device_unregister(vdev);
0712 
0713     return 0;
0714 }
0715 
0716 static const struct of_device_id rpcif_of_match[] = {
0717     { .compatible = "renesas,rcar-gen3-rpc-if", .data = (void *)RPCIF_RCAR_GEN3 },
0718     { .compatible = "renesas,rzg2l-rpc-if", .data = (void *)RPCIF_RZ_G2L },
0719     {},
0720 };
0721 MODULE_DEVICE_TABLE(of, rpcif_of_match);
0722 
0723 static struct platform_driver rpcif_driver = {
0724     .probe  = rpcif_probe,
0725     .remove = rpcif_remove,
0726     .driver = {
0727         .name = "rpc-if",
0728         .of_match_table = rpcif_of_match,
0729     },
0730 };
0731 module_platform_driver(rpcif_driver);
0732 
0733 MODULE_DESCRIPTION("Renesas RPC-IF core driver");
0734 MODULE_LICENSE("GPL v2");
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