drivers/memory/pl172.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Memory controller driver for ARM PrimeCell PL172
0004  * PrimeCell MultiPort Memory Controller (PL172)
0005  *
0006  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
0007  *
0008  * Based on:
0009  * TI AEMIF driver, Copyright (C) 2010 - 2013 Texas Instruments Inc.
0010  */
0011
0012 #include <linux/amba/bus.h>
0013 #include <linux/clk.h>
0014 #include <linux/device.h>
0015 #include <linux/err.h>
0016 #include <linux/init.h>
0017 #include <linux/io.h>
0018 #include <linux/kernel.h>
0019 #include <linux/module.h>
0020 #include <linux/of.h>
0021 #include <linux/of_platform.h>
0022 #include <linux/time.h>
0023
0024 #define MPMC_STATIC_CFG(n)      (0x200 + 0x20 * (n))
0025 #define  MPMC_STATIC_CFG_MW_8BIT    0x0
0026 #define  MPMC_STATIC_CFG_MW_16BIT   0x1
0027 #define  MPMC_STATIC_CFG_MW_32BIT   0x2
0028 #define  MPMC_STATIC_CFG_PM     BIT(3)
0029 #define  MPMC_STATIC_CFG_PC     BIT(6)
0030 #define  MPMC_STATIC_CFG_PB     BIT(7)
0031 #define  MPMC_STATIC_CFG_EW     BIT(8)
0032 #define  MPMC_STATIC_CFG_B      BIT(19)
0033 #define  MPMC_STATIC_CFG_P      BIT(20)
0034 #define MPMC_STATIC_WAIT_WEN(n)     (0x204 + 0x20 * (n))
0035 #define  MPMC_STATIC_WAIT_WEN_MAX   0x0f
0036 #define MPMC_STATIC_WAIT_OEN(n)     (0x208 + 0x20 * (n))
0037 #define  MPMC_STATIC_WAIT_OEN_MAX   0x0f
0038 #define MPMC_STATIC_WAIT_RD(n)      (0x20c + 0x20 * (n))
0039 #define  MPMC_STATIC_WAIT_RD_MAX    0x1f
0040 #define MPMC_STATIC_WAIT_PAGE(n)    (0x210 + 0x20 * (n))
0041 #define  MPMC_STATIC_WAIT_PAGE_MAX  0x1f
0042 #define MPMC_STATIC_WAIT_WR(n)      (0x214 + 0x20 * (n))
0043 #define  MPMC_STATIC_WAIT_WR_MAX    0x1f
0044 #define MPMC_STATIC_WAIT_TURN(n)    (0x218 + 0x20 * (n))
0045 #define  MPMC_STATIC_WAIT_TURN_MAX  0x0f
0046
0047 /* Maximum number of static chip selects */
0048 #define PL172_MAX_CS        4
0049
0050 struct pl172_data {
0051     void __iomem *base;
0052     unsigned long rate;
0053     struct clk *clk;
0054 };
0055
0056 static int pl172_timing_prop(struct amba_device *adev,
0057                  const struct device_node *np, const char *name,
0058                  u32 reg_offset, u32 max, int start)
0059 {
0060     struct pl172_data *pl172 = amba_get_drvdata(adev);
0061     int cycles;
0062     u32 val;
0063
0064     if (!of_property_read_u32(np, name, &val)) {
0065         cycles = DIV_ROUND_UP(val * pl172->rate, NSEC_PER_MSEC) - start;
0066         if (cycles < 0) {
0067             cycles = 0;
0068         } else if (cycles > max) {
0069             dev_err(&adev->dev, "%s timing too tight\n", name);
0070             return -EINVAL;
0071         }
0072
0073         writel(cycles, pl172->base + reg_offset);
0074     }
0075
0076     dev_dbg(&adev->dev, "%s: %u cycle(s)\n", name, start +
0077                 readl(pl172->base + reg_offset));
0078
0079     return 0;
0080 }
0081
0082 static int pl172_setup_static(struct amba_device *adev,
0083                   struct device_node *np, u32 cs)
0084 {
0085     struct pl172_data *pl172 = amba_get_drvdata(adev);
0086     u32 cfg;
0087     int ret;
0088
0089     /* MPMC static memory configuration */
0090     if (!of_property_read_u32(np, "mpmc,memory-width", &cfg)) {
0091         if (cfg == 8) {
0092             cfg = MPMC_STATIC_CFG_MW_8BIT;
0093         } else if (cfg == 16) {
0094             cfg = MPMC_STATIC_CFG_MW_16BIT;
0095         } else if (cfg == 32) {
0096             cfg = MPMC_STATIC_CFG_MW_32BIT;
0097         } else {
0098             dev_err(&adev->dev, "invalid memory width cs%u\n", cs);
0099             return -EINVAL;
0100         }
0101     } else {
0102         dev_err(&adev->dev, "memory-width property required\n");
0103         return -EINVAL;
0104     }
0105
0106     if (of_property_read_bool(np, "mpmc,async-page-mode"))
0107         cfg |= MPMC_STATIC_CFG_PM;
0108
0109     if (of_property_read_bool(np, "mpmc,cs-active-high"))
0110         cfg |= MPMC_STATIC_CFG_PC;
0111
0112     if (of_property_read_bool(np, "mpmc,byte-lane-low"))
0113         cfg |= MPMC_STATIC_CFG_PB;
0114
0115     if (of_property_read_bool(np, "mpmc,extended-wait"))
0116         cfg |= MPMC_STATIC_CFG_EW;
0117
0118     if (amba_part(adev) == 0x172 &&
0119         of_property_read_bool(np, "mpmc,buffer-enable"))
0120         cfg |= MPMC_STATIC_CFG_B;
0121
0122     if (of_property_read_bool(np, "mpmc,write-protect"))
0123         cfg |= MPMC_STATIC_CFG_P;
0124
0125     writel(cfg, pl172->base + MPMC_STATIC_CFG(cs));
0126     dev_dbg(&adev->dev, "mpmc static config cs%u: 0x%08x\n", cs, cfg);
0127
0128     /* MPMC static memory timing */
0129     ret = pl172_timing_prop(adev, np, "mpmc,write-enable-delay",
0130                 MPMC_STATIC_WAIT_WEN(cs),
0131                 MPMC_STATIC_WAIT_WEN_MAX, 1);
0132     if (ret)
0133         goto fail;
0134
0135     ret = pl172_timing_prop(adev, np, "mpmc,output-enable-delay",
0136                 MPMC_STATIC_WAIT_OEN(cs),
0137                 MPMC_STATIC_WAIT_OEN_MAX, 0);
0138     if (ret)
0139         goto fail;
0140
0141     ret = pl172_timing_prop(adev, np, "mpmc,read-access-delay",
0142                 MPMC_STATIC_WAIT_RD(cs),
0143                 MPMC_STATIC_WAIT_RD_MAX, 1);
0144     if (ret)
0145         goto fail;
0146
0147     ret = pl172_timing_prop(adev, np, "mpmc,page-mode-read-delay",
0148                 MPMC_STATIC_WAIT_PAGE(cs),
0149                 MPMC_STATIC_WAIT_PAGE_MAX, 1);
0150     if (ret)
0151         goto fail;
0152
0153     ret = pl172_timing_prop(adev, np, "mpmc,write-access-delay",
0154                 MPMC_STATIC_WAIT_WR(cs),
0155                 MPMC_STATIC_WAIT_WR_MAX, 2);
0156     if (ret)
0157         goto fail;
0158
0159     ret = pl172_timing_prop(adev, np, "mpmc,turn-round-delay",
0160                 MPMC_STATIC_WAIT_TURN(cs),
0161                 MPMC_STATIC_WAIT_TURN_MAX, 1);
0162     if (ret)
0163         goto fail;
0164
0165     return 0;
0166 fail:
0167     dev_err(&adev->dev, "failed to configure cs%u\n", cs);
0168     return ret;
0169 }
0170
0171 static int pl172_parse_cs_config(struct amba_device *adev,
0172                  struct device_node *np)
0173 {
0174     u32 cs;
0175
0176     if (!of_property_read_u32(np, "mpmc,cs", &cs)) {
0177         if (cs >= PL172_MAX_CS) {
0178             dev_err(&adev->dev, "cs%u invalid\n", cs);
0179             return -EINVAL;
0180         }
0181
0182         return pl172_setup_static(adev, np, cs);
0183     }
0184
0185     dev_err(&adev->dev, "cs property required\n");
0186
0187     return -EINVAL;
0188 }
0189
0190 static const char * const pl172_revisions[] = {"r1", "r2", "r2p3", "r2p4"};
0191 static const char * const pl175_revisions[] = {"r1"};
0192 static const char * const pl176_revisions[] = {"r0"};
0193
0194 static int pl172_probe(struct amba_device *adev, const struct amba_id *id)
0195 {
0196     struct device_node *child_np, *np = adev->dev.of_node;
0197     struct device *dev = &adev->dev;
0198     static const char *rev = "?";
0199     struct pl172_data *pl172;
0200     int ret;
0201
0202     if (amba_part(adev) == 0x172) {
0203         if (amba_rev(adev) < ARRAY_SIZE(pl172_revisions))
0204             rev = pl172_revisions[amba_rev(adev)];
0205     } else if (amba_part(adev) == 0x175) {
0206         if (amba_rev(adev) < ARRAY_SIZE(pl175_revisions))
0207             rev = pl175_revisions[amba_rev(adev)];
0208     } else if (amba_part(adev) == 0x176) {
0209         if (amba_rev(adev) < ARRAY_SIZE(pl176_revisions))
0210             rev = pl176_revisions[amba_rev(adev)];
0211     }
0212
0213     dev_info(dev, "ARM PL%x revision %s\n", amba_part(adev), rev);
0214
0215     pl172 = devm_kzalloc(dev, sizeof(*pl172), GFP_KERNEL);
0216     if (!pl172)
0217         return -ENOMEM;
0218
0219     pl172->clk = devm_clk_get(dev, "mpmcclk");
0220     if (IS_ERR(pl172->clk)) {
0221         dev_err(dev, "no mpmcclk provided clock\n");
0222         return PTR_ERR(pl172->clk);
0223     }
0224
0225     ret = clk_prepare_enable(pl172->clk);
0226     if (ret) {
0227         dev_err(dev, "unable to mpmcclk enable clock\n");
0228         return ret;
0229     }
0230
0231     pl172->rate = clk_get_rate(pl172->clk) / MSEC_PER_SEC;
0232     if (!pl172->rate) {
0233         dev_err(dev, "unable to get mpmcclk clock rate\n");
0234         ret = -EINVAL;
0235         goto err_clk_enable;
0236     }
0237
0238     ret = amba_request_regions(adev, NULL);
0239     if (ret) {
0240         dev_err(dev, "unable to request AMBA regions\n");
0241         goto err_clk_enable;
0242     }
0243
0244     pl172->base = devm_ioremap(dev, adev->res.start,
0245                    resource_size(&adev->res));
0246     if (!pl172->base) {
0247         dev_err(dev, "ioremap failed\n");
0248         ret = -ENOMEM;
0249         goto err_no_ioremap;
0250     }
0251
0252     amba_set_drvdata(adev, pl172);
0253
0254     /*
0255      * Loop through each child node, which represent a chip select, and
0256      * configure parameters and timing. If successful; populate devices
0257      * under that node.
0258      */
0259     for_each_available_child_of_node(np, child_np) {
0260         ret = pl172_parse_cs_config(adev, child_np);
0261         if (ret)
0262             continue;
0263
0264         of_platform_populate(child_np, NULL, NULL, dev);
0265     }
0266
0267     return 0;
0268
0269 err_no_ioremap:
0270     amba_release_regions(adev);
0271 err_clk_enable:
0272     clk_disable_unprepare(pl172->clk);
0273     return ret;
0274 }
0275
0276 static void pl172_remove(struct amba_device *adev)
0277 {
0278     struct pl172_data *pl172 = amba_get_drvdata(adev);
0279
0280     clk_disable_unprepare(pl172->clk);
0281     amba_release_regions(adev);
0282 }
0283
0284 static const struct amba_id pl172_ids[] = {
0285     /*  PrimeCell MPMC PL172, EMC found on NXP LPC18xx and LPC43xx */
0286     {
0287         .id = 0x07041172,
0288         .mask   = 0x3f0fffff,
0289     },
0290     /* PrimeCell MPMC PL175, EMC found on NXP LPC32xx */
0291     {
0292         .id = 0x07041175,
0293         .mask   = 0x3f0fffff,
0294     },
0295     /* PrimeCell MPMC PL176 */
0296     {
0297         .id = 0x89041176,
0298         .mask   = 0xff0fffff,
0299     },
0300     { 0, 0 },
0301 };
0302 MODULE_DEVICE_TABLE(amba, pl172_ids);
0303
0304 static struct amba_driver pl172_driver = {
0305     .drv = {
0306         .name   = "memory-pl172",
0307     },
0308     .probe      = pl172_probe,
0309     .remove     = pl172_remove,
0310     .id_table   = pl172_ids,
0311 };
0312 module_amba_driver(pl172_driver);
0313
0314 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
0315 MODULE_DESCRIPTION("PL172 Memory Controller Driver");
0316 MODULE_LICENSE("GPL v2");