drivers/memory/mtk-smi.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2015-2016 MediaTek Inc.
0004  * Author: Yong Wu <yong.wu@mediatek.com>
0005  */
0006 #include <linux/clk.h>
0007 #include <linux/component.h>
0008 #include <linux/device.h>
0009 #include <linux/err.h>
0010 #include <linux/io.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/of_platform.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/pm_runtime.h>
0017 #include <soc/mediatek/smi.h>
0018 #include <dt-bindings/memory/mt2701-larb-port.h>
0019 #include <dt-bindings/memory/mtk-memory-port.h>
0020
0021 /* SMI COMMON */
0022 #define SMI_L1LEN           0x100
0023
0024 #define SMI_L1_ARB          0x200
0025 #define SMI_BUS_SEL         0x220
0026 #define SMI_BUS_LARB_SHIFT(larbid)  ((larbid) << 1)
0027 /* All are MMU0 defaultly. Only specialize mmu1 here. */
0028 #define F_MMU1_LARB(larbid)     (0x1 << SMI_BUS_LARB_SHIFT(larbid))
0029
0030 #define SMI_READ_FIFO_TH        0x230
0031 #define SMI_M4U_TH          0x234
0032 #define SMI_FIFO_TH1            0x238
0033 #define SMI_FIFO_TH2            0x23c
0034 #define SMI_DCM             0x300
0035 #define SMI_DUMMY           0x444
0036
0037 /* SMI LARB */
0038 #define SMI_LARB_SLP_CON                0xc
0039 #define SLP_PROT_EN                     BIT(0)
0040 #define SLP_PROT_RDY                    BIT(16)
0041
0042 #define SMI_LARB_CMD_THRT_CON       0x24
0043 #define SMI_LARB_THRT_RD_NU_LMT_MSK GENMASK(7, 4)
0044 #define SMI_LARB_THRT_RD_NU_LMT     (5 << 4)
0045
0046 #define SMI_LARB_SW_FLAG        0x40
0047 #define SMI_LARB_SW_FLAG_1      0x1
0048
0049 #define SMI_LARB_OSTDL_PORT     0x200
0050 #define SMI_LARB_OSTDL_PORTx(id)    (SMI_LARB_OSTDL_PORT + (((id) & 0x1f) << 2))
0051
0052 /* Below are about mmu enable registers, they are different in SoCs */
0053 /* gen1: mt2701 */
0054 #define REG_SMI_SECUR_CON_BASE      0x5c0
0055
0056 /* every register control 8 port, register offset 0x4 */
0057 #define REG_SMI_SECUR_CON_OFFSET(id)    (((id) >> 3) << 2)
0058 #define REG_SMI_SECUR_CON_ADDR(id)  \
0059     (REG_SMI_SECUR_CON_BASE + REG_SMI_SECUR_CON_OFFSET(id))
0060
0061 /*
0062  * every port have 4 bit to control, bit[port + 3] control virtual or physical,
0063  * bit[port + 2 : port + 1] control the domain, bit[port] control the security
0064  * or non-security.
0065  */
0066 #define SMI_SECUR_CON_VAL_MSK(id)   (~(0xf << (((id) & 0x7) << 2)))
0067 #define SMI_SECUR_CON_VAL_VIRT(id)  BIT((((id) & 0x7) << 2) + 3)
0068 /* mt2701 domain should be set to 3 */
0069 #define SMI_SECUR_CON_VAL_DOMAIN(id)    (0x3 << ((((id) & 0x7) << 2) + 1))
0070
0071 /* gen2: */
0072 /* mt8167 */
0073 #define MT8167_SMI_LARB_MMU_EN      0xfc0
0074
0075 /* mt8173 */
0076 #define MT8173_SMI_LARB_MMU_EN      0xf00
0077
0078 /* general */
0079 #define SMI_LARB_NONSEC_CON(id)     (0x380 + ((id) * 4))
0080 #define F_MMU_EN            BIT(0)
0081 #define BANK_SEL(id)            ({      \
0082     u32 _id = (id) & 0x3;               \
0083     (_id << 8 | _id << 10 | _id << 12 | _id << 14); \
0084 })
0085
0086 #define SMI_COMMON_INIT_REGS_NR     6
0087 #define SMI_LARB_PORT_NR_MAX        32
0088
0089 #define MTK_SMI_FLAG_THRT_UPDATE    BIT(0)
0090 #define MTK_SMI_FLAG_SW_FLAG        BIT(1)
0091 #define MTK_SMI_FLAG_SLEEP_CTL      BIT(2)
0092 #define MTK_SMI_CAPS(flags, _x)     (!!((flags) & (_x)))
0093
0094 struct mtk_smi_reg_pair {
0095     unsigned int        offset;
0096     u32         value;
0097 };
0098
0099 enum mtk_smi_type {
0100     MTK_SMI_GEN1,
0101     MTK_SMI_GEN2,       /* gen2 smi common */
0102     MTK_SMI_GEN2_SUB_COMM,  /* gen2 smi sub common */
0103 };
0104
0105 /* larbs: Require apb/smi clocks while gals is optional. */
0106 static const char * const mtk_smi_larb_clks[] = {"apb", "smi", "gals"};
0107 #define MTK_SMI_LARB_REQ_CLK_NR     2
0108 #define MTK_SMI_LARB_OPT_CLK_NR     1
0109
0110 /*
0111  * common: Require these four clocks in has_gals case. Otherwise, only apb/smi are required.
0112  * sub common: Require apb/smi/gals0 clocks in has_gals case. Otherwise, only apb/smi are required.
0113  */
0114 static const char * const mtk_smi_common_clks[] = {"apb", "smi", "gals0", "gals1"};
0115 #define MTK_SMI_CLK_NR_MAX      ARRAY_SIZE(mtk_smi_common_clks)
0116 #define MTK_SMI_COM_REQ_CLK_NR      2
0117 #define MTK_SMI_COM_GALS_REQ_CLK_NR MTK_SMI_CLK_NR_MAX
0118 #define MTK_SMI_SUB_COM_GALS_REQ_CLK_NR 3
0119
0120 struct mtk_smi_common_plat {
0121     enum mtk_smi_type   type;
0122     bool            has_gals;
0123     u32         bus_sel; /* Balance some larbs to enter mmu0 or mmu1 */
0124
0125     const struct mtk_smi_reg_pair   *init;
0126 };
0127
0128 struct mtk_smi_larb_gen {
0129     int port_in_larb[MTK_LARB_NR_MAX + 1];
0130     void (*config_port)(struct device *dev);
0131     unsigned int            larb_direct_to_common_mask;
0132     unsigned int            flags_general;
0133     const u8            (*ostd)[SMI_LARB_PORT_NR_MAX];
0134 };
0135
0136 struct mtk_smi {
0137     struct device           *dev;
0138     unsigned int            clk_num;
0139     struct clk_bulk_data        clks[MTK_SMI_CLK_NR_MAX];
0140     struct clk          *clk_async; /*only needed by mt2701*/
0141     union {
0142         void __iomem        *smi_ao_base; /* only for gen1 */
0143         void __iomem        *base;        /* only for gen2 */
0144     };
0145     struct device           *smi_common_dev; /* for sub common */
0146     const struct mtk_smi_common_plat *plat;
0147 };
0148
0149 struct mtk_smi_larb { /* larb: local arbiter */
0150     struct mtk_smi          smi;
0151     void __iomem            *base;
0152     struct device           *smi_common_dev; /* common or sub-common dev */
0153     const struct mtk_smi_larb_gen   *larb_gen;
0154     int             larbid;
0155     u32             *mmu;
0156     unsigned char           *bank;
0157 };
0158
0159 static int
0160 mtk_smi_larb_bind(struct device *dev, struct device *master, void *data)
0161 {
0162     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0163     struct mtk_smi_larb_iommu *larb_mmu = data;
0164     unsigned int         i;
0165
0166     for (i = 0; i < MTK_LARB_NR_MAX; i++) {
0167         if (dev == larb_mmu[i].dev) {
0168             larb->larbid = i;
0169             larb->mmu = &larb_mmu[i].mmu;
0170             larb->bank = larb_mmu[i].bank;
0171             return 0;
0172         }
0173     }
0174     return -ENODEV;
0175 }
0176
0177 static void
0178 mtk_smi_larb_unbind(struct device *dev, struct device *master, void *data)
0179 {
0180     /* Do nothing as the iommu is always enabled. */
0181 }
0182
0183 static const struct component_ops mtk_smi_larb_component_ops = {
0184     .bind = mtk_smi_larb_bind,
0185     .unbind = mtk_smi_larb_unbind,
0186 };
0187
0188 static void mtk_smi_larb_config_port_gen1(struct device *dev)
0189 {
0190     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0191     const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
0192     struct mtk_smi *common = dev_get_drvdata(larb->smi_common_dev);
0193     int i, m4u_port_id, larb_port_num;
0194     u32 sec_con_val, reg_val;
0195
0196     m4u_port_id = larb_gen->port_in_larb[larb->larbid];
0197     larb_port_num = larb_gen->port_in_larb[larb->larbid + 1]
0198             - larb_gen->port_in_larb[larb->larbid];
0199
0200     for (i = 0; i < larb_port_num; i++, m4u_port_id++) {
0201         if (*larb->mmu & BIT(i)) {
0202             /* bit[port + 3] controls the virtual or physical */
0203             sec_con_val = SMI_SECUR_CON_VAL_VIRT(m4u_port_id);
0204         } else {
0205             /* do not need to enable m4u for this port */
0206             continue;
0207         }
0208         reg_val = readl(common->smi_ao_base
0209             + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
0210         reg_val &= SMI_SECUR_CON_VAL_MSK(m4u_port_id);
0211         reg_val |= sec_con_val;
0212         reg_val |= SMI_SECUR_CON_VAL_DOMAIN(m4u_port_id);
0213         writel(reg_val,
0214             common->smi_ao_base
0215             + REG_SMI_SECUR_CON_ADDR(m4u_port_id));
0216     }
0217 }
0218
0219 static void mtk_smi_larb_config_port_mt8167(struct device *dev)
0220 {
0221     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0222
0223     writel(*larb->mmu, larb->base + MT8167_SMI_LARB_MMU_EN);
0224 }
0225
0226 static void mtk_smi_larb_config_port_mt8173(struct device *dev)
0227 {
0228     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0229
0230     writel(*larb->mmu, larb->base + MT8173_SMI_LARB_MMU_EN);
0231 }
0232
0233 static void mtk_smi_larb_config_port_gen2_general(struct device *dev)
0234 {
0235     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0236     u32 reg, flags_general = larb->larb_gen->flags_general;
0237     const u8 *larbostd = larb->larb_gen->ostd ? larb->larb_gen->ostd[larb->larbid] : NULL;
0238     int i;
0239
0240     if (BIT(larb->larbid) & larb->larb_gen->larb_direct_to_common_mask)
0241         return;
0242
0243     if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_THRT_UPDATE)) {
0244         reg = readl_relaxed(larb->base + SMI_LARB_CMD_THRT_CON);
0245         reg &= ~SMI_LARB_THRT_RD_NU_LMT_MSK;
0246         reg |= SMI_LARB_THRT_RD_NU_LMT;
0247         writel_relaxed(reg, larb->base + SMI_LARB_CMD_THRT_CON);
0248     }
0249
0250     if (MTK_SMI_CAPS(flags_general, MTK_SMI_FLAG_SW_FLAG))
0251         writel_relaxed(SMI_LARB_SW_FLAG_1, larb->base + SMI_LARB_SW_FLAG);
0252
0253     for (i = 0; i < SMI_LARB_PORT_NR_MAX && larbostd && !!larbostd[i]; i++)
0254         writel_relaxed(larbostd[i], larb->base + SMI_LARB_OSTDL_PORTx(i));
0255
0256     for_each_set_bit(i, (unsigned long *)larb->mmu, 32) {
0257         reg = readl_relaxed(larb->base + SMI_LARB_NONSEC_CON(i));
0258         reg |= F_MMU_EN;
0259         reg |= BANK_SEL(larb->bank[i]);
0260         writel(reg, larb->base + SMI_LARB_NONSEC_CON(i));
0261     }
0262 }
0263
0264 static const u8 mtk_smi_larb_mt8195_ostd[][SMI_LARB_PORT_NR_MAX] = {
0265     [0] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb0 */
0266     [1] = {0x0a, 0xc, 0x22, 0x22, 0x01, 0x0a,}, /* larb1 */
0267     [2] = {0x12, 0x12, 0x12, 0x12, 0x0a,},      /* ... */
0268     [3] = {0x12, 0x12, 0x12, 0x12, 0x28, 0x28, 0x0a,},
0269     [4] = {0x06, 0x01, 0x17, 0x06, 0x0a,},
0270     [5] = {0x06, 0x01, 0x17, 0x06, 0x06, 0x01, 0x06, 0x0a,},
0271     [6] = {0x06, 0x01, 0x06, 0x0a,},
0272     [7] = {0x0c, 0x0c, 0x12,},
0273     [8] = {0x0c, 0x0c, 0x12,},
0274     [9] = {0x0a, 0x08, 0x04, 0x06, 0x01, 0x01, 0x10, 0x18, 0x11, 0x0a,
0275         0x08, 0x04, 0x11, 0x06, 0x02, 0x06, 0x01, 0x11, 0x11, 0x06,},
0276     [10] = {0x18, 0x08, 0x01, 0x01, 0x20, 0x12, 0x18, 0x06, 0x05, 0x10,
0277         0x08, 0x08, 0x10, 0x08, 0x08, 0x18, 0x0c, 0x09, 0x0b, 0x0d,
0278         0x0d, 0x06, 0x10, 0x10,},
0279     [11] = {0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x0e, 0x01, 0x01, 0x01, 0x01,},
0280     [12] = {0x09, 0x09, 0x05, 0x05, 0x0c, 0x18, 0x02, 0x02, 0x04, 0x02,},
0281     [13] = {0x02, 0x02, 0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x08, 0x01,},
0282     [14] = {0x12, 0x12, 0x02, 0x02, 0x02, 0x02, 0x16, 0x01, 0x16, 0x01,
0283         0x01, 0x02, 0x02, 0x08, 0x02,},
0284     [15] = {},
0285     [16] = {0x28, 0x02, 0x02, 0x12, 0x02, 0x12, 0x10, 0x02, 0x02, 0x0a,
0286         0x12, 0x02, 0x0a, 0x16, 0x02, 0x04,},
0287     [17] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
0288     [18] = {0x12, 0x06, 0x12, 0x06,},
0289     [19] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
0290         0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
0291         0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
0292     [20] = {0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x04, 0x01,
0293         0x01, 0x01, 0x04, 0x0a, 0x06, 0x01, 0x01, 0x01, 0x0a, 0x06,
0294         0x01, 0x01, 0x05, 0x03, 0x03, 0x04, 0x01,},
0295     [21] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
0296     [22] = {0x28, 0x19, 0x0c, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04,},
0297     [23] = {0x18, 0x01,},
0298     [24] = {0x01, 0x01, 0x04, 0x01, 0x01, 0x01, 0x01, 0x01, 0x04, 0x01,
0299         0x01, 0x01,},
0300     [25] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0301         0x02, 0x01,},
0302     [26] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0303         0x02, 0x01,},
0304     [27] = {0x02, 0x02, 0x02, 0x28, 0x16, 0x02, 0x02, 0x02, 0x12, 0x16,
0305         0x02, 0x01,},
0306     [28] = {0x1a, 0x0e, 0x0a, 0x0a, 0x0c, 0x0e, 0x10,},
0307 };
0308
0309 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2701 = {
0310     .port_in_larb = {
0311         LARB0_PORT_OFFSET, LARB1_PORT_OFFSET,
0312         LARB2_PORT_OFFSET, LARB3_PORT_OFFSET
0313     },
0314     .config_port = mtk_smi_larb_config_port_gen1,
0315 };
0316
0317 static const struct mtk_smi_larb_gen mtk_smi_larb_mt2712 = {
0318     .config_port                = mtk_smi_larb_config_port_gen2_general,
0319     .larb_direct_to_common_mask = BIT(8) | BIT(9),      /* bdpsys */
0320 };
0321
0322 static const struct mtk_smi_larb_gen mtk_smi_larb_mt6779 = {
0323     .config_port  = mtk_smi_larb_config_port_gen2_general,
0324     .larb_direct_to_common_mask =
0325         BIT(4) | BIT(6) | BIT(11) | BIT(12) | BIT(13),
0326         /* DUMMY | IPU0 | IPU1 | CCU | MDLA */
0327 };
0328
0329 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8167 = {
0330     /* mt8167 do not need the port in larb */
0331     .config_port = mtk_smi_larb_config_port_mt8167,
0332 };
0333
0334 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8173 = {
0335     /* mt8173 do not need the port in larb */
0336     .config_port = mtk_smi_larb_config_port_mt8173,
0337 };
0338
0339 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8183 = {
0340     .config_port                = mtk_smi_larb_config_port_gen2_general,
0341     .larb_direct_to_common_mask = BIT(2) | BIT(3) | BIT(7),
0342                       /* IPU0 | IPU1 | CCU */
0343 };
0344
0345 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8186 = {
0346     .config_port                = mtk_smi_larb_config_port_gen2_general,
0347     .flags_general              = MTK_SMI_FLAG_SLEEP_CTL,
0348 };
0349
0350 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8192 = {
0351     .config_port                = mtk_smi_larb_config_port_gen2_general,
0352 };
0353
0354 static const struct mtk_smi_larb_gen mtk_smi_larb_mt8195 = {
0355     .config_port                = mtk_smi_larb_config_port_gen2_general,
0356     .flags_general              = MTK_SMI_FLAG_THRT_UPDATE | MTK_SMI_FLAG_SW_FLAG |
0357                       MTK_SMI_FLAG_SLEEP_CTL,
0358     .ostd                   = mtk_smi_larb_mt8195_ostd,
0359 };
0360
0361 static const struct of_device_id mtk_smi_larb_of_ids[] = {
0362     {.compatible = "mediatek,mt2701-smi-larb", .data = &mtk_smi_larb_mt2701},
0363     {.compatible = "mediatek,mt2712-smi-larb", .data = &mtk_smi_larb_mt2712},
0364     {.compatible = "mediatek,mt6779-smi-larb", .data = &mtk_smi_larb_mt6779},
0365     {.compatible = "mediatek,mt6795-smi-larb", .data = &mtk_smi_larb_mt8173},
0366     {.compatible = "mediatek,mt8167-smi-larb", .data = &mtk_smi_larb_mt8167},
0367     {.compatible = "mediatek,mt8173-smi-larb", .data = &mtk_smi_larb_mt8173},
0368     {.compatible = "mediatek,mt8183-smi-larb", .data = &mtk_smi_larb_mt8183},
0369     {.compatible = "mediatek,mt8186-smi-larb", .data = &mtk_smi_larb_mt8186},
0370     {.compatible = "mediatek,mt8192-smi-larb", .data = &mtk_smi_larb_mt8192},
0371     {.compatible = "mediatek,mt8195-smi-larb", .data = &mtk_smi_larb_mt8195},
0372     {}
0373 };
0374
0375 static int mtk_smi_larb_sleep_ctrl_enable(struct mtk_smi_larb *larb)
0376 {
0377     int ret;
0378     u32 tmp;
0379
0380     writel_relaxed(SLP_PROT_EN, larb->base + SMI_LARB_SLP_CON);
0381     ret = readl_poll_timeout_atomic(larb->base + SMI_LARB_SLP_CON,
0382                     tmp, !!(tmp & SLP_PROT_RDY), 10, 1000);
0383     if (ret) {
0384         /* TODO: Reset this larb if it fails here. */
0385         dev_err(larb->smi.dev, "sleep ctrl is not ready(0x%x).\n", tmp);
0386     }
0387     return ret;
0388 }
0389
0390 static void mtk_smi_larb_sleep_ctrl_disable(struct mtk_smi_larb *larb)
0391 {
0392     writel_relaxed(0, larb->base + SMI_LARB_SLP_CON);
0393 }
0394
0395 static int mtk_smi_device_link_common(struct device *dev, struct device **com_dev)
0396 {
0397     struct platform_device *smi_com_pdev;
0398     struct device_node *smi_com_node;
0399     struct device *smi_com_dev;
0400     struct device_link *link;
0401
0402     smi_com_node = of_parse_phandle(dev->of_node, "mediatek,smi", 0);
0403     if (!smi_com_node)
0404         return -EINVAL;
0405
0406     smi_com_pdev = of_find_device_by_node(smi_com_node);
0407     of_node_put(smi_com_node);
0408     if (smi_com_pdev) {
0409         /* smi common is the supplier, Make sure it is ready before */
0410         if (!platform_get_drvdata(smi_com_pdev)) {
0411             put_device(&smi_com_pdev->dev);
0412             return -EPROBE_DEFER;
0413         }
0414         smi_com_dev = &smi_com_pdev->dev;
0415         link = device_link_add(dev, smi_com_dev,
0416                        DL_FLAG_PM_RUNTIME | DL_FLAG_STATELESS);
0417         if (!link) {
0418             dev_err(dev, "Unable to link smi-common dev\n");
0419             put_device(&smi_com_pdev->dev);
0420             return -ENODEV;
0421         }
0422         *com_dev = smi_com_dev;
0423     } else {
0424         dev_err(dev, "Failed to get the smi_common device\n");
0425         return -EINVAL;
0426     }
0427     return 0;
0428 }
0429
0430 static int mtk_smi_dts_clk_init(struct device *dev, struct mtk_smi *smi,
0431                 const char * const clks[],
0432                 unsigned int clk_nr_required,
0433                 unsigned int clk_nr_optional)
0434 {
0435     int i, ret;
0436
0437     for (i = 0; i < clk_nr_required; i++)
0438         smi->clks[i].id = clks[i];
0439     ret = devm_clk_bulk_get(dev, clk_nr_required, smi->clks);
0440     if (ret)
0441         return ret;
0442
0443     for (i = clk_nr_required; i < clk_nr_required + clk_nr_optional; i++)
0444         smi->clks[i].id = clks[i];
0445     ret = devm_clk_bulk_get_optional(dev, clk_nr_optional,
0446                      smi->clks + clk_nr_required);
0447     smi->clk_num = clk_nr_required + clk_nr_optional;
0448     return ret;
0449 }
0450
0451 static int mtk_smi_larb_probe(struct platform_device *pdev)
0452 {
0453     struct mtk_smi_larb *larb;
0454     struct device *dev = &pdev->dev;
0455     int ret;
0456
0457     larb = devm_kzalloc(dev, sizeof(*larb), GFP_KERNEL);
0458     if (!larb)
0459         return -ENOMEM;
0460
0461     larb->larb_gen = of_device_get_match_data(dev);
0462     larb->base = devm_platform_ioremap_resource(pdev, 0);
0463     if (IS_ERR(larb->base))
0464         return PTR_ERR(larb->base);
0465
0466     ret = mtk_smi_dts_clk_init(dev, &larb->smi, mtk_smi_larb_clks,
0467                    MTK_SMI_LARB_REQ_CLK_NR, MTK_SMI_LARB_OPT_CLK_NR);
0468     if (ret)
0469         return ret;
0470
0471     larb->smi.dev = dev;
0472
0473     ret = mtk_smi_device_link_common(dev, &larb->smi_common_dev);
0474     if (ret < 0)
0475         return ret;
0476
0477     pm_runtime_enable(dev);
0478     platform_set_drvdata(pdev, larb);
0479     ret = component_add(dev, &mtk_smi_larb_component_ops);
0480     if (ret)
0481         goto err_pm_disable;
0482     return 0;
0483
0484 err_pm_disable:
0485     pm_runtime_disable(dev);
0486     device_link_remove(dev, larb->smi_common_dev);
0487     return ret;
0488 }
0489
0490 static int mtk_smi_larb_remove(struct platform_device *pdev)
0491 {
0492     struct mtk_smi_larb *larb = platform_get_drvdata(pdev);
0493
0494     device_link_remove(&pdev->dev, larb->smi_common_dev);
0495     pm_runtime_disable(&pdev->dev);
0496     component_del(&pdev->dev, &mtk_smi_larb_component_ops);
0497     return 0;
0498 }
0499
0500 static int __maybe_unused mtk_smi_larb_resume(struct device *dev)
0501 {
0502     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0503     const struct mtk_smi_larb_gen *larb_gen = larb->larb_gen;
0504     int ret;
0505
0506     ret = clk_bulk_prepare_enable(larb->smi.clk_num, larb->smi.clks);
0507     if (ret)
0508         return ret;
0509
0510     if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL))
0511         mtk_smi_larb_sleep_ctrl_disable(larb);
0512
0513     /* Configure the basic setting for this larb */
0514     larb_gen->config_port(dev);
0515
0516     return 0;
0517 }
0518
0519 static int __maybe_unused mtk_smi_larb_suspend(struct device *dev)
0520 {
0521     struct mtk_smi_larb *larb = dev_get_drvdata(dev);
0522     int ret;
0523
0524     if (MTK_SMI_CAPS(larb->larb_gen->flags_general, MTK_SMI_FLAG_SLEEP_CTL)) {
0525         ret = mtk_smi_larb_sleep_ctrl_enable(larb);
0526         if (ret)
0527             return ret;
0528     }
0529
0530     clk_bulk_disable_unprepare(larb->smi.clk_num, larb->smi.clks);
0531     return 0;
0532 }
0533
0534 static const struct dev_pm_ops smi_larb_pm_ops = {
0535     SET_RUNTIME_PM_OPS(mtk_smi_larb_suspend, mtk_smi_larb_resume, NULL)
0536     SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0537                      pm_runtime_force_resume)
0538 };
0539
0540 static struct platform_driver mtk_smi_larb_driver = {
0541     .probe  = mtk_smi_larb_probe,
0542     .remove = mtk_smi_larb_remove,
0543     .driver = {
0544         .name = "mtk-smi-larb",
0545         .of_match_table = mtk_smi_larb_of_ids,
0546         .pm             = &smi_larb_pm_ops,
0547     }
0548 };
0549
0550 static const struct mtk_smi_reg_pair mtk_smi_common_mt6795_init[SMI_COMMON_INIT_REGS_NR] = {
0551     {SMI_L1_ARB, 0x1b},
0552     {SMI_M4U_TH, 0xce810c85},
0553     {SMI_FIFO_TH1, 0x43214c8},
0554     {SMI_READ_FIFO_TH, 0x191f},
0555 };
0556
0557 static const struct mtk_smi_reg_pair mtk_smi_common_mt8195_init[SMI_COMMON_INIT_REGS_NR] = {
0558     {SMI_L1LEN, 0xb},
0559     {SMI_M4U_TH, 0xe100e10},
0560     {SMI_FIFO_TH1, 0x506090a},
0561     {SMI_FIFO_TH2, 0x506090a},
0562     {SMI_DCM, 0x4f1},
0563     {SMI_DUMMY, 0x1},
0564 };
0565
0566 static const struct mtk_smi_common_plat mtk_smi_common_gen1 = {
0567     .type     = MTK_SMI_GEN1,
0568 };
0569
0570 static const struct mtk_smi_common_plat mtk_smi_common_gen2 = {
0571     .type     = MTK_SMI_GEN2,
0572 };
0573
0574 static const struct mtk_smi_common_plat mtk_smi_common_mt6779 = {
0575     .type     = MTK_SMI_GEN2,
0576     .has_gals = true,
0577     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(4) |
0578             F_MMU1_LARB(5) | F_MMU1_LARB(6) | F_MMU1_LARB(7),
0579 };
0580
0581 static const struct mtk_smi_common_plat mtk_smi_common_mt6795 = {
0582     .type     = MTK_SMI_GEN2,
0583     .bus_sel  = F_MMU1_LARB(0),
0584     .init     = mtk_smi_common_mt6795_init,
0585 };
0586
0587 static const struct mtk_smi_common_plat mtk_smi_common_mt8183 = {
0588     .type     = MTK_SMI_GEN2,
0589     .has_gals = true,
0590     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
0591             F_MMU1_LARB(7),
0592 };
0593
0594 static const struct mtk_smi_common_plat mtk_smi_common_mt8186 = {
0595     .type     = MTK_SMI_GEN2,
0596     .has_gals = true,
0597     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(4) | F_MMU1_LARB(7),
0598 };
0599
0600 static const struct mtk_smi_common_plat mtk_smi_common_mt8192 = {
0601     .type     = MTK_SMI_GEN2,
0602     .has_gals = true,
0603     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(5) |
0604             F_MMU1_LARB(6),
0605 };
0606
0607 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vdo = {
0608     .type     = MTK_SMI_GEN2,
0609     .has_gals = true,
0610     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(3) | F_MMU1_LARB(5) |
0611             F_MMU1_LARB(7),
0612     .init     = mtk_smi_common_mt8195_init,
0613 };
0614
0615 static const struct mtk_smi_common_plat mtk_smi_common_mt8195_vpp = {
0616     .type     = MTK_SMI_GEN2,
0617     .has_gals = true,
0618     .bus_sel  = F_MMU1_LARB(1) | F_MMU1_LARB(2) | F_MMU1_LARB(7),
0619     .init     = mtk_smi_common_mt8195_init,
0620 };
0621
0622 static const struct mtk_smi_common_plat mtk_smi_sub_common_mt8195 = {
0623     .type     = MTK_SMI_GEN2_SUB_COMM,
0624     .has_gals = true,
0625 };
0626
0627 static const struct of_device_id mtk_smi_common_of_ids[] = {
0628     {.compatible = "mediatek,mt2701-smi-common", .data = &mtk_smi_common_gen1},
0629     {.compatible = "mediatek,mt2712-smi-common", .data = &mtk_smi_common_gen2},
0630     {.compatible = "mediatek,mt6779-smi-common", .data = &mtk_smi_common_mt6779},
0631     {.compatible = "mediatek,mt6795-smi-common", .data = &mtk_smi_common_mt6795},
0632     {.compatible = "mediatek,mt8167-smi-common", .data = &mtk_smi_common_gen2},
0633     {.compatible = "mediatek,mt8173-smi-common", .data = &mtk_smi_common_gen2},
0634     {.compatible = "mediatek,mt8183-smi-common", .data = &mtk_smi_common_mt8183},
0635     {.compatible = "mediatek,mt8186-smi-common", .data = &mtk_smi_common_mt8186},
0636     {.compatible = "mediatek,mt8192-smi-common", .data = &mtk_smi_common_mt8192},
0637     {.compatible = "mediatek,mt8195-smi-common-vdo", .data = &mtk_smi_common_mt8195_vdo},
0638     {.compatible = "mediatek,mt8195-smi-common-vpp", .data = &mtk_smi_common_mt8195_vpp},
0639     {.compatible = "mediatek,mt8195-smi-sub-common", .data = &mtk_smi_sub_common_mt8195},
0640     {}
0641 };
0642
0643 static int mtk_smi_common_probe(struct platform_device *pdev)
0644 {
0645     struct device *dev = &pdev->dev;
0646     struct mtk_smi *common;
0647     int ret, clk_required = MTK_SMI_COM_REQ_CLK_NR;
0648
0649     common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
0650     if (!common)
0651         return -ENOMEM;
0652     common->dev = dev;
0653     common->plat = of_device_get_match_data(dev);
0654
0655     if (common->plat->has_gals) {
0656         if (common->plat->type == MTK_SMI_GEN2)
0657             clk_required = MTK_SMI_COM_GALS_REQ_CLK_NR;
0658         else if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
0659             clk_required = MTK_SMI_SUB_COM_GALS_REQ_CLK_NR;
0660     }
0661     ret = mtk_smi_dts_clk_init(dev, common, mtk_smi_common_clks, clk_required, 0);
0662     if (ret)
0663         return ret;
0664
0665     /*
0666      * for mtk smi gen 1, we need to get the ao(always on) base to config
0667      * m4u port, and we need to enable the aync clock for transform the smi
0668      * clock into emi clock domain, but for mtk smi gen2, there's no smi ao
0669      * base.
0670      */
0671     if (common->plat->type == MTK_SMI_GEN1) {
0672         common->smi_ao_base = devm_platform_ioremap_resource(pdev, 0);
0673         if (IS_ERR(common->smi_ao_base))
0674             return PTR_ERR(common->smi_ao_base);
0675
0676         common->clk_async = devm_clk_get(dev, "async");
0677         if (IS_ERR(common->clk_async))
0678             return PTR_ERR(common->clk_async);
0679
0680         ret = clk_prepare_enable(common->clk_async);
0681         if (ret)
0682             return ret;
0683     } else {
0684         common->base = devm_platform_ioremap_resource(pdev, 0);
0685         if (IS_ERR(common->base))
0686             return PTR_ERR(common->base);
0687     }
0688
0689     /* link its smi-common if this is smi-sub-common */
0690     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM) {
0691         ret = mtk_smi_device_link_common(dev, &common->smi_common_dev);
0692         if (ret < 0)
0693             return ret;
0694     }
0695
0696     pm_runtime_enable(dev);
0697     platform_set_drvdata(pdev, common);
0698     return 0;
0699 }
0700
0701 static int mtk_smi_common_remove(struct platform_device *pdev)
0702 {
0703     struct mtk_smi *common = dev_get_drvdata(&pdev->dev);
0704
0705     if (common->plat->type == MTK_SMI_GEN2_SUB_COMM)
0706         device_link_remove(&pdev->dev, common->smi_common_dev);
0707     pm_runtime_disable(&pdev->dev);
0708     return 0;
0709 }
0710
0711 static int __maybe_unused mtk_smi_common_resume(struct device *dev)
0712 {
0713     struct mtk_smi *common = dev_get_drvdata(dev);
0714     const struct mtk_smi_reg_pair *init = common->plat->init;
0715     u32 bus_sel = common->plat->bus_sel; /* default is 0 */
0716     int ret, i;
0717
0718     ret = clk_bulk_prepare_enable(common->clk_num, common->clks);
0719     if (ret)
0720         return ret;
0721
0722     if (common->plat->type != MTK_SMI_GEN2)
0723         return 0;
0724
0725     for (i = 0; i < SMI_COMMON_INIT_REGS_NR && init && init[i].offset; i++)
0726         writel_relaxed(init[i].value, common->base + init[i].offset);
0727
0728     writel(bus_sel, common->base + SMI_BUS_SEL);
0729     return 0;
0730 }
0731
0732 static int __maybe_unused mtk_smi_common_suspend(struct device *dev)
0733 {
0734     struct mtk_smi *common = dev_get_drvdata(dev);
0735
0736     clk_bulk_disable_unprepare(common->clk_num, common->clks);
0737     return 0;
0738 }
0739
0740 static const struct dev_pm_ops smi_common_pm_ops = {
0741     SET_RUNTIME_PM_OPS(mtk_smi_common_suspend, mtk_smi_common_resume, NULL)
0742     SET_LATE_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0743                      pm_runtime_force_resume)
0744 };
0745
0746 static struct platform_driver mtk_smi_common_driver = {
0747     .probe  = mtk_smi_common_probe,
0748     .remove = mtk_smi_common_remove,
0749     .driver = {
0750         .name = "mtk-smi-common",
0751         .of_match_table = mtk_smi_common_of_ids,
0752         .pm             = &smi_common_pm_ops,
0753     }
0754 };
0755
0756 static struct platform_driver * const smidrivers[] = {
0757     &mtk_smi_common_driver,
0758     &mtk_smi_larb_driver,
0759 };
0760
0761 static int __init mtk_smi_init(void)
0762 {
0763     return platform_register_drivers(smidrivers, ARRAY_SIZE(smidrivers));
0764 }
0765 module_init(mtk_smi_init);
0766
0767 static void __exit mtk_smi_exit(void)
0768 {
0769     platform_unregister_drivers(smidrivers, ARRAY_SIZE(smidrivers));
0770 }
0771 module_exit(mtk_smi_exit);
0772
0773 MODULE_DESCRIPTION("MediaTek SMI driver");
0774 MODULE_LICENSE("GPL v2");