drivers/memory/jz4780-nemc.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * JZ4780 NAND/external memory controller (NEMC)
0004  *
0005  * Copyright (c) 2015 Imagination Technologies
0006  * Author: Alex Smith <alex@alex-smith.me.uk>
0007  */
0008
0009 #include <linux/clk.h>
0010 #include <linux/init.h>
0011 #include <linux/io.h>
0012 #include <linux/math64.h>
0013 #include <linux/of.h>
0014 #include <linux/of_address.h>
0015 #include <linux/of_device.h>
0016 #include <linux/of_platform.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/slab.h>
0019 #include <linux/spinlock.h>
0020
0021 #include <linux/jz4780-nemc.h>
0022
0023 #define NEMC_SMCRn(n)       (0x14 + (((n) - 1) * 4))
0024 #define NEMC_NFCSR      0x50
0025
0026 #define NEMC_REG_LEN        0x54
0027
0028 #define NEMC_SMCR_SMT       BIT(0)
0029 #define NEMC_SMCR_BW_SHIFT  6
0030 #define NEMC_SMCR_BW_MASK   (0x3 << NEMC_SMCR_BW_SHIFT)
0031 #define NEMC_SMCR_BW_8      (0 << 6)
0032 #define NEMC_SMCR_TAS_SHIFT 8
0033 #define NEMC_SMCR_TAS_MASK  (0xf << NEMC_SMCR_TAS_SHIFT)
0034 #define NEMC_SMCR_TAH_SHIFT 12
0035 #define NEMC_SMCR_TAH_MASK  (0xf << NEMC_SMCR_TAH_SHIFT)
0036 #define NEMC_SMCR_TBP_SHIFT 16
0037 #define NEMC_SMCR_TBP_MASK  (0xf << NEMC_SMCR_TBP_SHIFT)
0038 #define NEMC_SMCR_TAW_SHIFT 20
0039 #define NEMC_SMCR_TAW_MASK  (0xf << NEMC_SMCR_TAW_SHIFT)
0040 #define NEMC_SMCR_TSTRV_SHIFT   24
0041 #define NEMC_SMCR_TSTRV_MASK    (0x3f << NEMC_SMCR_TSTRV_SHIFT)
0042
0043 #define NEMC_NFCSR_NFEn(n)  BIT(((n) - 1) << 1)
0044 #define NEMC_NFCSR_NFCEn(n) BIT((((n) - 1) << 1) + 1)
0045 #define NEMC_NFCSR_TNFEn(n) BIT(16 + (n) - 1)
0046
0047 struct jz_soc_info {
0048     u8 tas_tah_cycles_max;
0049 };
0050
0051 struct jz4780_nemc {
0052     spinlock_t lock;
0053     struct device *dev;
0054     const struct jz_soc_info *soc_info;
0055     void __iomem *base;
0056     struct clk *clk;
0057     uint32_t clk_period;
0058     unsigned long banks_present;
0059 };
0060
0061 /**
0062  * jz4780_nemc_num_banks() - count the number of banks referenced by a device
0063  * @dev: device to count banks for, must be a child of the NEMC.
0064  *
0065  * Return: The number of unique NEMC banks referred to by the specified NEMC
0066  * child device. Unique here means that a device that references the same bank
0067  * multiple times in its "reg" property will only count once.
0068  */
0069 unsigned int jz4780_nemc_num_banks(struct device *dev)
0070 {
0071     const __be32 *prop;
0072     unsigned int bank, count = 0;
0073     unsigned long referenced = 0;
0074     int i = 0;
0075
0076     while ((prop = of_get_address(dev->of_node, i++, NULL, NULL))) {
0077         bank = of_read_number(prop, 1);
0078         if (!(referenced & BIT(bank))) {
0079             referenced |= BIT(bank);
0080             count++;
0081         }
0082     }
0083
0084     return count;
0085 }
0086 EXPORT_SYMBOL(jz4780_nemc_num_banks);
0087
0088 /**
0089  * jz4780_nemc_set_type() - set the type of device connected to a bank
0090  * @dev: child device of the NEMC.
0091  * @bank: bank number to configure.
0092  * @type: type of device connected to the bank.
0093  */
0094 void jz4780_nemc_set_type(struct device *dev, unsigned int bank,
0095               enum jz4780_nemc_bank_type type)
0096 {
0097     struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
0098     uint32_t nfcsr;
0099
0100     nfcsr = readl(nemc->base + NEMC_NFCSR);
0101
0102     /* TODO: Support toggle NAND devices. */
0103     switch (type) {
0104     case JZ4780_NEMC_BANK_SRAM:
0105         nfcsr &= ~(NEMC_NFCSR_TNFEn(bank) | NEMC_NFCSR_NFEn(bank));
0106         break;
0107     case JZ4780_NEMC_BANK_NAND:
0108         nfcsr &= ~NEMC_NFCSR_TNFEn(bank);
0109         nfcsr |= NEMC_NFCSR_NFEn(bank);
0110         break;
0111     }
0112
0113     writel(nfcsr, nemc->base + NEMC_NFCSR);
0114 }
0115 EXPORT_SYMBOL(jz4780_nemc_set_type);
0116
0117 /**
0118  * jz4780_nemc_assert() - (de-)assert a NAND device's chip enable pin
0119  * @dev: child device of the NEMC.
0120  * @bank: bank number of device.
0121  * @assert: whether the chip enable pin should be asserted.
0122  *
0123  * (De-)asserts the chip enable pin for the NAND device connected to the
0124  * specified bank.
0125  */
0126 void jz4780_nemc_assert(struct device *dev, unsigned int bank, bool assert)
0127 {
0128     struct jz4780_nemc *nemc = dev_get_drvdata(dev->parent);
0129     uint32_t nfcsr;
0130
0131     nfcsr = readl(nemc->base + NEMC_NFCSR);
0132
0133     if (assert)
0134         nfcsr |= NEMC_NFCSR_NFCEn(bank);
0135     else
0136         nfcsr &= ~NEMC_NFCSR_NFCEn(bank);
0137
0138     writel(nfcsr, nemc->base + NEMC_NFCSR);
0139 }
0140 EXPORT_SYMBOL(jz4780_nemc_assert);
0141
0142 static uint32_t jz4780_nemc_clk_period(struct jz4780_nemc *nemc)
0143 {
0144     unsigned long rate;
0145
0146     rate = clk_get_rate(nemc->clk);
0147     if (!rate)
0148         return 0;
0149
0150     /* Return in picoseconds. */
0151     return div64_ul(1000000000000ull, rate);
0152 }
0153
0154 static uint32_t jz4780_nemc_ns_to_cycles(struct jz4780_nemc *nemc, uint32_t ns)
0155 {
0156     return ((ns * 1000) + nemc->clk_period - 1) / nemc->clk_period;
0157 }
0158
0159 static bool jz4780_nemc_configure_bank(struct jz4780_nemc *nemc,
0160                        unsigned int bank,
0161                        struct device_node *node)
0162 {
0163     uint32_t smcr, val, cycles;
0164
0165     /*
0166      * Conversion of tBP and tAW cycle counts to values supported by the
0167      * hardware (round up to the next supported value).
0168      */
0169     static const u8 convert_tBP_tAW[] = {
0170         0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
0171
0172         /* 11 - 12 -> 12 cycles */
0173         11, 11,
0174
0175         /* 13 - 15 -> 15 cycles */
0176         12, 12, 12,
0177
0178         /* 16 - 20 -> 20 cycles */
0179         13, 13, 13, 13, 13,
0180
0181         /* 21 - 25 -> 25 cycles */
0182         14, 14, 14, 14, 14,
0183
0184         /* 26 - 31 -> 31 cycles */
0185         15, 15, 15, 15, 15, 15
0186     };
0187
0188     smcr = readl(nemc->base + NEMC_SMCRn(bank));
0189     smcr &= ~NEMC_SMCR_SMT;
0190
0191     if (!of_property_read_u32(node, "ingenic,nemc-bus-width", &val)) {
0192         smcr &= ~NEMC_SMCR_BW_MASK;
0193         switch (val) {
0194         case 8:
0195             smcr |= NEMC_SMCR_BW_8;
0196             break;
0197         default:
0198             /*
0199              * Earlier SoCs support a 16 bit bus width (the 4780
0200              * does not), until those are properly supported, error.
0201              */
0202             dev_err(nemc->dev, "unsupported bus width: %u\n", val);
0203             return false;
0204         }
0205     }
0206
0207     if (of_property_read_u32(node, "ingenic,nemc-tAS", &val) == 0) {
0208         smcr &= ~NEMC_SMCR_TAS_MASK;
0209         cycles = jz4780_nemc_ns_to_cycles(nemc, val);
0210         if (cycles > nemc->soc_info->tas_tah_cycles_max) {
0211             dev_err(nemc->dev, "tAS %u is too high (%u cycles)\n",
0212                 val, cycles);
0213             return false;
0214         }
0215
0216         smcr |= cycles << NEMC_SMCR_TAS_SHIFT;
0217     }
0218
0219     if (of_property_read_u32(node, "ingenic,nemc-tAH", &val) == 0) {
0220         smcr &= ~NEMC_SMCR_TAH_MASK;
0221         cycles = jz4780_nemc_ns_to_cycles(nemc, val);
0222         if (cycles > nemc->soc_info->tas_tah_cycles_max) {
0223             dev_err(nemc->dev, "tAH %u is too high (%u cycles)\n",
0224                 val, cycles);
0225             return false;
0226         }
0227
0228         smcr |= cycles << NEMC_SMCR_TAH_SHIFT;
0229     }
0230
0231     if (of_property_read_u32(node, "ingenic,nemc-tBP", &val) == 0) {
0232         smcr &= ~NEMC_SMCR_TBP_MASK;
0233         cycles = jz4780_nemc_ns_to_cycles(nemc, val);
0234         if (cycles > 31) {
0235             dev_err(nemc->dev, "tBP %u is too high (%u cycles)\n",
0236                 val, cycles);
0237             return false;
0238         }
0239
0240         smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TBP_SHIFT;
0241     }
0242
0243     if (of_property_read_u32(node, "ingenic,nemc-tAW", &val) == 0) {
0244         smcr &= ~NEMC_SMCR_TAW_MASK;
0245         cycles = jz4780_nemc_ns_to_cycles(nemc, val);
0246         if (cycles > 31) {
0247             dev_err(nemc->dev, "tAW %u is too high (%u cycles)\n",
0248                 val, cycles);
0249             return false;
0250         }
0251
0252         smcr |= convert_tBP_tAW[cycles] << NEMC_SMCR_TAW_SHIFT;
0253     }
0254
0255     if (of_property_read_u32(node, "ingenic,nemc-tSTRV", &val) == 0) {
0256         smcr &= ~NEMC_SMCR_TSTRV_MASK;
0257         cycles = jz4780_nemc_ns_to_cycles(nemc, val);
0258         if (cycles > 63) {
0259             dev_err(nemc->dev, "tSTRV %u is too high (%u cycles)\n",
0260                 val, cycles);
0261             return false;
0262         }
0263
0264         smcr |= cycles << NEMC_SMCR_TSTRV_SHIFT;
0265     }
0266
0267     writel(smcr, nemc->base + NEMC_SMCRn(bank));
0268     return true;
0269 }
0270
0271 static int jz4780_nemc_probe(struct platform_device *pdev)
0272 {
0273     struct device *dev = &pdev->dev;
0274     struct jz4780_nemc *nemc;
0275     struct resource *res;
0276     struct device_node *child;
0277     const __be32 *prop;
0278     unsigned int bank;
0279     unsigned long referenced;
0280     int i, ret;
0281
0282     nemc = devm_kzalloc(dev, sizeof(*nemc), GFP_KERNEL);
0283     if (!nemc)
0284         return -ENOMEM;
0285
0286     nemc->soc_info = device_get_match_data(dev);
0287     if (!nemc->soc_info)
0288         return -EINVAL;
0289
0290     spin_lock_init(&nemc->lock);
0291     nemc->dev = dev;
0292
0293     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0294     if (!res)
0295         return -EINVAL;
0296
0297     /*
0298      * The driver currently only uses the registers up to offset
0299      * NEMC_REG_LEN. Since the EFUSE registers are in the middle of the
0300      * NEMC registers, we only request the registers we will use for now;
0301      * that way the EFUSE driver can probe too.
0302      */
0303     if (!devm_request_mem_region(dev, res->start, NEMC_REG_LEN, dev_name(dev))) {
0304         dev_err(dev, "unable to request I/O memory region\n");
0305         return -EBUSY;
0306     }
0307
0308     nemc->base = devm_ioremap(dev, res->start, NEMC_REG_LEN);
0309     if (!nemc->base) {
0310         dev_err(dev, "failed to get I/O memory\n");
0311         return -ENOMEM;
0312     }
0313
0314     writel(0, nemc->base + NEMC_NFCSR);
0315
0316     nemc->clk = devm_clk_get(dev, NULL);
0317     if (IS_ERR(nemc->clk)) {
0318         dev_err(dev, "failed to get clock\n");
0319         return PTR_ERR(nemc->clk);
0320     }
0321
0322     ret = clk_prepare_enable(nemc->clk);
0323     if (ret) {
0324         dev_err(dev, "failed to enable clock: %d\n", ret);
0325         return ret;
0326     }
0327
0328     nemc->clk_period = jz4780_nemc_clk_period(nemc);
0329     if (!nemc->clk_period) {
0330         dev_err(dev, "failed to calculate clock period\n");
0331         clk_disable_unprepare(nemc->clk);
0332         return -EINVAL;
0333     }
0334
0335     /*
0336      * Iterate over child devices, check that they do not conflict with
0337      * each other, and register child devices for them. If a child device
0338      * has invalid properties, it is ignored and no platform device is
0339      * registered for it.
0340      */
0341     for_each_child_of_node(nemc->dev->of_node, child) {
0342         referenced = 0;
0343         i = 0;
0344         while ((prop = of_get_address(child, i++, NULL, NULL))) {
0345             bank = of_read_number(prop, 1);
0346             if (bank < 1 || bank >= JZ4780_NEMC_NUM_BANKS) {
0347                 dev_err(nemc->dev,
0348                     "%pOF requests invalid bank %u\n",
0349                     child, bank);
0350
0351                 /* Will continue the outer loop below. */
0352                 referenced = 0;
0353                 break;
0354             }
0355
0356             referenced |= BIT(bank);
0357         }
0358
0359         if (!referenced) {
0360             dev_err(nemc->dev, "%pOF has no addresses\n",
0361                 child);
0362             continue;
0363         } else if (nemc->banks_present & referenced) {
0364             dev_err(nemc->dev, "%pOF conflicts with another node\n",
0365                 child);
0366             continue;
0367         }
0368
0369         /* Configure bank parameters. */
0370         for_each_set_bit(bank, &referenced, JZ4780_NEMC_NUM_BANKS) {
0371             if (!jz4780_nemc_configure_bank(nemc, bank, child)) {
0372                 referenced = 0;
0373                 break;
0374             }
0375         }
0376
0377         if (referenced) {
0378             if (of_platform_device_create(child, NULL, nemc->dev))
0379                 nemc->banks_present |= referenced;
0380         }
0381     }
0382
0383     platform_set_drvdata(pdev, nemc);
0384     dev_info(dev, "JZ4780 NEMC initialised\n");
0385     return 0;
0386 }
0387
0388 static int jz4780_nemc_remove(struct platform_device *pdev)
0389 {
0390     struct jz4780_nemc *nemc = platform_get_drvdata(pdev);
0391
0392     clk_disable_unprepare(nemc->clk);
0393     return 0;
0394 }
0395
0396 static const struct jz_soc_info jz4740_soc_info = {
0397     .tas_tah_cycles_max = 7,
0398 };
0399
0400 static const struct jz_soc_info jz4780_soc_info = {
0401     .tas_tah_cycles_max = 15,
0402 };
0403
0404 static const struct of_device_id jz4780_nemc_dt_match[] = {
0405     { .compatible = "ingenic,jz4740-nemc", .data = &jz4740_soc_info, },
0406     { .compatible = "ingenic,jz4780-nemc", .data = &jz4780_soc_info, },
0407     {},
0408 };
0409
0410 static struct platform_driver jz4780_nemc_driver = {
0411     .probe      = jz4780_nemc_probe,
0412     .remove     = jz4780_nemc_remove,
0413     .driver = {
0414         .name   = "jz4780-nemc",
0415         .of_match_table = of_match_ptr(jz4780_nemc_dt_match),
0416     },
0417 };
0418
0419 static int __init jz4780_nemc_init(void)
0420 {
0421     return platform_driver_register(&jz4780_nemc_driver);
0422 }
0423 subsys_initcall(jz4780_nemc_init);