drivers/memory/jedec_ddr_data.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * DDR addressing details and AC timing parameters from JEDEC specs
0004  *
0005  * Copyright (C) 2012 Texas Instruments, Inc.
0006  *
0007  * Aneesh V <aneesh@ti.com>
0008  */
0009
0010 #include <linux/export.h>
0011
0012 #include "jedec_ddr.h"
0013
0014 /* LPDDR2 addressing details from JESD209-2 section 2.4 */
0015 const struct lpddr2_addressing
0016     lpddr2_jedec_addressing_table[NUM_DDR_ADDR_TABLE_ENTRIES] = {
0017     {B4, T_REFI_15_6, T_RFC_90}, /* 64M */
0018     {B4, T_REFI_15_6, T_RFC_90}, /* 128M */
0019     {B4, T_REFI_7_8,  T_RFC_90}, /* 256M */
0020     {B4, T_REFI_7_8,  T_RFC_90}, /* 512M */
0021     {B8, T_REFI_7_8, T_RFC_130}, /* 1GS4 */
0022     {B8, T_REFI_3_9, T_RFC_130}, /* 2GS4 */
0023     {B8, T_REFI_3_9, T_RFC_130}, /* 4G */
0024     {B8, T_REFI_3_9, T_RFC_210}, /* 8G */
0025     {B4, T_REFI_7_8, T_RFC_130}, /* 1GS2 */
0026     {B4, T_REFI_3_9, T_RFC_130}, /* 2GS2 */
0027 };
0028 EXPORT_SYMBOL_GPL(lpddr2_jedec_addressing_table);
0029
0030 /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
0031 const struct lpddr2_timings
0032     lpddr2_jedec_timings[NUM_DDR_TIMING_TABLE_ENTRIES] = {
0033     /* Speed bin 400(200 MHz) */
0034     [0] = {
0035         .max_freq   = 200000000,
0036         .min_freq   = 10000000,
0037         .tRPab      = 21000,
0038         .tRCD       = 18000,
0039         .tWR        = 15000,
0040         .tRAS_min   = 42000,
0041         .tRRD       = 10000,
0042         .tWTR       = 10000,
0043         .tXP        = 7500,
0044         .tRTP       = 7500,
0045         .tCKESR     = 15000,
0046         .tDQSCK_max = 5500,
0047         .tFAW       = 50000,
0048         .tZQCS      = 90000,
0049         .tZQCL      = 360000,
0050         .tZQinit    = 1000000,
0051         .tRAS_max_ns    = 70000,
0052         .tDQSCK_max_derated = 6000,
0053     },
0054     /* Speed bin 533(266 MHz) */
0055     [1] = {
0056         .max_freq   = 266666666,
0057         .min_freq   = 10000000,
0058         .tRPab      = 21000,
0059         .tRCD       = 18000,
0060         .tWR        = 15000,
0061         .tRAS_min   = 42000,
0062         .tRRD       = 10000,
0063         .tWTR       = 7500,
0064         .tXP        = 7500,
0065         .tRTP       = 7500,
0066         .tCKESR     = 15000,
0067         .tDQSCK_max = 5500,
0068         .tFAW       = 50000,
0069         .tZQCS      = 90000,
0070         .tZQCL      = 360000,
0071         .tZQinit    = 1000000,
0072         .tRAS_max_ns    = 70000,
0073         .tDQSCK_max_derated = 6000,
0074     },
0075     /* Speed bin 800(400 MHz) */
0076     [2] = {
0077         .max_freq   = 400000000,
0078         .min_freq   = 10000000,
0079         .tRPab      = 21000,
0080         .tRCD       = 18000,
0081         .tWR        = 15000,
0082         .tRAS_min   = 42000,
0083         .tRRD       = 10000,
0084         .tWTR       = 7500,
0085         .tXP        = 7500,
0086         .tRTP       = 7500,
0087         .tCKESR     = 15000,
0088         .tDQSCK_max = 5500,
0089         .tFAW       = 50000,
0090         .tZQCS      = 90000,
0091         .tZQCL      = 360000,
0092         .tZQinit    = 1000000,
0093         .tRAS_max_ns    = 70000,
0094         .tDQSCK_max_derated = 6000,
0095     },
0096     /* Speed bin 1066(533 MHz) */
0097     [3] = {
0098         .max_freq   = 533333333,
0099         .min_freq   = 10000000,
0100         .tRPab      = 21000,
0101         .tRCD       = 18000,
0102         .tWR        = 15000,
0103         .tRAS_min   = 42000,
0104         .tRRD       = 10000,
0105         .tWTR       = 7500,
0106         .tXP        = 7500,
0107         .tRTP       = 7500,
0108         .tCKESR     = 15000,
0109         .tDQSCK_max = 5500,
0110         .tFAW       = 50000,
0111         .tZQCS      = 90000,
0112         .tZQCL      = 360000,
0113         .tZQinit    = 1000000,
0114         .tRAS_max_ns    = 70000,
0115         .tDQSCK_max_derated = 5620,
0116     },
0117 };
0118 EXPORT_SYMBOL_GPL(lpddr2_jedec_timings);
0119
0120 const struct lpddr2_min_tck lpddr2_jedec_min_tck = {
0121     .tRPab      = 3,
0122     .tRCD       = 3,
0123     .tWR        = 3,
0124     .tRASmin    = 3,
0125     .tRRD       = 2,
0126     .tWTR       = 2,
0127     .tXP        = 2,
0128     .tRTP       = 2,
0129     .tCKE       = 3,
0130     .tCKESR     = 3,
0131     .tFAW       = 8
0132 };
0133 EXPORT_SYMBOL_GPL(lpddr2_jedec_min_tck);
0134
0135 const char *lpddr2_jedec_manufacturer(unsigned int manufacturer_id)
0136 {
0137     switch (manufacturer_id) {
0138     case LPDDR2_MANID_SAMSUNG:
0139         return "Samsung";
0140     case LPDDR2_MANID_QIMONDA:
0141         return "Qimonda";
0142     case LPDDR2_MANID_ELPIDA:
0143         return "Elpida";
0144     case LPDDR2_MANID_ETRON:
0145         return "Etron";
0146     case LPDDR2_MANID_NANYA:
0147         return "Nanya";
0148     case LPDDR2_MANID_HYNIX:
0149         return "Hynix";
0150     case LPDDR2_MANID_MOSEL:
0151         return "Mosel";
0152     case LPDDR2_MANID_WINBOND:
0153         return "Winbond";
0154     case LPDDR2_MANID_ESMT:
0155         return "ESMT";
0156     case LPDDR2_MANID_SPANSION:
0157         return "Spansion";
0158     case LPDDR2_MANID_SST:
0159         return "SST";
0160     case LPDDR2_MANID_ZMOS:
0161         return "ZMOS";
0162     case LPDDR2_MANID_INTEL:
0163         return "Intel";
0164     case LPDDR2_MANID_NUMONYX:
0165         return "Numonyx";
0166     case LPDDR2_MANID_MICRON:
0167         return "Micron";
0168     default:
0169         break;
0170     }
0171
0172     return "invalid";
0173 }
0174 EXPORT_SYMBOL_GPL(lpddr2_jedec_manufacturer);