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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /* Frontend part of the Linux driver for the Afatech 9005
0003  * USB1.1 DVB-T receiver.
0004  *
0005  * Copyright (C) 2007 Luca Olivetti (luca@ventoso.org)
0006  *
0007  * Thanks to Afatech who kindly provided information.
0008  *
0009  * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
0010  */
0011 #include "af9005.h"
0012 #include "af9005-script.h"
0013 #include "mt2060.h"
0014 #include "qt1010.h"
0015 #include <asm/div64.h>
0016 
0017 struct af9005_fe_state {
0018     struct dvb_usb_device *d;
0019     enum fe_status stat;
0020 
0021     /* retraining parameters */
0022     u32 original_fcw;
0023     u16 original_rf_top;
0024     u16 original_if_top;
0025     u16 original_if_min;
0026     u16 original_aci0_if_top;
0027     u16 original_aci1_if_top;
0028     u16 original_aci0_if_min;
0029     u8 original_if_unplug_th;
0030     u8 original_rf_unplug_th;
0031     u8 original_dtop_if_unplug_th;
0032     u8 original_dtop_rf_unplug_th;
0033 
0034     /* statistics */
0035     u32 pre_vit_error_count;
0036     u32 pre_vit_bit_count;
0037     u32 ber;
0038     u32 post_vit_error_count;
0039     u32 post_vit_bit_count;
0040     u32 unc;
0041     u16 abort_count;
0042 
0043     int opened;
0044     int strong;
0045     unsigned long next_status_check;
0046     struct dvb_frontend frontend;
0047 };
0048 
0049 static int af9005_write_word_agc(struct dvb_usb_device *d, u16 reghi,
0050                  u16 reglo, u8 pos, u8 len, u16 value)
0051 {
0052     int ret;
0053 
0054     if ((ret = af9005_write_ofdm_register(d, reglo, (u8) (value & 0xff))))
0055         return ret;
0056     return af9005_write_register_bits(d, reghi, pos, len,
0057                       (u8) ((value & 0x300) >> 8));
0058 }
0059 
0060 static int af9005_read_word_agc(struct dvb_usb_device *d, u16 reghi,
0061                 u16 reglo, u8 pos, u8 len, u16 * value)
0062 {
0063     int ret;
0064     u8 temp0, temp1;
0065 
0066     if ((ret = af9005_read_ofdm_register(d, reglo, &temp0)))
0067         return ret;
0068     if ((ret = af9005_read_ofdm_register(d, reghi, &temp1)))
0069         return ret;
0070     switch (pos) {
0071     case 0:
0072         *value = ((u16) (temp1 & 0x03) << 8) + (u16) temp0;
0073         break;
0074     case 2:
0075         *value = ((u16) (temp1 & 0x0C) << 6) + (u16) temp0;
0076         break;
0077     case 4:
0078         *value = ((u16) (temp1 & 0x30) << 4) + (u16) temp0;
0079         break;
0080     case 6:
0081         *value = ((u16) (temp1 & 0xC0) << 2) + (u16) temp0;
0082         break;
0083     default:
0084         err("invalid pos in read word agc");
0085         return -EINVAL;
0086     }
0087     return 0;
0088 
0089 }
0090 
0091 static int af9005_is_fecmon_available(struct dvb_frontend *fe, int *available)
0092 {
0093     struct af9005_fe_state *state = fe->demodulator_priv;
0094     int ret;
0095     u8 temp;
0096 
0097     *available = false;
0098 
0099     ret = af9005_read_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
0100                     fec_vtb_rsd_mon_en_pos,
0101                     fec_vtb_rsd_mon_en_len, &temp);
0102     if (ret)
0103         return ret;
0104     if (temp & 1) {
0105         ret =
0106             af9005_read_register_bits(state->d,
0107                           xd_p_reg_ofsm_read_rbc_en,
0108                           reg_ofsm_read_rbc_en_pos,
0109                           reg_ofsm_read_rbc_en_len, &temp);
0110         if (ret)
0111             return ret;
0112         if ((temp & 1) == 0)
0113             *available = true;
0114 
0115     }
0116     return 0;
0117 }
0118 
0119 static int af9005_get_post_vit_err_cw_count(struct dvb_frontend *fe,
0120                         u32 * post_err_count,
0121                         u32 * post_cw_count,
0122                         u16 * abort_count)
0123 {
0124     struct af9005_fe_state *state = fe->demodulator_priv;
0125     int ret;
0126     u32 err_count;
0127     u32 cw_count;
0128     u8 temp, temp0, temp1, temp2;
0129     u16 loc_abort_count;
0130 
0131     *post_err_count = 0;
0132     *post_cw_count = 0;
0133 
0134     /* check if error bit count is ready */
0135     ret =
0136         af9005_read_register_bits(state->d, xd_r_fec_rsd_ber_rdy,
0137                       fec_rsd_ber_rdy_pos, fec_rsd_ber_rdy_len,
0138                       &temp);
0139     if (ret)
0140         return ret;
0141     if (!temp) {
0142         deb_info("rsd counter not ready\n");
0143         return 100;
0144     }
0145     /* get abort count */
0146     ret =
0147         af9005_read_ofdm_register(state->d,
0148                       xd_r_fec_rsd_abort_packet_cnt_7_0,
0149                       &temp0);
0150     if (ret)
0151         return ret;
0152     ret =
0153         af9005_read_ofdm_register(state->d,
0154                       xd_r_fec_rsd_abort_packet_cnt_15_8,
0155                       &temp1);
0156     if (ret)
0157         return ret;
0158     loc_abort_count = ((u16) temp1 << 8) + temp0;
0159 
0160     /* get error count */
0161     ret =
0162         af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_7_0,
0163                       &temp0);
0164     if (ret)
0165         return ret;
0166     ret =
0167         af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_15_8,
0168                       &temp1);
0169     if (ret)
0170         return ret;
0171     ret =
0172         af9005_read_ofdm_register(state->d, xd_r_fec_rsd_bit_err_cnt_23_16,
0173                       &temp2);
0174     if (ret)
0175         return ret;
0176     err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
0177     *post_err_count = err_count - (u32) loc_abort_count *8 * 8;
0178 
0179     /* get RSD packet number */
0180     ret =
0181         af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
0182                       &temp0);
0183     if (ret)
0184         return ret;
0185     ret =
0186         af9005_read_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
0187                       &temp1);
0188     if (ret)
0189         return ret;
0190     cw_count = ((u32) temp1 << 8) + temp0;
0191     if (cw_count == 0) {
0192         err("wrong RSD packet count");
0193         return -EIO;
0194     }
0195     deb_info("POST abort count %d err count %d rsd packets %d\n",
0196          loc_abort_count, err_count, cw_count);
0197     *post_cw_count = cw_count - (u32) loc_abort_count;
0198     *abort_count = loc_abort_count;
0199     return 0;
0200 
0201 }
0202 
0203 static int af9005_get_post_vit_ber(struct dvb_frontend *fe,
0204                    u32 * post_err_count, u32 * post_cw_count,
0205                    u16 * abort_count)
0206 {
0207     u32 loc_cw_count = 0, loc_err_count;
0208     u16 loc_abort_count = 0;
0209     int ret;
0210 
0211     ret =
0212         af9005_get_post_vit_err_cw_count(fe, &loc_err_count, &loc_cw_count,
0213                          &loc_abort_count);
0214     if (ret)
0215         return ret;
0216     *post_err_count = loc_err_count;
0217     *post_cw_count = loc_cw_count * 204 * 8;
0218     *abort_count = loc_abort_count;
0219 
0220     return 0;
0221 }
0222 
0223 static int af9005_get_pre_vit_err_bit_count(struct dvb_frontend *fe,
0224                         u32 * pre_err_count,
0225                         u32 * pre_bit_count)
0226 {
0227     struct af9005_fe_state *state = fe->demodulator_priv;
0228     u8 temp, temp0, temp1, temp2;
0229     u32 super_frame_count, x, bits;
0230     int ret;
0231 
0232     ret =
0233         af9005_read_register_bits(state->d, xd_r_fec_vtb_ber_rdy,
0234                       fec_vtb_ber_rdy_pos, fec_vtb_ber_rdy_len,
0235                       &temp);
0236     if (ret)
0237         return ret;
0238     if (!temp) {
0239         deb_info("viterbi counter not ready\n");
0240         return 101; /* ERR_APO_VTB_COUNTER_NOT_READY; */
0241     }
0242     ret =
0243         af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_7_0,
0244                       &temp0);
0245     if (ret)
0246         return ret;
0247     ret =
0248         af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_15_8,
0249                       &temp1);
0250     if (ret)
0251         return ret;
0252     ret =
0253         af9005_read_ofdm_register(state->d, xd_r_fec_vtb_err_bit_cnt_23_16,
0254                       &temp2);
0255     if (ret)
0256         return ret;
0257     *pre_err_count = ((u32) temp2 << 16) + ((u32) temp1 << 8) + temp0;
0258 
0259     ret =
0260         af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
0261                       &temp0);
0262     if (ret)
0263         return ret;
0264     ret =
0265         af9005_read_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
0266                       &temp1);
0267     if (ret)
0268         return ret;
0269     super_frame_count = ((u32) temp1 << 8) + temp0;
0270     if (super_frame_count == 0) {
0271         deb_info("super frame count 0\n");
0272         return 102;
0273     }
0274 
0275     /* read fft mode */
0276     ret =
0277         af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
0278                       reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
0279                       &temp);
0280     if (ret)
0281         return ret;
0282     if (temp == 0) {
0283         /* 2K */
0284         x = 1512;
0285     } else if (temp == 1) {
0286         /* 8k */
0287         x = 6048;
0288     } else {
0289         err("Invalid fft mode");
0290         return -EINVAL;
0291     }
0292 
0293     /* read modulation mode */
0294     ret =
0295         af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
0296                       reg_tpsd_const_pos, reg_tpsd_const_len,
0297                       &temp);
0298     if (ret)
0299         return ret;
0300     switch (temp) {
0301     case 0:     /* QPSK */
0302         bits = 2;
0303         break;
0304     case 1:     /* QAM_16 */
0305         bits = 4;
0306         break;
0307     case 2:     /* QAM_64 */
0308         bits = 6;
0309         break;
0310     default:
0311         err("invalid modulation mode");
0312         return -EINVAL;
0313     }
0314     *pre_bit_count = super_frame_count * 68 * 4 * x * bits;
0315     deb_info("PRE err count %d frame count %d bit count %d\n",
0316          *pre_err_count, super_frame_count, *pre_bit_count);
0317     return 0;
0318 }
0319 
0320 static int af9005_reset_pre_viterbi(struct dvb_frontend *fe)
0321 {
0322     struct af9005_fe_state *state = fe->demodulator_priv;
0323     int ret;
0324 
0325     /* set super frame count to 1 */
0326     ret =
0327         af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_7_0,
0328                        1 & 0xff);
0329     if (ret)
0330         return ret;
0331     ret = af9005_write_ofdm_register(state->d, xd_p_fec_super_frm_unit_15_8,
0332                      1 >> 8);
0333     if (ret)
0334         return ret;
0335     /* reset pre viterbi error count */
0336     ret =
0337         af9005_write_register_bits(state->d, xd_p_fec_vtb_ber_rst,
0338                        fec_vtb_ber_rst_pos, fec_vtb_ber_rst_len,
0339                        1);
0340 
0341     return ret;
0342 }
0343 
0344 static int af9005_reset_post_viterbi(struct dvb_frontend *fe)
0345 {
0346     struct af9005_fe_state *state = fe->demodulator_priv;
0347     int ret;
0348 
0349     /* set packet unit */
0350     ret =
0351         af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_7_0,
0352                        10000 & 0xff);
0353     if (ret)
0354         return ret;
0355     ret =
0356         af9005_write_ofdm_register(state->d, xd_p_fec_rsd_packet_unit_15_8,
0357                        10000 >> 8);
0358     if (ret)
0359         return ret;
0360     /* reset post viterbi error count */
0361     ret =
0362         af9005_write_register_bits(state->d, xd_p_fec_rsd_ber_rst,
0363                        fec_rsd_ber_rst_pos, fec_rsd_ber_rst_len,
0364                        1);
0365 
0366     return ret;
0367 }
0368 
0369 static int af9005_get_statistic(struct dvb_frontend *fe)
0370 {
0371     struct af9005_fe_state *state = fe->demodulator_priv;
0372     int ret, fecavailable;
0373     u64 numerator, denominator;
0374 
0375     deb_info("GET STATISTIC\n");
0376     ret = af9005_is_fecmon_available(fe, &fecavailable);
0377     if (ret)
0378         return ret;
0379     if (!fecavailable) {
0380         deb_info("fecmon not available\n");
0381         return 0;
0382     }
0383 
0384     ret = af9005_get_pre_vit_err_bit_count(fe, &state->pre_vit_error_count,
0385                            &state->pre_vit_bit_count);
0386     if (ret == 0) {
0387         af9005_reset_pre_viterbi(fe);
0388         if (state->pre_vit_bit_count > 0) {
0389             /* according to v 0.0.4 of the dvb api ber should be a multiple
0390                of 10E-9 so we have to multiply the error count by
0391                10E9=1000000000 */
0392             numerator =
0393                 (u64) state->pre_vit_error_count * (u64) 1000000000;
0394             denominator = (u64) state->pre_vit_bit_count;
0395             state->ber = do_div(numerator, denominator);
0396         } else {
0397             state->ber = 0xffffffff;
0398         }
0399     }
0400 
0401     ret = af9005_get_post_vit_ber(fe, &state->post_vit_error_count,
0402                       &state->post_vit_bit_count,
0403                       &state->abort_count);
0404     if (ret == 0) {
0405         ret = af9005_reset_post_viterbi(fe);
0406         state->unc += state->abort_count;
0407         if (ret)
0408             return ret;
0409     }
0410     return 0;
0411 }
0412 
0413 static int af9005_fe_refresh_state(struct dvb_frontend *fe)
0414 {
0415     struct af9005_fe_state *state = fe->demodulator_priv;
0416     if (time_after(jiffies, state->next_status_check)) {
0417         deb_info("REFRESH STATE\n");
0418 
0419         /* statistics */
0420         if (af9005_get_statistic(fe))
0421             err("get_statistic_failed");
0422         state->next_status_check = jiffies + 250 * HZ / 1000;
0423     }
0424     return 0;
0425 }
0426 
0427 static int af9005_fe_read_status(struct dvb_frontend *fe,
0428                  enum fe_status *stat)
0429 {
0430     struct af9005_fe_state *state = fe->demodulator_priv;
0431     u8 temp;
0432     int ret;
0433 
0434     if (fe->ops.tuner_ops.release == NULL)
0435         return -ENODEV;
0436 
0437     *stat = 0;
0438     ret = af9005_read_register_bits(state->d, xd_p_agc_lock,
0439                     agc_lock_pos, agc_lock_len, &temp);
0440     if (ret)
0441         return ret;
0442     if (temp)
0443         *stat |= FE_HAS_SIGNAL;
0444 
0445     ret = af9005_read_register_bits(state->d, xd_p_fd_tpsd_lock,
0446                     fd_tpsd_lock_pos, fd_tpsd_lock_len,
0447                     &temp);
0448     if (ret)
0449         return ret;
0450     if (temp)
0451         *stat |= FE_HAS_CARRIER;
0452 
0453     ret = af9005_read_register_bits(state->d,
0454                     xd_r_mp2if_sync_byte_locked,
0455                     mp2if_sync_byte_locked_pos,
0456                     mp2if_sync_byte_locked_pos, &temp);
0457     if (ret)
0458         return ret;
0459     if (temp)
0460         *stat |= FE_HAS_SYNC | FE_HAS_VITERBI | FE_HAS_LOCK;
0461     if (state->opened)
0462         af9005_led_control(state->d, *stat & FE_HAS_LOCK);
0463 
0464     ret =
0465         af9005_read_register_bits(state->d, xd_p_reg_strong_sginal_detected,
0466                       reg_strong_sginal_detected_pos,
0467                       reg_strong_sginal_detected_len, &temp);
0468     if (ret)
0469         return ret;
0470     if (temp != state->strong) {
0471         deb_info("adjust for strong signal %d\n", temp);
0472         state->strong = temp;
0473     }
0474     return 0;
0475 }
0476 
0477 static int af9005_fe_read_ber(struct dvb_frontend *fe, u32 * ber)
0478 {
0479     struct af9005_fe_state *state = fe->demodulator_priv;
0480     if (fe->ops.tuner_ops.release  == NULL)
0481         return -ENODEV;
0482     af9005_fe_refresh_state(fe);
0483     *ber = state->ber;
0484     return 0;
0485 }
0486 
0487 static int af9005_fe_read_unc_blocks(struct dvb_frontend *fe, u32 * unc)
0488 {
0489     struct af9005_fe_state *state = fe->demodulator_priv;
0490     if (fe->ops.tuner_ops.release == NULL)
0491         return -ENODEV;
0492     af9005_fe_refresh_state(fe);
0493     *unc = state->unc;
0494     return 0;
0495 }
0496 
0497 static int af9005_fe_read_signal_strength(struct dvb_frontend *fe,
0498                       u16 * strength)
0499 {
0500     struct af9005_fe_state *state = fe->demodulator_priv;
0501     int ret;
0502     u8 if_gain, rf_gain;
0503 
0504     if (fe->ops.tuner_ops.release == NULL)
0505         return -ENODEV;
0506     ret =
0507         af9005_read_ofdm_register(state->d, xd_r_reg_aagc_rf_gain,
0508                       &rf_gain);
0509     if (ret)
0510         return ret;
0511     ret =
0512         af9005_read_ofdm_register(state->d, xd_r_reg_aagc_if_gain,
0513                       &if_gain);
0514     if (ret)
0515         return ret;
0516     /* this value has no real meaning, but i don't have the tables that relate
0517        the rf and if gain with the dbm, so I just scale the value */
0518     *strength = (512 - rf_gain - if_gain) << 7;
0519     return 0;
0520 }
0521 
0522 static int af9005_fe_read_snr(struct dvb_frontend *fe, u16 * snr)
0523 {
0524     /* the snr can be derived from the ber and the modulation
0525        but I don't think this kind of complex calculations belong
0526        in the driver. I may be wrong.... */
0527     return -ENOSYS;
0528 }
0529 
0530 static int af9005_fe_program_cfoe(struct dvb_usb_device *d, u32 bw)
0531 {
0532     u8 temp0, temp1, temp2, temp3, buf[4];
0533     int ret;
0534     u32 NS_coeff1_2048Nu;
0535     u32 NS_coeff1_8191Nu;
0536     u32 NS_coeff1_8192Nu;
0537     u32 NS_coeff1_8193Nu;
0538     u32 NS_coeff2_2k;
0539     u32 NS_coeff2_8k;
0540 
0541     switch (bw) {
0542     case 6000000:
0543         NS_coeff1_2048Nu = 0x2ADB6DC;
0544         NS_coeff1_8191Nu = 0xAB7313;
0545         NS_coeff1_8192Nu = 0xAB6DB7;
0546         NS_coeff1_8193Nu = 0xAB685C;
0547         NS_coeff2_2k = 0x156DB6E;
0548         NS_coeff2_8k = 0x55B6DC;
0549         break;
0550 
0551     case 7000000:
0552         NS_coeff1_2048Nu = 0x3200001;
0553         NS_coeff1_8191Nu = 0xC80640;
0554         NS_coeff1_8192Nu = 0xC80000;
0555         NS_coeff1_8193Nu = 0xC7F9C0;
0556         NS_coeff2_2k = 0x1900000;
0557         NS_coeff2_8k = 0x640000;
0558         break;
0559 
0560     case 8000000:
0561         NS_coeff1_2048Nu = 0x3924926;
0562         NS_coeff1_8191Nu = 0xE4996E;
0563         NS_coeff1_8192Nu = 0xE49249;
0564         NS_coeff1_8193Nu = 0xE48B25;
0565         NS_coeff2_2k = 0x1C92493;
0566         NS_coeff2_8k = 0x724925;
0567         break;
0568     default:
0569         err("Invalid bandwidth %d.", bw);
0570         return -EINVAL;
0571     }
0572 
0573     /*
0574      *  write NS_coeff1_2048Nu
0575      */
0576 
0577     temp0 = (u8) (NS_coeff1_2048Nu & 0x000000FF);
0578     temp1 = (u8) ((NS_coeff1_2048Nu & 0x0000FF00) >> 8);
0579     temp2 = (u8) ((NS_coeff1_2048Nu & 0x00FF0000) >> 16);
0580     temp3 = (u8) ((NS_coeff1_2048Nu & 0x03000000) >> 24);
0581 
0582     /*  big endian to make 8051 happy */
0583     buf[0] = temp3;
0584     buf[1] = temp2;
0585     buf[2] = temp1;
0586     buf[3] = temp0;
0587 
0588     /*  cfoe_NS_2k_coeff1_25_24 */
0589     ret = af9005_write_ofdm_register(d, 0xAE00, buf[0]);
0590     if (ret)
0591         return ret;
0592 
0593     /*  cfoe_NS_2k_coeff1_23_16 */
0594     ret = af9005_write_ofdm_register(d, 0xAE01, buf[1]);
0595     if (ret)
0596         return ret;
0597 
0598     /*  cfoe_NS_2k_coeff1_15_8 */
0599     ret = af9005_write_ofdm_register(d, 0xAE02, buf[2]);
0600     if (ret)
0601         return ret;
0602 
0603     /*  cfoe_NS_2k_coeff1_7_0 */
0604     ret = af9005_write_ofdm_register(d, 0xAE03, buf[3]);
0605     if (ret)
0606         return ret;
0607 
0608     /*
0609      *  write NS_coeff2_2k
0610      */
0611 
0612     temp0 = (u8) ((NS_coeff2_2k & 0x0000003F));
0613     temp1 = (u8) ((NS_coeff2_2k & 0x00003FC0) >> 6);
0614     temp2 = (u8) ((NS_coeff2_2k & 0x003FC000) >> 14);
0615     temp3 = (u8) ((NS_coeff2_2k & 0x01C00000) >> 22);
0616 
0617     /*  big endian to make 8051 happy */
0618     buf[0] = temp3;
0619     buf[1] = temp2;
0620     buf[2] = temp1;
0621     buf[3] = temp0;
0622 
0623     ret = af9005_write_ofdm_register(d, 0xAE04, buf[0]);
0624     if (ret)
0625         return ret;
0626 
0627     ret = af9005_write_ofdm_register(d, 0xAE05, buf[1]);
0628     if (ret)
0629         return ret;
0630 
0631     ret = af9005_write_ofdm_register(d, 0xAE06, buf[2]);
0632     if (ret)
0633         return ret;
0634 
0635     ret = af9005_write_ofdm_register(d, 0xAE07, buf[3]);
0636     if (ret)
0637         return ret;
0638 
0639     /*
0640      *  write NS_coeff1_8191Nu
0641      */
0642 
0643     temp0 = (u8) ((NS_coeff1_8191Nu & 0x000000FF));
0644     temp1 = (u8) ((NS_coeff1_8191Nu & 0x0000FF00) >> 8);
0645     temp2 = (u8) ((NS_coeff1_8191Nu & 0x00FFC000) >> 16);
0646     temp3 = (u8) ((NS_coeff1_8191Nu & 0x03000000) >> 24);
0647 
0648     /*  big endian to make 8051 happy */
0649     buf[0] = temp3;
0650     buf[1] = temp2;
0651     buf[2] = temp1;
0652     buf[3] = temp0;
0653 
0654     ret = af9005_write_ofdm_register(d, 0xAE08, buf[0]);
0655     if (ret)
0656         return ret;
0657 
0658     ret = af9005_write_ofdm_register(d, 0xAE09, buf[1]);
0659     if (ret)
0660         return ret;
0661 
0662     ret = af9005_write_ofdm_register(d, 0xAE0A, buf[2]);
0663     if (ret)
0664         return ret;
0665 
0666     ret = af9005_write_ofdm_register(d, 0xAE0B, buf[3]);
0667     if (ret)
0668         return ret;
0669 
0670     /*
0671      *  write NS_coeff1_8192Nu
0672      */
0673 
0674     temp0 = (u8) (NS_coeff1_8192Nu & 0x000000FF);
0675     temp1 = (u8) ((NS_coeff1_8192Nu & 0x0000FF00) >> 8);
0676     temp2 = (u8) ((NS_coeff1_8192Nu & 0x00FFC000) >> 16);
0677     temp3 = (u8) ((NS_coeff1_8192Nu & 0x03000000) >> 24);
0678 
0679     /*  big endian to make 8051 happy */
0680     buf[0] = temp3;
0681     buf[1] = temp2;
0682     buf[2] = temp1;
0683     buf[3] = temp0;
0684 
0685     ret = af9005_write_ofdm_register(d, 0xAE0C, buf[0]);
0686     if (ret)
0687         return ret;
0688 
0689     ret = af9005_write_ofdm_register(d, 0xAE0D, buf[1]);
0690     if (ret)
0691         return ret;
0692 
0693     ret = af9005_write_ofdm_register(d, 0xAE0E, buf[2]);
0694     if (ret)
0695         return ret;
0696 
0697     ret = af9005_write_ofdm_register(d, 0xAE0F, buf[3]);
0698     if (ret)
0699         return ret;
0700 
0701     /*
0702      *  write NS_coeff1_8193Nu
0703      */
0704 
0705     temp0 = (u8) ((NS_coeff1_8193Nu & 0x000000FF));
0706     temp1 = (u8) ((NS_coeff1_8193Nu & 0x0000FF00) >> 8);
0707     temp2 = (u8) ((NS_coeff1_8193Nu & 0x00FFC000) >> 16);
0708     temp3 = (u8) ((NS_coeff1_8193Nu & 0x03000000) >> 24);
0709 
0710     /*  big endian to make 8051 happy */
0711     buf[0] = temp3;
0712     buf[1] = temp2;
0713     buf[2] = temp1;
0714     buf[3] = temp0;
0715 
0716     ret = af9005_write_ofdm_register(d, 0xAE10, buf[0]);
0717     if (ret)
0718         return ret;
0719 
0720     ret = af9005_write_ofdm_register(d, 0xAE11, buf[1]);
0721     if (ret)
0722         return ret;
0723 
0724     ret = af9005_write_ofdm_register(d, 0xAE12, buf[2]);
0725     if (ret)
0726         return ret;
0727 
0728     ret = af9005_write_ofdm_register(d, 0xAE13, buf[3]);
0729     if (ret)
0730         return ret;
0731 
0732     /*
0733      *  write NS_coeff2_8k
0734      */
0735 
0736     temp0 = (u8) ((NS_coeff2_8k & 0x0000003F));
0737     temp1 = (u8) ((NS_coeff2_8k & 0x00003FC0) >> 6);
0738     temp2 = (u8) ((NS_coeff2_8k & 0x003FC000) >> 14);
0739     temp3 = (u8) ((NS_coeff2_8k & 0x01C00000) >> 22);
0740 
0741     /*  big endian to make 8051 happy */
0742     buf[0] = temp3;
0743     buf[1] = temp2;
0744     buf[2] = temp1;
0745     buf[3] = temp0;
0746 
0747     ret = af9005_write_ofdm_register(d, 0xAE14, buf[0]);
0748     if (ret)
0749         return ret;
0750 
0751     ret = af9005_write_ofdm_register(d, 0xAE15, buf[1]);
0752     if (ret)
0753         return ret;
0754 
0755     ret = af9005_write_ofdm_register(d, 0xAE16, buf[2]);
0756     if (ret)
0757         return ret;
0758 
0759     ret = af9005_write_ofdm_register(d, 0xAE17, buf[3]);
0760     return ret;
0761 
0762 }
0763 
0764 static int af9005_fe_select_bw(struct dvb_usb_device *d, u32 bw)
0765 {
0766     u8 temp;
0767     switch (bw) {
0768     case 6000000:
0769         temp = 0;
0770         break;
0771     case 7000000:
0772         temp = 1;
0773         break;
0774     case 8000000:
0775         temp = 2;
0776         break;
0777     default:
0778         err("Invalid bandwidth %d.", bw);
0779         return -EINVAL;
0780     }
0781     return af9005_write_register_bits(d, xd_g_reg_bw, reg_bw_pos,
0782                       reg_bw_len, temp);
0783 }
0784 
0785 static int af9005_fe_power(struct dvb_frontend *fe, int on)
0786 {
0787     struct af9005_fe_state *state = fe->demodulator_priv;
0788     u8 temp = on;
0789     int ret;
0790     deb_info("power %s tuner\n", on ? "on" : "off");
0791     ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
0792     return ret;
0793 }
0794 
0795 static struct mt2060_config af9005_mt2060_config = {
0796     0xC0
0797 };
0798 
0799 static struct qt1010_config af9005_qt1010_config = {
0800     0xC4
0801 };
0802 
0803 static int af9005_fe_init(struct dvb_frontend *fe)
0804 {
0805     struct af9005_fe_state *state = fe->demodulator_priv;
0806     struct dvb_usb_adapter *adap = fe->dvb->priv;
0807     int ret, i, scriptlen;
0808     u8 temp, temp0 = 0, temp1 = 0, temp2 = 0;
0809     u8 buf[2];
0810     u16 if1;
0811 
0812     deb_info("in af9005_fe_init\n");
0813 
0814     /* reset */
0815     deb_info("reset\n");
0816     if ((ret =
0817          af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst_en,
0818                     4, 1, 0x01)))
0819         return ret;
0820     if ((ret = af9005_write_ofdm_register(state->d, APO_REG_RESET, 0)))
0821         return ret;
0822     /* clear ofdm reset */
0823     deb_info("clear ofdm reset\n");
0824     for (i = 0; i < 150; i++) {
0825         if ((ret =
0826              af9005_read_ofdm_register(state->d,
0827                            xd_I2C_reg_ofdm_rst, &temp)))
0828             return ret;
0829         if (temp & (regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos))
0830             break;
0831         msleep(10);
0832     }
0833     if (i == 150)
0834         return -ETIMEDOUT;
0835 
0836     /*FIXME in the dump
0837        write B200 A9
0838        write xd_g_reg_ofsm_clk 7
0839        read eepr c6 (2)
0840        read eepr c7 (2)
0841        misc ctrl 3 -> 1
0842        read eepr ca (6)
0843        write xd_g_reg_ofsm_clk 0
0844        write B200 a1
0845      */
0846     ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa9);
0847     if (ret)
0848         return ret;
0849     ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x07);
0850     if (ret)
0851         return ret;
0852     temp = 0x01;
0853     ret = af9005_send_command(state->d, 0x03, &temp, 1, NULL, 0);
0854     if (ret)
0855         return ret;
0856     ret = af9005_write_ofdm_register(state->d, xd_g_reg_ofsm_clk, 0x00);
0857     if (ret)
0858         return ret;
0859     ret = af9005_write_ofdm_register(state->d, 0xb200, 0xa1);
0860     if (ret)
0861         return ret;
0862 
0863     temp = regmask[reg_ofdm_rst_len - 1] << reg_ofdm_rst_pos;
0864     if ((ret =
0865          af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
0866                     reg_ofdm_rst_pos, reg_ofdm_rst_len, 1)))
0867         return ret;
0868     ret = af9005_write_register_bits(state->d, xd_I2C_reg_ofdm_rst,
0869                      reg_ofdm_rst_pos, reg_ofdm_rst_len, 0);
0870 
0871     if (ret)
0872         return ret;
0873     /* don't know what register aefc is, but this is what the windows driver does */
0874     ret = af9005_write_ofdm_register(state->d, 0xaefc, 0);
0875     if (ret)
0876         return ret;
0877 
0878     /* set stand alone chip */
0879     deb_info("set stand alone chip\n");
0880     if ((ret =
0881          af9005_write_register_bits(state->d, xd_p_reg_dca_stand_alone,
0882                     reg_dca_stand_alone_pos,
0883                     reg_dca_stand_alone_len, 1)))
0884         return ret;
0885 
0886     /* set dca upper & lower chip */
0887     deb_info("set dca upper & lower chip\n");
0888     if ((ret =
0889          af9005_write_register_bits(state->d, xd_p_reg_dca_upper_chip,
0890                     reg_dca_upper_chip_pos,
0891                     reg_dca_upper_chip_len, 0)))
0892         return ret;
0893     if ((ret =
0894          af9005_write_register_bits(state->d, xd_p_reg_dca_lower_chip,
0895                     reg_dca_lower_chip_pos,
0896                     reg_dca_lower_chip_len, 0)))
0897         return ret;
0898 
0899     /* set 2wire master clock to 0x14 (for 60KHz) */
0900     deb_info("set 2wire master clock to 0x14 (for 60KHz)\n");
0901     if ((ret =
0902          af9005_write_ofdm_register(state->d, xd_I2C_i2c_m_period, 0x14)))
0903         return ret;
0904 
0905     /* clear dca enable chip */
0906     deb_info("clear dca enable chip\n");
0907     if ((ret =
0908          af9005_write_register_bits(state->d, xd_p_reg_dca_en,
0909                     reg_dca_en_pos, reg_dca_en_len, 0)))
0910         return ret;
0911     /* FIXME these are register bits, but I don't know which ones */
0912     ret = af9005_write_ofdm_register(state->d, 0xa16c, 1);
0913     if (ret)
0914         return ret;
0915     ret = af9005_write_ofdm_register(state->d, 0xa3c1, 0);
0916     if (ret)
0917         return ret;
0918 
0919     /* init other parameters: program cfoe and select bandwidth */
0920     deb_info("program cfoe\n");
0921     ret = af9005_fe_program_cfoe(state->d, 6000000);
0922     if (ret)
0923         return ret;
0924     /* set read-update bit for modulation */
0925     deb_info("set read-update bit for modulation\n");
0926     if ((ret =
0927          af9005_write_register_bits(state->d, xd_p_reg_feq_read_update,
0928                     reg_feq_read_update_pos,
0929                     reg_feq_read_update_len, 1)))
0930         return ret;
0931 
0932     /* sample code has a set MPEG TS code here
0933        but sniffing reveals that it doesn't do it */
0934 
0935     /* set read-update bit to 1 for DCA modulation */
0936     deb_info("set read-update bit 1 for DCA modulation\n");
0937     if ((ret =
0938          af9005_write_register_bits(state->d, xd_p_reg_dca_read_update,
0939                     reg_dca_read_update_pos,
0940                     reg_dca_read_update_len, 1)))
0941         return ret;
0942 
0943     /* enable fec monitor */
0944     deb_info("enable fec monitor\n");
0945     if ((ret =
0946          af9005_write_register_bits(state->d, xd_p_fec_vtb_rsd_mon_en,
0947                     fec_vtb_rsd_mon_en_pos,
0948                     fec_vtb_rsd_mon_en_len, 1)))
0949         return ret;
0950 
0951     /* FIXME should be register bits, I don't know which ones */
0952     ret = af9005_write_ofdm_register(state->d, 0xa601, 0);
0953 
0954     /* set api_retrain_never_freeze */
0955     deb_info("set api_retrain_never_freeze\n");
0956     if ((ret = af9005_write_ofdm_register(state->d, 0xaefb, 0x01)))
0957         return ret;
0958 
0959     /* load init script */
0960     deb_info("load init script\n");
0961     scriptlen = sizeof(script) / sizeof(RegDesc);
0962     for (i = 0; i < scriptlen; i++) {
0963         if ((ret =
0964              af9005_write_register_bits(state->d, script[i].reg,
0965                         script[i].pos,
0966                         script[i].len, script[i].val)))
0967             return ret;
0968         /* save 3 bytes of original fcw */
0969         if (script[i].reg == 0xae18)
0970             temp2 = script[i].val;
0971         if (script[i].reg == 0xae19)
0972             temp1 = script[i].val;
0973         if (script[i].reg == 0xae1a)
0974             temp0 = script[i].val;
0975 
0976         /* save original unplug threshold */
0977         if (script[i].reg == xd_p_reg_unplug_th)
0978             state->original_if_unplug_th = script[i].val;
0979         if (script[i].reg == xd_p_reg_unplug_rf_gain_th)
0980             state->original_rf_unplug_th = script[i].val;
0981         if (script[i].reg == xd_p_reg_unplug_dtop_if_gain_th)
0982             state->original_dtop_if_unplug_th = script[i].val;
0983         if (script[i].reg == xd_p_reg_unplug_dtop_rf_gain_th)
0984             state->original_dtop_rf_unplug_th = script[i].val;
0985 
0986     }
0987     state->original_fcw =
0988         ((u32) temp2 << 16) + ((u32) temp1 << 8) + (u32) temp0;
0989 
0990 
0991     /* save original TOPs */
0992     deb_info("save original TOPs\n");
0993 
0994     /*  RF TOP */
0995     ret =
0996         af9005_read_word_agc(state->d,
0997                  xd_p_reg_aagc_rf_top_numerator_9_8,
0998                  xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
0999                  &state->original_rf_top);
1000     if (ret)
1001         return ret;
1002 
1003     /*  IF TOP */
1004     ret =
1005         af9005_read_word_agc(state->d,
1006                  xd_p_reg_aagc_if_top_numerator_9_8,
1007                  xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1008                  &state->original_if_top);
1009     if (ret)
1010         return ret;
1011 
1012     /*  ACI 0 IF TOP */
1013     ret =
1014         af9005_read_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1015                  &state->original_aci0_if_top);
1016     if (ret)
1017         return ret;
1018 
1019     /*  ACI 1 IF TOP */
1020     ret =
1021         af9005_read_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1022                  &state->original_aci1_if_top);
1023     if (ret)
1024         return ret;
1025 
1026     /* attach tuner and init */
1027     if (fe->ops.tuner_ops.release == NULL) {
1028         /* read tuner and board id from eeprom */
1029         ret = af9005_read_eeprom(adap->dev, 0xc6, buf, 2);
1030         if (ret) {
1031             err("Impossible to read EEPROM\n");
1032             return ret;
1033         }
1034         deb_info("Tuner id %d, board id %d\n", buf[0], buf[1]);
1035         switch (buf[0]) {
1036         case 2: /* MT2060 */
1037             /* read if1 from eeprom */
1038             ret = af9005_read_eeprom(adap->dev, 0xc8, buf, 2);
1039             if (ret) {
1040                 err("Impossible to read EEPROM\n");
1041                 return ret;
1042             }
1043             if1 = (u16) (buf[0] << 8) + buf[1];
1044             if (dvb_attach(mt2060_attach, fe, &adap->dev->i2c_adap,
1045                      &af9005_mt2060_config, if1) == NULL) {
1046                 deb_info("MT2060 attach failed\n");
1047                 return -ENODEV;
1048             }
1049             break;
1050         case 3: /* QT1010 */
1051         case 9: /* QT1010B */
1052             if (dvb_attach(qt1010_attach, fe, &adap->dev->i2c_adap,
1053                     &af9005_qt1010_config) ==NULL) {
1054                 deb_info("QT1010 attach failed\n");
1055                 return -ENODEV;
1056             }
1057             break;
1058         default:
1059             err("Unsupported tuner type %d", buf[0]);
1060             return -ENODEV;
1061         }
1062         ret = fe->ops.tuner_ops.init(fe);
1063         if (ret)
1064             return ret;
1065     }
1066 
1067     deb_info("profit!\n");
1068     return 0;
1069 }
1070 
1071 static int af9005_fe_sleep(struct dvb_frontend *fe)
1072 {
1073     return af9005_fe_power(fe, 0);
1074 }
1075 
1076 static int af9005_ts_bus_ctrl(struct dvb_frontend *fe, int acquire)
1077 {
1078     struct af9005_fe_state *state = fe->demodulator_priv;
1079 
1080     if (acquire) {
1081         state->opened++;
1082     } else {
1083 
1084         state->opened--;
1085         if (!state->opened)
1086             af9005_led_control(state->d, 0);
1087     }
1088     return 0;
1089 }
1090 
1091 static int af9005_fe_set_frontend(struct dvb_frontend *fe)
1092 {
1093     struct dtv_frontend_properties *fep = &fe->dtv_property_cache;
1094     struct af9005_fe_state *state = fe->demodulator_priv;
1095     int ret;
1096     u8 temp, temp0, temp1, temp2;
1097 
1098     deb_info("af9005_fe_set_frontend freq %d bw %d\n", fep->frequency,
1099          fep->bandwidth_hz);
1100     if (fe->ops.tuner_ops.release == NULL) {
1101         err("Tuner not attached");
1102         return -ENODEV;
1103     }
1104 
1105     deb_info("turn off led\n");
1106     /* not in the log */
1107     ret = af9005_led_control(state->d, 0);
1108     if (ret)
1109         return ret;
1110     /* not sure about the bits */
1111     ret = af9005_write_register_bits(state->d, XD_MP2IF_MISC, 2, 1, 0);
1112     if (ret)
1113         return ret;
1114 
1115     /* set FCW to default value */
1116     deb_info("set FCW to default value\n");
1117     temp0 = (u8) (state->original_fcw & 0x000000ff);
1118     temp1 = (u8) ((state->original_fcw & 0x0000ff00) >> 8);
1119     temp2 = (u8) ((state->original_fcw & 0x00ff0000) >> 16);
1120     ret = af9005_write_ofdm_register(state->d, 0xae1a, temp0);
1121     if (ret)
1122         return ret;
1123     ret = af9005_write_ofdm_register(state->d, 0xae19, temp1);
1124     if (ret)
1125         return ret;
1126     ret = af9005_write_ofdm_register(state->d, 0xae18, temp2);
1127     if (ret)
1128         return ret;
1129 
1130     /* restore original TOPs */
1131     deb_info("restore original TOPs\n");
1132     ret =
1133         af9005_write_word_agc(state->d,
1134                   xd_p_reg_aagc_rf_top_numerator_9_8,
1135                   xd_p_reg_aagc_rf_top_numerator_7_0, 0, 2,
1136                   state->original_rf_top);
1137     if (ret)
1138         return ret;
1139     ret =
1140         af9005_write_word_agc(state->d,
1141                   xd_p_reg_aagc_if_top_numerator_9_8,
1142                   xd_p_reg_aagc_if_top_numerator_7_0, 0, 2,
1143                   state->original_if_top);
1144     if (ret)
1145         return ret;
1146     ret =
1147         af9005_write_word_agc(state->d, 0xA60E, 0xA60A, 4, 2,
1148                   state->original_aci0_if_top);
1149     if (ret)
1150         return ret;
1151     ret =
1152         af9005_write_word_agc(state->d, 0xA60E, 0xA60B, 6, 2,
1153                   state->original_aci1_if_top);
1154     if (ret)
1155         return ret;
1156 
1157     /* select bandwidth */
1158     deb_info("select bandwidth");
1159     ret = af9005_fe_select_bw(state->d, fep->bandwidth_hz);
1160     if (ret)
1161         return ret;
1162     ret = af9005_fe_program_cfoe(state->d, fep->bandwidth_hz);
1163     if (ret)
1164         return ret;
1165 
1166     /* clear easy mode flag */
1167     deb_info("clear easy mode flag\n");
1168     ret = af9005_write_ofdm_register(state->d, 0xaefd, 0);
1169     if (ret)
1170         return ret;
1171 
1172     /* set unplug threshold to original value */
1173     deb_info("set unplug threshold to original value\n");
1174     ret =
1175         af9005_write_ofdm_register(state->d, xd_p_reg_unplug_th,
1176                        state->original_if_unplug_th);
1177     if (ret)
1178         return ret;
1179     /* set tuner */
1180     deb_info("set tuner\n");
1181     ret = fe->ops.tuner_ops.set_params(fe);
1182     if (ret)
1183         return ret;
1184 
1185     /* trigger ofsm */
1186     deb_info("trigger ofsm\n");
1187     temp = 0;
1188     ret = af9005_write_tuner_registers(state->d, 0xffff, &temp, 1);
1189     if (ret)
1190         return ret;
1191 
1192     /* clear retrain and freeze flag */
1193     deb_info("clear retrain and freeze flag\n");
1194     ret =
1195         af9005_write_register_bits(state->d,
1196                        xd_p_reg_api_retrain_request,
1197                        reg_api_retrain_request_pos, 2, 0);
1198     if (ret)
1199         return ret;
1200 
1201     /* reset pre viterbi and post viterbi registers and statistics */
1202     af9005_reset_pre_viterbi(fe);
1203     af9005_reset_post_viterbi(fe);
1204     state->pre_vit_error_count = 0;
1205     state->pre_vit_bit_count = 0;
1206     state->ber = 0;
1207     state->post_vit_error_count = 0;
1208     /* state->unc = 0; commented out since it should be ever increasing */
1209     state->abort_count = 0;
1210 
1211     state->next_status_check = jiffies;
1212     state->strong = -1;
1213 
1214     return 0;
1215 }
1216 
1217 static int af9005_fe_get_frontend(struct dvb_frontend *fe,
1218                   struct dtv_frontend_properties *fep)
1219 {
1220     struct af9005_fe_state *state = fe->demodulator_priv;
1221     int ret;
1222     u8 temp;
1223 
1224     /* mode */
1225     ret =
1226         af9005_read_register_bits(state->d, xd_g_reg_tpsd_const,
1227                       reg_tpsd_const_pos, reg_tpsd_const_len,
1228                       &temp);
1229     if (ret)
1230         return ret;
1231     deb_info("===== fe_get_frontend_legacy = =============\n");
1232     deb_info("CONSTELLATION ");
1233     switch (temp) {
1234     case 0:
1235         fep->modulation = QPSK;
1236         deb_info("QPSK\n");
1237         break;
1238     case 1:
1239         fep->modulation = QAM_16;
1240         deb_info("QAM_16\n");
1241         break;
1242     case 2:
1243         fep->modulation = QAM_64;
1244         deb_info("QAM_64\n");
1245         break;
1246     }
1247 
1248     /* tps hierarchy and alpha value */
1249     ret =
1250         af9005_read_register_bits(state->d, xd_g_reg_tpsd_hier,
1251                       reg_tpsd_hier_pos, reg_tpsd_hier_len,
1252                       &temp);
1253     if (ret)
1254         return ret;
1255     deb_info("HIERARCHY ");
1256     switch (temp) {
1257     case 0:
1258         fep->hierarchy = HIERARCHY_NONE;
1259         deb_info("NONE\n");
1260         break;
1261     case 1:
1262         fep->hierarchy = HIERARCHY_1;
1263         deb_info("1\n");
1264         break;
1265     case 2:
1266         fep->hierarchy = HIERARCHY_2;
1267         deb_info("2\n");
1268         break;
1269     case 3:
1270         fep->hierarchy = HIERARCHY_4;
1271         deb_info("4\n");
1272         break;
1273     }
1274 
1275     /*  high/low priority     */
1276     ret =
1277         af9005_read_register_bits(state->d, xd_g_reg_dec_pri,
1278                       reg_dec_pri_pos, reg_dec_pri_len, &temp);
1279     if (ret)
1280         return ret;
1281     /* if temp is set = high priority */
1282     deb_info("PRIORITY %s\n", temp ? "high" : "low");
1283 
1284     /* high coderate */
1285     ret =
1286         af9005_read_register_bits(state->d, xd_g_reg_tpsd_hpcr,
1287                       reg_tpsd_hpcr_pos, reg_tpsd_hpcr_len,
1288                       &temp);
1289     if (ret)
1290         return ret;
1291     deb_info("CODERATE HP ");
1292     switch (temp) {
1293     case 0:
1294         fep->code_rate_HP = FEC_1_2;
1295         deb_info("FEC_1_2\n");
1296         break;
1297     case 1:
1298         fep->code_rate_HP = FEC_2_3;
1299         deb_info("FEC_2_3\n");
1300         break;
1301     case 2:
1302         fep->code_rate_HP = FEC_3_4;
1303         deb_info("FEC_3_4\n");
1304         break;
1305     case 3:
1306         fep->code_rate_HP = FEC_5_6;
1307         deb_info("FEC_5_6\n");
1308         break;
1309     case 4:
1310         fep->code_rate_HP = FEC_7_8;
1311         deb_info("FEC_7_8\n");
1312         break;
1313     }
1314 
1315     /* low coderate */
1316     ret =
1317         af9005_read_register_bits(state->d, xd_g_reg_tpsd_lpcr,
1318                       reg_tpsd_lpcr_pos, reg_tpsd_lpcr_len,
1319                       &temp);
1320     if (ret)
1321         return ret;
1322     deb_info("CODERATE LP ");
1323     switch (temp) {
1324     case 0:
1325         fep->code_rate_LP = FEC_1_2;
1326         deb_info("FEC_1_2\n");
1327         break;
1328     case 1:
1329         fep->code_rate_LP = FEC_2_3;
1330         deb_info("FEC_2_3\n");
1331         break;
1332     case 2:
1333         fep->code_rate_LP = FEC_3_4;
1334         deb_info("FEC_3_4\n");
1335         break;
1336     case 3:
1337         fep->code_rate_LP = FEC_5_6;
1338         deb_info("FEC_5_6\n");
1339         break;
1340     case 4:
1341         fep->code_rate_LP = FEC_7_8;
1342         deb_info("FEC_7_8\n");
1343         break;
1344     }
1345 
1346     /* guard interval */
1347     ret =
1348         af9005_read_register_bits(state->d, xd_g_reg_tpsd_gi,
1349                       reg_tpsd_gi_pos, reg_tpsd_gi_len, &temp);
1350     if (ret)
1351         return ret;
1352     deb_info("GUARD INTERVAL ");
1353     switch (temp) {
1354     case 0:
1355         fep->guard_interval = GUARD_INTERVAL_1_32;
1356         deb_info("1_32\n");
1357         break;
1358     case 1:
1359         fep->guard_interval = GUARD_INTERVAL_1_16;
1360         deb_info("1_16\n");
1361         break;
1362     case 2:
1363         fep->guard_interval = GUARD_INTERVAL_1_8;
1364         deb_info("1_8\n");
1365         break;
1366     case 3:
1367         fep->guard_interval = GUARD_INTERVAL_1_4;
1368         deb_info("1_4\n");
1369         break;
1370     }
1371 
1372     /* fft */
1373     ret =
1374         af9005_read_register_bits(state->d, xd_g_reg_tpsd_txmod,
1375                       reg_tpsd_txmod_pos, reg_tpsd_txmod_len,
1376                       &temp);
1377     if (ret)
1378         return ret;
1379     deb_info("TRANSMISSION MODE ");
1380     switch (temp) {
1381     case 0:
1382         fep->transmission_mode = TRANSMISSION_MODE_2K;
1383         deb_info("2K\n");
1384         break;
1385     case 1:
1386         fep->transmission_mode = TRANSMISSION_MODE_8K;
1387         deb_info("8K\n");
1388         break;
1389     }
1390 
1391     /* bandwidth      */
1392     ret =
1393         af9005_read_register_bits(state->d, xd_g_reg_bw, reg_bw_pos,
1394                       reg_bw_len, &temp);
1395     deb_info("BANDWIDTH ");
1396     switch (temp) {
1397     case 0:
1398         fep->bandwidth_hz = 6000000;
1399         deb_info("6\n");
1400         break;
1401     case 1:
1402         fep->bandwidth_hz = 7000000;
1403         deb_info("7\n");
1404         break;
1405     case 2:
1406         fep->bandwidth_hz = 8000000;
1407         deb_info("8\n");
1408         break;
1409     }
1410     return 0;
1411 }
1412 
1413 static void af9005_fe_release(struct dvb_frontend *fe)
1414 {
1415     struct af9005_fe_state *state =
1416         (struct af9005_fe_state *)fe->demodulator_priv;
1417     kfree(state);
1418 }
1419 
1420 static const struct dvb_frontend_ops af9005_fe_ops;
1421 
1422 struct dvb_frontend *af9005_fe_attach(struct dvb_usb_device *d)
1423 {
1424     struct af9005_fe_state *state = NULL;
1425 
1426     /* allocate memory for the internal state */
1427     state = kzalloc(sizeof(struct af9005_fe_state), GFP_KERNEL);
1428     if (state == NULL)
1429         goto error;
1430 
1431     deb_info("attaching frontend af9005\n");
1432 
1433     state->d = d;
1434     state->opened = 0;
1435 
1436     memcpy(&state->frontend.ops, &af9005_fe_ops,
1437            sizeof(struct dvb_frontend_ops));
1438     state->frontend.demodulator_priv = state;
1439 
1440     return &state->frontend;
1441       error:
1442     return NULL;
1443 }
1444 
1445 static const struct dvb_frontend_ops af9005_fe_ops = {
1446     .delsys = { SYS_DVBT },
1447     .info = {
1448          .name = "AF9005 USB DVB-T",
1449          .frequency_min_hz =    44250 * kHz,
1450          .frequency_max_hz =   867250 * kHz,
1451          .frequency_stepsize_hz = 250 * kHz,
1452          .caps = FE_CAN_INVERSION_AUTO |
1453          FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
1454          FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
1455          FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
1456          FE_CAN_QAM_AUTO | FE_CAN_TRANSMISSION_MODE_AUTO |
1457          FE_CAN_GUARD_INTERVAL_AUTO | FE_CAN_RECOVER |
1458          FE_CAN_HIERARCHY_AUTO,
1459          },
1460 
1461     .release = af9005_fe_release,
1462 
1463     .init = af9005_fe_init,
1464     .sleep = af9005_fe_sleep,
1465     .ts_bus_ctrl = af9005_ts_bus_ctrl,
1466 
1467     .set_frontend = af9005_fe_set_frontend,
1468     .get_frontend = af9005_fe_get_frontend,
1469 
1470     .read_status = af9005_fe_read_status,
1471     .read_ber = af9005_fe_read_ber,
1472     .read_signal_strength = af9005_fe_read_signal_strength,
1473     .read_snr = af9005_fe_read_snr,
1474     .read_ucblocks = af9005_fe_read_unc_blocks,
1475 };
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