usb/dvb-usb-v2/mxl111sf-phy.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  mxl111sf-phy.c - driver for the MaxLinear MXL111SF
0004  *
0005  *  Copyright (C) 2010-2014 Michael Krufky <mkrufky@linuxtv.org>
0006  */
0007
0008 #include "mxl111sf-phy.h"
0009 #include "mxl111sf-reg.h"
0010
0011 int mxl111sf_init_tuner_demod(struct mxl111sf_state *state)
0012 {
0013     struct mxl111sf_reg_ctrl_info mxl_111_overwrite_default[] = {
0014         {0x07, 0xff, 0x0c},
0015         {0x58, 0xff, 0x9d},
0016         {0x09, 0xff, 0x00},
0017         {0x06, 0xff, 0x06},
0018         {0xc8, 0xff, 0x40}, /* ED_LE_WIN_OLD = 0 */
0019         {0x8d, 0x01, 0x01}, /* NEGATE_Q */
0020         {0x32, 0xff, 0xac}, /* DIG_RFREFSELECT = 12 */
0021         {0x42, 0xff, 0x43}, /* DIG_REG_AMP = 4 */
0022         {0x74, 0xff, 0xc4}, /* SSPUR_FS_PRIO = 4 */
0023         {0x71, 0xff, 0xe6}, /* SPUR_ROT_PRIO_VAL = 1 */
0024         {0x83, 0xff, 0x64}, /* INF_FILT1_THD_SC = 100 */
0025         {0x85, 0xff, 0x64}, /* INF_FILT2_THD_SC = 100 */
0026         {0x88, 0xff, 0xf0}, /* INF_THD = 240 */
0027         {0x6f, 0xf0, 0xb0}, /* DFE_DLY = 11 */
0028         {0x00, 0xff, 0x01}, /* Change to page 1 */
0029         {0x81, 0xff, 0x11}, /* DSM_FERR_BYPASS = 1 */
0030         {0xf4, 0xff, 0x07}, /* DIG_FREQ_CORR = 1 */
0031         {0xd4, 0x1f, 0x0f}, /* SPUR_TEST_NOISE_TH = 15 */
0032         {0xd6, 0xff, 0x0c}, /* SPUR_TEST_NOISE_PAPR = 12 */
0033         {0x00, 0xff, 0x00}, /* Change to page 0 */
0034         {0,    0,    0}
0035     };
0036
0037     mxl_debug("()");
0038
0039     return mxl111sf_ctrl_program_regs(state, mxl_111_overwrite_default);
0040 }
0041
0042 int mxl1x1sf_soft_reset(struct mxl111sf_state *state)
0043 {
0044     int ret;
0045     mxl_debug("()");
0046
0047     ret = mxl111sf_write_reg(state, 0xff, 0x00); /* AIC */
0048     if (mxl_fail(ret))
0049         goto fail;
0050     ret = mxl111sf_write_reg(state, 0x02, 0x01); /* get out of reset */
0051     mxl_fail(ret);
0052 fail:
0053     return ret;
0054 }
0055
0056 int mxl1x1sf_set_device_mode(struct mxl111sf_state *state, int mode)
0057 {
0058     int ret;
0059
0060     mxl_debug("(%s)", MXL_SOC_MODE == mode ?
0061         "MXL_SOC_MODE" : "MXL_TUNER_MODE");
0062
0063     /* set device mode */
0064     ret = mxl111sf_write_reg(state, 0x03,
0065                  MXL_SOC_MODE == mode ? 0x01 : 0x00);
0066     if (mxl_fail(ret))
0067         goto fail;
0068
0069     ret = mxl111sf_write_reg_mask(state,
0070                       0x7d, 0x40, MXL_SOC_MODE == mode ?
0071                       0x00 : /* enable impulse noise filter,
0072                         INF_BYP = 0 */
0073                       0x40); /* disable impulse noise filter,
0074                         INF_BYP = 1 */
0075     if (mxl_fail(ret))
0076         goto fail;
0077
0078     state->device_mode = mode;
0079 fail:
0080     return ret;
0081 }
0082
0083 /* power up tuner */
0084 int mxl1x1sf_top_master_ctrl(struct mxl111sf_state *state, int onoff)
0085 {
0086     mxl_debug("(%d)", onoff);
0087
0088     return mxl111sf_write_reg(state, 0x01, onoff ? 0x01 : 0x00);
0089 }
0090
0091 int mxl111sf_disable_656_port(struct mxl111sf_state *state)
0092 {
0093     mxl_debug("()");
0094
0095     return mxl111sf_write_reg_mask(state, 0x12, 0x04, 0x00);
0096 }
0097
0098 int mxl111sf_enable_usb_output(struct mxl111sf_state *state)
0099 {
0100     mxl_debug("()");
0101
0102     return mxl111sf_write_reg_mask(state, 0x17, 0x40, 0x00);
0103 }
0104
0105 /* initialize TSIF as input port of MxL1X1SF for MPEG2 data transfer */
0106 int mxl111sf_config_mpeg_in(struct mxl111sf_state *state,
0107                 unsigned int parallel_serial,
0108                 unsigned int msb_lsb_1st,
0109                 unsigned int clock_phase,
0110                 unsigned int mpeg_valid_pol,
0111                 unsigned int mpeg_sync_pol)
0112 {
0113     int ret;
0114     u8 mode, tmp;
0115
0116     mxl_debug("(%u,%u,%u,%u,%u)", parallel_serial, msb_lsb_1st,
0117           clock_phase, mpeg_valid_pol, mpeg_sync_pol);
0118
0119     /* Enable PIN MUX */
0120     ret = mxl111sf_write_reg(state, V6_PIN_MUX_MODE_REG, V6_ENABLE_PIN_MUX);
0121     mxl_fail(ret);
0122
0123     /* Configure MPEG Clock phase */
0124     mxl111sf_read_reg(state, V6_MPEG_IN_CLK_INV_REG, &mode);
0125
0126     if (clock_phase == TSIF_NORMAL)
0127         mode &= ~V6_INVERTED_CLK_PHASE;
0128     else
0129         mode |= V6_INVERTED_CLK_PHASE;
0130
0131     ret = mxl111sf_write_reg(state, V6_MPEG_IN_CLK_INV_REG, mode);
0132     mxl_fail(ret);
0133
0134     /* Configure data input mode, MPEG Valid polarity, MPEG Sync polarity
0135      * Get current configuration */
0136     ret = mxl111sf_read_reg(state, V6_MPEG_IN_CTRL_REG, &mode);
0137     mxl_fail(ret);
0138
0139     /* Data Input mode */
0140     if (parallel_serial == TSIF_INPUT_PARALLEL) {
0141         /* Disable serial mode */
0142         mode &= ~V6_MPEG_IN_DATA_SERIAL;
0143
0144         /* Enable Parallel mode */
0145         mode |= V6_MPEG_IN_DATA_PARALLEL;
0146     } else {
0147         /* Disable Parallel mode */
0148         mode &= ~V6_MPEG_IN_DATA_PARALLEL;
0149
0150         /* Enable Serial Mode */
0151         mode |= V6_MPEG_IN_DATA_SERIAL;
0152
0153         /* If serial interface is chosen, configure
0154            MSB or LSB order in transmission */
0155         ret = mxl111sf_read_reg(state,
0156                     V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
0157                     &tmp);
0158         mxl_fail(ret);
0159
0160         if (msb_lsb_1st == MPEG_SER_MSB_FIRST_ENABLED)
0161             tmp |= V6_MPEG_SER_MSB_FIRST;
0162         else
0163             tmp &= ~V6_MPEG_SER_MSB_FIRST;
0164
0165         ret = mxl111sf_write_reg(state,
0166                      V6_MPEG_INOUT_BIT_ORDER_CTRL_REG,
0167                      tmp);
0168         mxl_fail(ret);
0169     }
0170
0171     /* MPEG Sync polarity */
0172     if (mpeg_sync_pol == TSIF_NORMAL)
0173         mode &= ~V6_INVERTED_MPEG_SYNC;
0174     else
0175         mode |= V6_INVERTED_MPEG_SYNC;
0176
0177     /* MPEG Valid polarity */
0178     if (mpeg_valid_pol == 0)
0179         mode &= ~V6_INVERTED_MPEG_VALID;
0180     else
0181         mode |= V6_INVERTED_MPEG_VALID;
0182
0183     ret = mxl111sf_write_reg(state, V6_MPEG_IN_CTRL_REG, mode);
0184     mxl_fail(ret);
0185
0186     return ret;
0187 }
0188
0189 int mxl111sf_init_i2s_port(struct mxl111sf_state *state, u8 sample_size)
0190 {
0191     static struct mxl111sf_reg_ctrl_info init_i2s[] = {
0192         {0x1b, 0xff, 0x1e}, /* pin mux mode, Choose 656/I2S input */
0193         {0x15, 0x60, 0x60}, /* Enable I2S */
0194         {0x17, 0xe0, 0x20}, /* Input, MPEG MODE USB,
0195                        Inverted 656 Clock, I2S_SOFT_RESET,
0196                        0 : Normal operation, 1 : Reset State */
0197 #if 0
0198         {0x12, 0x01, 0x00}, /* AUDIO_IRQ_CLR (Overflow Indicator) */
0199 #endif
0200         {0x00, 0xff, 0x02}, /* Change to Control Page */
0201         {0x26, 0x0d, 0x0d}, /* I2S_MODE & BT656_SRC_SEL for FPGA only */
0202         {0x00, 0xff, 0x00},
0203         {0,    0,    0}
0204     };
0205     int ret;
0206
0207     mxl_debug("(0x%02x)", sample_size);
0208
0209     ret = mxl111sf_ctrl_program_regs(state, init_i2s);
0210     if (mxl_fail(ret))
0211         goto fail;
0212
0213     ret = mxl111sf_write_reg(state, V6_I2S_NUM_SAMPLES_REG, sample_size);
0214     mxl_fail(ret);
0215 fail:
0216     return ret;
0217 }
0218
0219 int mxl111sf_disable_i2s_port(struct mxl111sf_state *state)
0220 {
0221     static struct mxl111sf_reg_ctrl_info disable_i2s[] = {
0222         {0x15, 0x40, 0x00},
0223         {0,    0,    0}
0224     };
0225
0226     mxl_debug("()");
0227
0228     return mxl111sf_ctrl_program_regs(state, disable_i2s);
0229 }
0230
0231 int mxl111sf_config_i2s(struct mxl111sf_state *state,
0232             u8 msb_start_pos, u8 data_width)
0233 {
0234     int ret;
0235     u8 tmp;
0236
0237     mxl_debug("(0x%02x, 0x%02x)", msb_start_pos, data_width);
0238
0239     ret = mxl111sf_read_reg(state, V6_I2S_STREAM_START_BIT_REG, &tmp);
0240     if (mxl_fail(ret))
0241         goto fail;
0242
0243     tmp &= 0xe0;
0244     tmp |= msb_start_pos;
0245     ret = mxl111sf_write_reg(state, V6_I2S_STREAM_START_BIT_REG, tmp);
0246     if (mxl_fail(ret))
0247         goto fail;
0248
0249     ret = mxl111sf_read_reg(state, V6_I2S_STREAM_END_BIT_REG, &tmp);
0250     if (mxl_fail(ret))
0251         goto fail;
0252
0253     tmp &= 0xe0;
0254     tmp |= data_width;
0255     ret = mxl111sf_write_reg(state, V6_I2S_STREAM_END_BIT_REG, tmp);
0256     mxl_fail(ret);
0257 fail:
0258     return ret;
0259 }
0260
0261 int mxl111sf_config_spi(struct mxl111sf_state *state, int onoff)
0262 {
0263     u8 val;
0264     int ret;
0265
0266     mxl_debug("(%d)", onoff);
0267
0268     ret = mxl111sf_write_reg(state, 0x00, 0x02);
0269     if (mxl_fail(ret))
0270         goto fail;
0271
0272     ret = mxl111sf_read_reg(state, V8_SPI_MODE_REG, &val);
0273     if (mxl_fail(ret))
0274         goto fail;
0275
0276     if (onoff)
0277         val |= 0x04;
0278     else
0279         val &= ~0x04;
0280
0281     ret = mxl111sf_write_reg(state, V8_SPI_MODE_REG, val);
0282     if (mxl_fail(ret))
0283         goto fail;
0284
0285     ret = mxl111sf_write_reg(state, 0x00, 0x00);
0286     mxl_fail(ret);
0287 fail:
0288     return ret;
0289 }
0290
0291 int mxl111sf_idac_config(struct mxl111sf_state *state,
0292              u8 control_mode, u8 current_setting,
0293              u8 current_value, u8 hysteresis_value)
0294 {
0295     int ret;
0296     u8 val;
0297     /* current value will be set for both automatic & manual IDAC control */
0298     val = current_value;
0299
0300     if (control_mode == IDAC_MANUAL_CONTROL) {
0301         /* enable manual control of IDAC */
0302         val |= IDAC_MANUAL_CONTROL_BIT_MASK;
0303
0304         if (current_setting == IDAC_CURRENT_SINKING_ENABLE)
0305             /* enable current sinking in manual mode */
0306             val |= IDAC_CURRENT_SINKING_BIT_MASK;
0307         else
0308             /* disable current sinking in manual mode */
0309             val &= ~IDAC_CURRENT_SINKING_BIT_MASK;
0310     } else {
0311         /* disable manual control of IDAC */
0312         val &= ~IDAC_MANUAL_CONTROL_BIT_MASK;
0313
0314         /* set hysteresis value  reg: 0x0B<5:0> */
0315         ret = mxl111sf_write_reg(state, V6_IDAC_HYSTERESIS_REG,
0316                      (hysteresis_value & 0x3F));
0317         mxl_fail(ret);
0318     }
0319
0320     ret = mxl111sf_write_reg(state, V6_IDAC_SETTINGS_REG, val);
0321     mxl_fail(ret);
0322
0323     return ret;
0324 }