usb/dvb-usb-v2/af9035.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Afatech AF9035 DVB USB driver
0004  *
0005  * Copyright (C) 2009 Antti Palosaari <crope@iki.fi>
0006  * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
0007  */
0008
0009 #ifndef AF9035_H
0010 #define AF9035_H
0011
0012 #include <linux/platform_device.h>
0013 #include "dvb_usb.h"
0014 #include "af9033.h"
0015 #include "tua9001.h"
0016 #include "fc0011.h"
0017 #include "fc0012.h"
0018 #include "mxl5007t.h"
0019 #include "tda18218.h"
0020 #include "fc2580.h"
0021 #include "it913x.h"
0022 #include "si2168.h"
0023 #include "si2157.h"
0024
0025 struct reg_val {
0026     u32 reg;
0027     u8  val;
0028 };
0029
0030 struct reg_val_mask {
0031     u32 reg;
0032     u8  val;
0033     u8  mask;
0034 };
0035
0036 struct usb_req {
0037     u8  cmd;
0038     u8  mbox;
0039     u8  wlen;
0040     u8  *wbuf;
0041     u8  rlen;
0042     u8  *rbuf;
0043 };
0044
0045 struct state {
0046 #define BUF_LEN 64
0047     u8 buf[BUF_LEN];
0048     u8 seq; /* packet sequence number */
0049     u8 prechip_version;
0050     u8 chip_version;
0051     u16 chip_type;
0052     u8 eeprom[256];
0053     bool no_eeprom;
0054     u8 ir_mode;
0055     u8 ir_type;
0056     u8 dual_mode:1;
0057     u8 no_read:1;
0058     u8 af9033_i2c_addr[2];
0059     u8 it930x_addresses;
0060     struct af9033_config af9033_config[2];
0061     struct af9033_ops ops;
0062     #define AF9035_I2C_CLIENT_MAX 4
0063     struct i2c_client *i2c_client[AF9035_I2C_CLIENT_MAX];
0064     struct i2c_adapter *i2c_adapter_demod;
0065     struct platform_device *platform_device_tuner[2];
0066 };
0067
0068 struct address_table {
0069     u8 frontend_i2c_addr;
0070     u8 tuner_i2c_addr;
0071     u8 tuner_if_port;
0072 };
0073
0074 static const struct address_table it930x_addresses_table[] = {
0075     { 0x67, 0x63, 1 },
0076     { 0x64, 0x60, 0 },
0077 };
0078
0079 static const u32 clock_lut_af9035[] = {
0080     20480000, /*      FPGA */
0081     16384000, /* 16.38 MHz */
0082     20480000, /* 20.48 MHz */
0083     36000000, /* 36.00 MHz */
0084     30000000, /* 30.00 MHz */
0085     26000000, /* 26.00 MHz */
0086     28000000, /* 28.00 MHz */
0087     32000000, /* 32.00 MHz */
0088     34000000, /* 34.00 MHz */
0089     24000000, /* 24.00 MHz */
0090     22000000, /* 22.00 MHz */
0091     12000000, /* 12.00 MHz */
0092 };
0093
0094 static const u32 clock_lut_it9135[] = {
0095     12000000, /* 12.00 MHz */
0096     20480000, /* 20.48 MHz */
0097     36000000, /* 36.00 MHz */
0098     30000000, /* 30.00 MHz */
0099     26000000, /* 26.00 MHz */
0100     28000000, /* 28.00 MHz */
0101     32000000, /* 32.00 MHz */
0102     34000000, /* 34.00 MHz */
0103     24000000, /* 24.00 MHz */
0104     22000000, /* 22.00 MHz */
0105 };
0106
0107 #define AF9035_FIRMWARE_AF9035 "dvb-usb-af9035-02.fw"
0108 #define AF9035_FIRMWARE_IT9135_V1 "dvb-usb-it9135-01.fw"
0109 #define AF9035_FIRMWARE_IT9135_V2 "dvb-usb-it9135-02.fw"
0110 #define AF9035_FIRMWARE_IT9303 "dvb-usb-it9303-01.fw"
0111
0112 /*
0113  * eeprom is memory mapped as read only. Writing that memory mapped address
0114  * will not corrupt eeprom.
0115  *
0116  * TS mode:
0117  * 0  TS
0118  * 1  DCA + PIP
0119  * 3  PIP
0120  * 5  DCA + PIP (AF9035 only)
0121  * n  DCA
0122  *
0123  * Values 0, 3 and 5 are seen to this day. 0 for single TS and 3/5 for dual TS.
0124  */
0125
0126 #define EEPROM_BASE_AF9035        0x42f5
0127 #define EEPROM_BASE_IT9135        0x4994
0128 #define EEPROM_SHIFT                0x10
0129
0130 #define EEPROM_IR_MODE              0x18
0131 #define EEPROM_TS_MODE              0x31
0132 #define EEPROM_2ND_DEMOD_ADDR       0x32
0133 #define EEPROM_IR_TYPE              0x34
0134 #define EEPROM_1_IF_L               0x38
0135 #define EEPROM_1_IF_H               0x39
0136 #define EEPROM_1_TUNER_ID           0x3c
0137 #define EEPROM_2_IF_L               0x48
0138 #define EEPROM_2_IF_H               0x49
0139 #define EEPROM_2_TUNER_ID           0x4c
0140
0141 /* USB commands */
0142 #define CMD_MEM_RD                  0x00
0143 #define CMD_MEM_WR                  0x01
0144 #define CMD_I2C_RD                  0x02
0145 #define CMD_I2C_WR                  0x03
0146 #define CMD_IR_GET                  0x18
0147 #define CMD_FW_DL                   0x21
0148 #define CMD_FW_QUERYINFO            0x22
0149 #define CMD_FW_BOOT                 0x23
0150 #define CMD_FW_DL_BEGIN             0x24
0151 #define CMD_FW_DL_END               0x25
0152 #define CMD_FW_SCATTER_WR           0x29
0153 #define CMD_GENERIC_I2C_RD          0x2a
0154 #define CMD_GENERIC_I2C_WR          0x2b
0155
0156 #endif