media/tuners/tda18250_priv.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * NXP TDA18250BHN silicon tuner driver
0004  *
0005  * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
0006  */
0007
0008 #ifndef TDA18250_PRIV_H
0009 #define TDA18250_PRIV_H
0010
0011 #include "tda18250.h"
0012
0013 #define R00_ID1     0x00    /* ID byte 1 */
0014 #define R01_ID2     0x01    /* ID byte 2 */
0015 #define R02_ID3     0x02    /* ID byte 3 */
0016 #define R03_THERMO1 0x03    /* Thermo byte 1 */
0017 #define R04_THERMO2 0x04    /* Thermo byte 2 */
0018 #define R05_POWER1  0x05    /* Power byte 1 */
0019 #define R06_POWER2  0x06    /* Power byte 2 */
0020 #define R07_GPIO    0x07    /* GPIO */
0021 #define R08_IRQ1    0x08    /* IRQ */
0022 #define R09_IRQ2    0x09    /* IRQ */
0023 #define R0A_IRQ3    0x0a    /* IRQ */
0024 #define R0B_IRQ4    0x0b    /* IRQ */
0025 #define R0C_AGC11   0x0c    /* AGC1 byte 1 */
0026 #define R0D_AGC12   0x0d    /* AGC1 byte 2 */
0027 #define R0E_AGC13   0x0e    /* AGC1 byte 3 */
0028 #define R0F_AGC14   0x0f    /* AGC1 byte 4 */
0029 #define R10_LT1     0x10    /* LT byte 1 */
0030 #define R11_LT2     0x11    /* LT byte 2 */
0031 #define R12_AGC21   0x12    /* AGC2 byte 1 */
0032 #define R13_AGC22   0x13    /* AGC2 byte 2 */
0033 #define R14_AGC23   0x14    /* AGC2 byte 3 */
0034 #define R15_AGC24   0x15    /* AGC2 byte 4 */
0035 #define R16_AGC25   0x16    /* AGC2 byte 5 */
0036 #define R17_AGC31   0x17    /* AGC3 byte 1 */
0037 #define R18_AGC32   0x18    /* AGC3 byte 2 */
0038 #define R19_AGC33   0x19    /* AGC3 byte 3 */
0039 #define R1A_AGCK    0x1a
0040 #define R1B_GAIN1   0x1b
0041 #define R1C_GAIN2   0x1c
0042 #define R1D_GAIN3   0x1d
0043 #define R1E_WI_FI   0x1e    /* Wireless Filter */
0044 #define R1F_RF_BPF  0x1f    /* RF Band Pass Filter */
0045 #define R20_IR_MIX  0x20    /* IR Mixer */
0046 #define R21_IF_AGC  0x21
0047 #define R22_IF1     0x22    /* IF byte 1 */
0048 #define R23_IF2     0x23    /* IF byte 2 */
0049 #define R24_IF3     0x24    /* IF byte 3 */
0050 #define R25_REF     0x25    /* reference byte */
0051 #define R26_IF      0x26    /* IF frequency */
0052 #define R27_RF1     0x27    /* RF frequency byte 1 */
0053 #define R28_RF2     0x28    /* RF frequency byte 2 */
0054 #define R29_RF3     0x29    /* RF frequency byte 3 */
0055 #define R2A_MSM1    0x2a
0056 #define R2B_MSM2    0x2b
0057 #define R2C_PS1     0x2c    /* power saving mode byte 1 */
0058 #define R2D_PS2     0x2d    /* power saving mode byte 2 */
0059 #define R2E_PS3     0x2e    /* power saving mode byte 3 */
0060 #define R2F_RSSI1   0x2f
0061 #define R30_RSSI2   0x30
0062 #define R31_IRQ_CTRL    0x31
0063 #define R32_DUMMY   0x32
0064 #define R33_TEST    0x33
0065 #define R34_MD1     0x34
0066 #define R35_SD1     0x35
0067 #define R36_SD2     0x36
0068 #define R37_SD3     0x37
0069 #define R38_SD4     0x38
0070 #define R39_SD5     0x39
0071 #define R3A_SD_TEST 0x3a
0072 #define R3B_REGU    0x3b
0073 #define R3C_RCCAL1  0x3c
0074 #define R3D_RCCAL2  0x3d
0075 #define R3E_IRCAL1  0x3e
0076 #define R3F_IRCAL2  0x3f
0077 #define R40_IRCAL3  0x40
0078 #define R41_IRCAL4  0x41
0079 #define R42_IRCAL5  0x42
0080 #define R43_PD1     0x43    /* power down byte 1 */
0081 #define R44_PD2     0x44    /* power down byte 2 */
0082 #define R45_PD      0x45    /* power down */
0083 #define R46_CPUMP   0x46    /* charge pump */
0084 #define R47_LNAPOL  0x47    /* LNA polar casc */
0085 #define R48_SMOOTH1 0x48    /* smooth test byte 1 */
0086 #define R49_SMOOTH2 0x49    /* smooth test byte 2 */
0087 #define R4A_SMOOTH3 0x4a    /* smooth test byte 3 */
0088 #define R4B_XTALOSC1    0x4b
0089 #define R4C_XTALOSC2    0x4c
0090 #define R4D_XTALFLX1    0x4d
0091 #define R4E_XTALFLX2    0x4e
0092 #define R4F_XTALFLX3    0x4f
0093 #define R50_XTALFLX4    0x50
0094 #define R51_XTALFLX5    0x51
0095 #define R52_IRLOOP0 0x52
0096 #define R53_IRLOOP1 0x53
0097 #define R54_IRLOOP2 0x54
0098 #define R55_IRLOOP3 0x55
0099 #define R56_IRLOOP4 0x56
0100 #define R57_PLL_LOG 0x57
0101 #define R58_AGC2_UP1    0x58
0102 #define R59_AGC2_UP2    0x59
0103 #define R5A_H3H5    0x5a
0104 #define R5B_AGC_AUTO    0x5b
0105 #define R5C_AGC_DEBUG   0x5c
0106
0107 #define TDA18250_NUM_REGS 93
0108
0109 #define TDA18250_POWER_STANDBY 0
0110 #define TDA18250_POWER_NORMAL 1
0111
0112 #define TDA18250_IRQ_CAL     0x81
0113 #define TDA18250_IRQ_HW_INIT 0x82
0114 #define TDA18250_IRQ_TUNE    0x88
0115
0116 struct tda18250_dev {
0117     struct mutex i2c_mutex;
0118     struct dvb_frontend *fe;
0119     struct i2c_adapter *i2c;
0120     struct regmap *regmap;
0121     u8 xtal_freq;
0122     /* IF in kHz */
0123     u16 if_dvbt_6;
0124     u16 if_dvbt_7;
0125     u16 if_dvbt_8;
0126     u16 if_dvbc_6;
0127     u16 if_dvbc_8;
0128     u16 if_atsc;
0129     u16 if_frequency;
0130     bool slave;
0131     bool loopthrough;
0132     bool warm;
0133     u8 regs[TDA18250_NUM_REGS];
0134 };
0135
0136 #endif