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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * NXP TDA18250 silicon tuner driver
0004  *
0005  * Copyright (C) 2017 Olli Salonen <olli.salonen@iki.fi>
0006  */
0007 
0008 #include "tda18250_priv.h"
0009 #include <linux/regmap.h>
0010 
0011 static const struct dvb_tuner_ops tda18250_ops;
0012 
0013 static int tda18250_power_control(struct dvb_frontend *fe,
0014         unsigned int power_state)
0015 {
0016     struct i2c_client *client = fe->tuner_priv;
0017     struct tda18250_dev *dev = i2c_get_clientdata(client);
0018     int ret;
0019     unsigned int utmp;
0020 
0021     dev_dbg(&client->dev, "power state: %d", power_state);
0022 
0023     switch (power_state) {
0024     case TDA18250_POWER_NORMAL:
0025         ret = regmap_write_bits(dev->regmap, R06_POWER2, 0x07, 0x00);
0026         if (ret)
0027             goto err;
0028         ret = regmap_write_bits(dev->regmap, R25_REF, 0xc0, 0xc0);
0029         if (ret)
0030             goto err;
0031         break;
0032     case TDA18250_POWER_STANDBY:
0033         if (dev->loopthrough) {
0034             ret = regmap_write_bits(dev->regmap,
0035                     R25_REF, 0xc0, 0x80);
0036             if (ret)
0037                 goto err;
0038             ret = regmap_write_bits(dev->regmap,
0039                     R06_POWER2, 0x07, 0x02);
0040             if (ret)
0041                 goto err;
0042             ret = regmap_write_bits(dev->regmap,
0043                     R10_LT1, 0x80, 0x00);
0044             if (ret)
0045                 goto err;
0046         } else {
0047             ret = regmap_write_bits(dev->regmap,
0048                     R25_REF, 0xc0, 0x80);
0049             if (ret)
0050                 goto err;
0051             ret = regmap_write_bits(dev->regmap,
0052                     R06_POWER2, 0x07, 0x01);
0053             if (ret)
0054                 goto err;
0055             ret = regmap_read(dev->regmap,
0056                     R0D_AGC12, &utmp);
0057             if (ret)
0058                 goto err;
0059             ret = regmap_write_bits(dev->regmap,
0060                     R0D_AGC12, 0x03, 0x03);
0061             if (ret)
0062                 goto err;
0063             ret = regmap_write_bits(dev->regmap,
0064                     R10_LT1, 0x80, 0x80);
0065             if (ret)
0066                 goto err;
0067             ret = regmap_write_bits(dev->regmap,
0068                     R0D_AGC12, 0x03, utmp & 0x03);
0069             if (ret)
0070                 goto err;
0071         }
0072         break;
0073     default:
0074         ret = -EINVAL;
0075         goto err;
0076     }
0077 
0078     return 0;
0079 err:
0080     return ret;
0081 }
0082 
0083 static int tda18250_wait_for_irq(struct dvb_frontend *fe,
0084         int maxwait, int step, u8 irq)
0085 {
0086     struct i2c_client *client = fe->tuner_priv;
0087     struct tda18250_dev *dev = i2c_get_clientdata(client);
0088     int ret;
0089     unsigned long timeout;
0090     bool triggered;
0091     unsigned int utmp;
0092 
0093     triggered = false;
0094     timeout = jiffies + msecs_to_jiffies(maxwait);
0095     while (!time_after(jiffies, timeout)) {
0096         // check for the IRQ
0097         ret = regmap_read(dev->regmap, R08_IRQ1, &utmp);
0098         if (ret)
0099             goto err;
0100         if ((utmp & irq) == irq) {
0101             triggered = true;
0102             break;
0103         }
0104         msleep(step);
0105     }
0106 
0107     dev_dbg(&client->dev, "waited IRQ (0x%02x) %d ms, triggered: %s", irq,
0108             jiffies_to_msecs(jiffies) -
0109             (jiffies_to_msecs(timeout) - maxwait),
0110             triggered ? "true" : "false");
0111 
0112     if (!triggered)
0113         return -ETIMEDOUT;
0114 
0115     return 0;
0116 err:
0117     return ret;
0118 }
0119 
0120 static int tda18250_init(struct dvb_frontend *fe)
0121 {
0122     struct i2c_client *client = fe->tuner_priv;
0123     struct tda18250_dev *dev = i2c_get_clientdata(client);
0124     int ret, i;
0125 
0126     /* default values for various regs */
0127     static const u8 init_regs[][2] = {
0128         { R0C_AGC11, 0xc7 },
0129         { R0D_AGC12, 0x5d },
0130         { R0E_AGC13, 0x40 },
0131         { R0F_AGC14, 0x0e },
0132         { R10_LT1, 0x47 },
0133         { R11_LT2, 0x4e },
0134         { R12_AGC21, 0x26 },
0135         { R13_AGC22, 0x60 },
0136         { R18_AGC32, 0x37 },
0137         { R19_AGC33, 0x09 },
0138         { R1A_AGCK, 0x00 },
0139         { R1E_WI_FI, 0x29 },
0140         { R1F_RF_BPF, 0x06 },
0141         { R20_IR_MIX, 0xc6 },
0142         { R21_IF_AGC, 0x00 },
0143         { R2C_PS1, 0x75 },
0144         { R2D_PS2, 0x06 },
0145         { R2E_PS3, 0x07 },
0146         { R30_RSSI2, 0x0e },
0147         { R31_IRQ_CTRL, 0x00 },
0148         { R39_SD5, 0x00 },
0149         { R3B_REGU, 0x55 },
0150         { R3C_RCCAL1, 0xa7 },
0151         { R3F_IRCAL2, 0x85 },
0152         { R40_IRCAL3, 0x87 },
0153         { R41_IRCAL4, 0xc0 },
0154         { R43_PD1, 0x40 },
0155         { R44_PD2, 0xc0 },
0156         { R46_CPUMP, 0x0c },
0157         { R47_LNAPOL, 0x64 },
0158         { R4B_XTALOSC1, 0x30 },
0159         { R59_AGC2_UP2, 0x05 },
0160         { R5B_AGC_AUTO, 0x07 },
0161         { R5C_AGC_DEBUG, 0x00 },
0162     };
0163 
0164     /* crystal related regs depend on frequency */
0165     static const u8 xtal_regs[][5] = {
0166                     /* reg:   4d    4e    4f    50    51 */
0167         [TDA18250_XTAL_FREQ_16MHZ]  = { 0x3e, 0x80, 0x50, 0x00, 0x20 },
0168         [TDA18250_XTAL_FREQ_24MHZ]  = { 0x5d, 0xc0, 0xec, 0x00, 0x18 },
0169         [TDA18250_XTAL_FREQ_25MHZ]  = { 0x61, 0xa8, 0xec, 0x80, 0x19 },
0170         [TDA18250_XTAL_FREQ_27MHZ]  = { 0x69, 0x78, 0x8d, 0x80, 0x1b },
0171         [TDA18250_XTAL_FREQ_30MHZ]  = { 0x75, 0x30, 0x8f, 0x00, 0x1e },
0172     };
0173 
0174     dev_dbg(&client->dev, "\n");
0175 
0176     ret = tda18250_power_control(fe, TDA18250_POWER_NORMAL);
0177     if (ret)
0178         goto err;
0179 
0180     msleep(20);
0181 
0182     if (dev->warm)
0183         goto warm;
0184 
0185     /* set initial register values */
0186     for (i = 0; i < ARRAY_SIZE(init_regs); i++) {
0187         ret = regmap_write(dev->regmap, init_regs[i][0],
0188                 init_regs[i][1]);
0189         if (ret)
0190             goto err;
0191     }
0192 
0193     /* set xtal related regs */
0194     ret = regmap_bulk_write(dev->regmap, R4D_XTALFLX1,
0195             xtal_regs[dev->xtal_freq], 5);
0196     if (ret)
0197         goto err;
0198 
0199     ret = regmap_write_bits(dev->regmap, R10_LT1, 0x80,
0200             dev->loopthrough ? 0x00 : 0x80);
0201     if (ret)
0202         goto err;
0203 
0204     /* clear IRQ */
0205     ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_HW_INIT);
0206     if (ret)
0207         goto err;
0208 
0209     /* start HW init */
0210     ret = regmap_write(dev->regmap, R2A_MSM1, 0x70);
0211     if (ret)
0212         goto err;
0213 
0214     ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
0215     if (ret)
0216         goto err;
0217 
0218     ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_HW_INIT);
0219     if (ret)
0220         goto err;
0221 
0222     /* tuner calibration */
0223     ret = regmap_write(dev->regmap, R2A_MSM1, 0x02);
0224     if (ret)
0225         goto err;
0226 
0227     ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
0228     if (ret)
0229         goto err;
0230 
0231     ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_CAL);
0232     if (ret)
0233         goto err;
0234 
0235     dev->warm = true;
0236 
0237 warm:
0238     /* power up LNA */
0239     ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
0240     if (ret)
0241         goto err;
0242 
0243     return 0;
0244 err:
0245     dev_dbg(&client->dev, "failed=%d", ret);
0246     return ret;
0247 }
0248 
0249 static int tda18250_set_agc(struct dvb_frontend *fe)
0250 {
0251     struct i2c_client *client = fe->tuner_priv;
0252     struct tda18250_dev *dev = i2c_get_clientdata(client);
0253     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0254     int ret;
0255     u8 utmp, utmp2;
0256 
0257     dev_dbg(&client->dev, "\n");
0258 
0259     ret = regmap_write_bits(dev->regmap, R1F_RF_BPF, 0x87, 0x06);
0260     if (ret)
0261         goto err;
0262 
0263     utmp = ((c->frequency < 100000000) &&
0264             ((c->delivery_system == SYS_DVBC_ANNEX_A) ||
0265             (c->delivery_system == SYS_DVBC_ANNEX_C)) &&
0266             (c->bandwidth_hz == 6000000)) ? 0x80 : 0x00;
0267     ret = regmap_write(dev->regmap, R5A_H3H5, utmp);
0268     if (ret)
0269         goto err;
0270 
0271     /* AGC1 */
0272     switch (c->delivery_system) {
0273     case SYS_ATSC:
0274     case SYS_DVBT:
0275     case SYS_DVBT2:
0276         utmp = 4;
0277         break;
0278     default: /* DVB-C/QAM */
0279         switch (c->bandwidth_hz) {
0280         case 6000000:
0281             utmp = (c->frequency < 800000000) ? 6 : 4;
0282             break;
0283         default: /* 7.935 and 8 MHz */
0284             utmp = (c->frequency < 100000000) ? 2 : 3;
0285             break;
0286         }
0287         break;
0288     }
0289 
0290     ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x07, utmp);
0291     if (ret)
0292         goto err;
0293 
0294     /* AGC2 */
0295     switch (c->delivery_system) {
0296     case SYS_ATSC:
0297     case SYS_DVBT:
0298     case SYS_DVBT2:
0299         utmp = (c->frequency < 320000000) ? 20 : 16;
0300         utmp2 = (c->frequency < 320000000) ? 22 : 18;
0301         break;
0302     default: /* DVB-C/QAM */
0303         switch (c->bandwidth_hz) {
0304         case 6000000:
0305             if (c->frequency < 600000000) {
0306                 utmp = 18;
0307                 utmp2 = 22;
0308             } else if (c->frequency < 800000000) {
0309                 utmp = 16;
0310                 utmp2 = 20;
0311             } else {
0312                 utmp = 14;
0313                 utmp2 = 16;
0314             }
0315             break;
0316         default: /* 7.935 and 8 MHz */
0317             utmp = (c->frequency < 320000000) ? 16 : 18;
0318             utmp2 = (c->frequency < 320000000) ? 18 : 20;
0319             break;
0320         }
0321         break;
0322     }
0323     ret = regmap_write_bits(dev->regmap, R58_AGC2_UP1, 0x1f, utmp2+8);
0324     if (ret)
0325         goto err;
0326     ret = regmap_write_bits(dev->regmap, R13_AGC22, 0x1f, utmp);
0327     if (ret)
0328         goto err;
0329     ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x1f, utmp2);
0330     if (ret)
0331         goto err;
0332 
0333     switch (c->delivery_system) {
0334     case SYS_ATSC:
0335     case SYS_DVBT:
0336     case SYS_DVBT2:
0337         utmp = 98;
0338         break;
0339     default: /* DVB-C/QAM */
0340         utmp = 90;
0341         break;
0342     }
0343     ret = regmap_write_bits(dev->regmap, R16_AGC25, 0xf8, utmp);
0344     if (ret)
0345         goto err;
0346 
0347     ret = regmap_write_bits(dev->regmap, R12_AGC21, 0x60,
0348             (c->frequency > 800000000) ? 0x40 : 0x20);
0349     if (ret)
0350         goto err;
0351 
0352     /* AGC3 */
0353     switch (c->delivery_system) {
0354     case SYS_ATSC:
0355     case SYS_DVBT:
0356     case SYS_DVBT2:
0357         utmp = (c->frequency < 320000000) ? 5 : 7;
0358         utmp2 = (c->frequency < 320000000) ? 10 : 12;
0359         break;
0360     default: /* DVB-C/QAM */
0361         utmp = 7;
0362         utmp2 = 12;
0363         break;
0364     }
0365     ret = regmap_write(dev->regmap, R17_AGC31, (utmp << 4) | utmp2);
0366     if (ret)
0367         goto err;
0368 
0369     /* S2D */
0370     switch (c->delivery_system) {
0371     case SYS_ATSC:
0372     case SYS_DVBT:
0373     case SYS_DVBT2:
0374         if (c->bandwidth_hz == 8000000)
0375             utmp = 0x04;
0376         else
0377             utmp = (c->frequency < 320000000) ? 0x04 : 0x02;
0378         break;
0379     default: /* DVB-C/QAM */
0380         if (c->bandwidth_hz == 6000000)
0381             utmp = ((c->frequency > 172544000) &&
0382                 (c->frequency < 320000000)) ? 0x04 : 0x02;
0383         else /* 7.935 and 8 MHz */
0384             utmp = ((c->frequency > 320000000) &&
0385                 (c->frequency < 600000000)) ? 0x02 : 0x04;
0386         break;
0387     }
0388     ret = regmap_write_bits(dev->regmap, R20_IR_MIX, 0x06, utmp);
0389     if (ret)
0390         goto err;
0391 
0392     switch (c->delivery_system) {
0393     case SYS_ATSC:
0394     case SYS_DVBT:
0395     case SYS_DVBT2:
0396         utmp = 0;
0397         break;
0398     default: /* DVB-C/QAM */
0399         utmp = (c->frequency < 600000000) ? 0 : 3;
0400         break;
0401     }
0402     ret = regmap_write_bits(dev->regmap, R16_AGC25, 0x03, utmp);
0403     if (ret)
0404         goto err;
0405 
0406     utmp = 0x09;
0407     switch (c->delivery_system) {
0408     case SYS_ATSC:
0409     case SYS_DVBT:
0410     case SYS_DVBT2:
0411         if (c->bandwidth_hz == 8000000)
0412             utmp = 0x0c;
0413         break;
0414     default: /* DVB-C/QAM */
0415         utmp = 0x0c;
0416         break;
0417     }
0418     ret = regmap_write_bits(dev->regmap, R0F_AGC14, 0x3f, utmp);
0419     if (ret)
0420         goto err;
0421 
0422     return 0;
0423 err:
0424     dev_dbg(&client->dev, "failed=%d", ret);
0425     return ret;
0426 }
0427 
0428 static int tda18250_pll_calc(struct dvb_frontend *fe, u8 *rdiv,
0429         u8 *ndiv, u8 *icp)
0430 {
0431     struct i2c_client *client = fe->tuner_priv;
0432     struct tda18250_dev *dev = i2c_get_clientdata(client);
0433     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0434     int ret;
0435     unsigned int uval, exp, lopd, scale;
0436     unsigned long fvco;
0437 
0438     ret = regmap_read(dev->regmap, R34_MD1, &uval);
0439     if (ret)
0440         goto err;
0441 
0442     exp = (uval & 0x70) >> 4;
0443     if (exp > 5)
0444         exp = 0;
0445     lopd = 1 << (exp - 1);
0446     scale = uval & 0x0f;
0447     fvco = lopd * scale * ((c->frequency / 1000) + dev->if_frequency);
0448 
0449     switch (dev->xtal_freq) {
0450     case TDA18250_XTAL_FREQ_16MHZ:
0451         *rdiv = 1;
0452         *ndiv = 0;
0453         *icp = (fvco < 6622000) ? 0x05 : 0x02;
0454     break;
0455     case TDA18250_XTAL_FREQ_24MHZ:
0456     case TDA18250_XTAL_FREQ_25MHZ:
0457         *rdiv = 3;
0458         *ndiv = 1;
0459         *icp = (fvco < 6622000) ? 0x05 : 0x02;
0460     break;
0461     case TDA18250_XTAL_FREQ_27MHZ:
0462         if (fvco < 6643000) {
0463             *rdiv = 2;
0464             *ndiv = 0;
0465             *icp = 0x05;
0466         } else if (fvco < 6811000) {
0467             *rdiv = 2;
0468             *ndiv = 0;
0469             *icp = 0x06;
0470         } else {
0471             *rdiv = 3;
0472             *ndiv = 1;
0473             *icp = 0x02;
0474         }
0475     break;
0476     case TDA18250_XTAL_FREQ_30MHZ:
0477         *rdiv = 2;
0478         *ndiv = 0;
0479         *icp = (fvco < 6811000) ? 0x05 : 0x02;
0480     break;
0481     default:
0482         return -EINVAL;
0483     }
0484 
0485     dev_dbg(&client->dev,
0486             "lopd=%d scale=%u fvco=%lu, rdiv=%d ndiv=%d icp=%d",
0487             lopd, scale, fvco, *rdiv, *ndiv, *icp);
0488     return 0;
0489 err:
0490     return ret;
0491 }
0492 
0493 static int tda18250_set_params(struct dvb_frontend *fe)
0494 {
0495     struct i2c_client *client = fe->tuner_priv;
0496     struct tda18250_dev *dev = i2c_get_clientdata(client);
0497     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0498     u32 if_khz;
0499     int ret;
0500     unsigned int i, j;
0501     u8 utmp;
0502     u8 buf[3];
0503 
0504     #define REG      0
0505     #define MASK     1
0506     #define DVBT_6   2
0507     #define DVBT_7   3
0508     #define DVBT_8   4
0509     #define DVBC_6   5
0510     #define DVBC_8   6
0511     #define ATSC     7
0512 
0513     static const u8 delsys_params[][16] = {
0514         [REG]    = { 0x22, 0x23, 0x24, 0x21, 0x0d, 0x0c, 0x0f, 0x14,
0515                  0x0e, 0x12, 0x58, 0x59, 0x1a, 0x19, 0x1e, 0x30 },
0516         [MASK]   = { 0x77, 0xff, 0xff, 0x87, 0xf0, 0x78, 0x07, 0xe0,
0517                  0x60, 0x0f, 0x60, 0x0f, 0x33, 0x30, 0x80, 0x06 },
0518         [DVBT_6] = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
0519                  0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
0520         [DVBT_7] = { 0x52, 0x03, 0x85, 0x82, 0x40, 0x48, 0x01, 0xe0,
0521                  0x60, 0x0f, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
0522         [DVBT_8] = { 0x53, 0x03, 0x87, 0x82, 0x40, 0x48, 0x06, 0xe0,
0523                  0x60, 0x07, 0x60, 0x05, 0x03, 0x10, 0x00, 0x04 },
0524         [DVBC_6] = { 0x32, 0x05, 0x86, 0x82, 0x50, 0x00, 0x06, 0x60,
0525                  0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
0526         [DVBC_8] = { 0x53, 0x03, 0x88, 0x82, 0x50, 0x00, 0x06, 0x60,
0527                  0x40, 0x0e, 0x60, 0x05, 0x33, 0x10, 0x00, 0x04 },
0528         [ATSC]   = { 0x51, 0x03, 0x83, 0x82, 0x40, 0x48, 0x01, 0xe0,
0529                  0x40, 0x0e, 0x60, 0x05, 0x03, 0x00, 0x80, 0x04 },
0530     };
0531 
0532     dev_dbg(&client->dev,
0533             "delivery_system=%d frequency=%u bandwidth_hz=%u",
0534             c->delivery_system, c->frequency, c->bandwidth_hz);
0535 
0536 
0537     switch (c->delivery_system) {
0538     case SYS_ATSC:
0539         j = ATSC;
0540         if_khz = dev->if_atsc;
0541         break;
0542     case SYS_DVBT:
0543     case SYS_DVBT2:
0544         if (c->bandwidth_hz == 0) {
0545             ret = -EINVAL;
0546             goto err;
0547         } else if (c->bandwidth_hz <= 6000000) {
0548             j = DVBT_6;
0549             if_khz = dev->if_dvbt_6;
0550         } else if (c->bandwidth_hz <= 7000000) {
0551             j = DVBT_7;
0552             if_khz = dev->if_dvbt_7;
0553         } else if (c->bandwidth_hz <= 8000000) {
0554             j = DVBT_8;
0555             if_khz = dev->if_dvbt_8;
0556         } else {
0557             ret = -EINVAL;
0558             goto err;
0559         }
0560         break;
0561     case SYS_DVBC_ANNEX_A:
0562     case SYS_DVBC_ANNEX_C:
0563         if (c->bandwidth_hz == 0) {
0564             ret = -EINVAL;
0565             goto err;
0566         } else if (c->bandwidth_hz <= 6000000) {
0567             j = DVBC_6;
0568             if_khz = dev->if_dvbc_6;
0569         } else if (c->bandwidth_hz <= 8000000) {
0570             j = DVBC_8;
0571             if_khz = dev->if_dvbc_8;
0572         } else {
0573             ret = -EINVAL;
0574             goto err;
0575         }
0576         break;
0577     default:
0578         ret = -EINVAL;
0579         dev_err(&client->dev, "unsupported delivery system=%d",
0580                 c->delivery_system);
0581         goto err;
0582     }
0583 
0584     /* set delivery system dependent registers */
0585     for (i = 0; i < 16; i++) {
0586         ret = regmap_write_bits(dev->regmap, delsys_params[REG][i],
0587              delsys_params[MASK][i],  delsys_params[j][i]);
0588         if (ret)
0589             goto err;
0590     }
0591 
0592     /* set IF if needed */
0593     if (dev->if_frequency != if_khz) {
0594         utmp = DIV_ROUND_CLOSEST(if_khz, 50);
0595         ret = regmap_write(dev->regmap, R26_IF, utmp);
0596         if (ret)
0597             goto err;
0598         dev->if_frequency = if_khz;
0599         dev_dbg(&client->dev, "set IF=%u kHz", if_khz);
0600 
0601     }
0602 
0603     ret = tda18250_set_agc(fe);
0604     if (ret)
0605         goto err;
0606 
0607     ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x01);
0608     if (ret)
0609         goto err;
0610 
0611     ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x00);
0612     if (ret)
0613         goto err;
0614 
0615     /* set frequency */
0616     buf[0] = ((c->frequency / 1000) >> 16) & 0xff;
0617     buf[1] = ((c->frequency / 1000) >>  8) & 0xff;
0618     buf[2] = ((c->frequency / 1000) >>  0) & 0xff;
0619     ret = regmap_bulk_write(dev->regmap, R27_RF1, buf, 3);
0620     if (ret)
0621         goto err;
0622 
0623     ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
0624     if (ret)
0625         goto err;
0626 
0627     /* initial tune */
0628     ret = regmap_write(dev->regmap, R2A_MSM1, 0x01);
0629     if (ret)
0630         goto err;
0631 
0632     ret = regmap_write(dev->regmap, R2B_MSM2, 0x01);
0633     if (ret)
0634         goto err;
0635 
0636     ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
0637     if (ret)
0638         goto err;
0639 
0640     /* calc ndiv and rdiv */
0641     ret = tda18250_pll_calc(fe, &buf[0], &buf[1], &buf[2]);
0642     if (ret)
0643         goto err;
0644 
0645     ret = regmap_write_bits(dev->regmap, R4F_XTALFLX3, 0xe0,
0646             (buf[0] << 6) | (buf[1] << 5));
0647     if (ret)
0648         goto err;
0649 
0650     /* clear IRQ */
0651     ret = regmap_write(dev->regmap, R0A_IRQ3, TDA18250_IRQ_TUNE);
0652     if (ret)
0653         goto err;
0654 
0655     ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, 0x00);
0656     if (ret)
0657         goto err;
0658 
0659     ret = regmap_write_bits(dev->regmap, R39_SD5, 0x03, 0x00);
0660     if (ret)
0661         goto err;
0662 
0663     /* tune again */
0664     ret = regmap_write(dev->regmap, R2A_MSM1, 0x01); /* tune */
0665     if (ret)
0666         goto err;
0667 
0668     ret = regmap_write(dev->regmap, R2B_MSM2, 0x01); /* go */
0669     if (ret)
0670         goto err;
0671 
0672     ret = tda18250_wait_for_irq(fe, 500, 10, TDA18250_IRQ_TUNE);
0673     if (ret)
0674         goto err;
0675 
0676     /* pll locking */
0677     msleep(20);
0678 
0679     ret = regmap_write_bits(dev->regmap, R2B_MSM2, 0x04, 0x04);
0680     if (ret)
0681         goto err;
0682 
0683     msleep(20);
0684 
0685     /* restore AGCK */
0686     ret = regmap_write_bits(dev->regmap, R1A_AGCK, 0x03, 0x03);
0687     if (ret)
0688         goto err;
0689 
0690     ret = regmap_write_bits(dev->regmap, R14_AGC23, 0x40, 0x40);
0691     if (ret)
0692         goto err;
0693 
0694     /* charge pump */
0695     ret = regmap_write_bits(dev->regmap, R46_CPUMP, 0x07, buf[2]);
0696 
0697     return 0;
0698 err:
0699     return ret;
0700 }
0701 
0702 static int tda18250_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
0703 {
0704     struct i2c_client *client = fe->tuner_priv;
0705     struct tda18250_dev *dev = i2c_get_clientdata(client);
0706 
0707     *frequency = dev->if_frequency * 1000;
0708     return 0;
0709 }
0710 
0711 static int tda18250_sleep(struct dvb_frontend *fe)
0712 {
0713     struct i2c_client *client = fe->tuner_priv;
0714     struct tda18250_dev *dev = i2c_get_clientdata(client);
0715     int ret;
0716 
0717     dev_dbg(&client->dev, "\n");
0718 
0719     /* power down LNA */
0720     ret = regmap_write_bits(dev->regmap, R0C_AGC11, 0x80, 0x00);
0721     if (ret)
0722         return ret;
0723 
0724     /* set if freq to 0 in order to make sure it's set after wake up */
0725     dev->if_frequency = 0;
0726 
0727     ret = tda18250_power_control(fe, TDA18250_POWER_STANDBY);
0728     return ret;
0729 }
0730 
0731 static const struct dvb_tuner_ops tda18250_ops = {
0732     .info = {
0733         .name              = "NXP TDA18250",
0734         .frequency_min_hz  =  42 * MHz,
0735         .frequency_max_hz  = 870 * MHz,
0736     },
0737 
0738     .init = tda18250_init,
0739     .set_params = tda18250_set_params,
0740     .get_if_frequency = tda18250_get_if_frequency,
0741     .sleep = tda18250_sleep,
0742 };
0743 
0744 static int tda18250_probe(struct i2c_client *client,
0745         const struct i2c_device_id *id)
0746 {
0747     struct tda18250_config *cfg = client->dev.platform_data;
0748     struct dvb_frontend *fe = cfg->fe;
0749     struct tda18250_dev *dev;
0750     int ret;
0751     unsigned char chip_id[3];
0752 
0753     /* some registers are always read from HW */
0754     static const struct regmap_range tda18250_yes_ranges[] = {
0755         regmap_reg_range(R05_POWER1, R0B_IRQ4),
0756         regmap_reg_range(R21_IF_AGC, R21_IF_AGC),
0757         regmap_reg_range(R2A_MSM1, R2B_MSM2),
0758         regmap_reg_range(R2F_RSSI1, R31_IRQ_CTRL),
0759     };
0760 
0761     static const struct regmap_access_table tda18250_volatile_table = {
0762         .yes_ranges = tda18250_yes_ranges,
0763         .n_yes_ranges = ARRAY_SIZE(tda18250_yes_ranges),
0764     };
0765 
0766     static const struct regmap_config tda18250_regmap_config = {
0767         .reg_bits = 8,
0768         .val_bits = 8,
0769         .max_register = TDA18250_NUM_REGS - 1,
0770         .volatile_table = &tda18250_volatile_table,
0771     };
0772 
0773     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0774     if (!dev) {
0775         ret = -ENOMEM;
0776         goto err;
0777     }
0778 
0779     i2c_set_clientdata(client, dev);
0780 
0781     dev->fe = cfg->fe;
0782     dev->loopthrough = cfg->loopthrough;
0783     if (cfg->xtal_freq < TDA18250_XTAL_FREQ_MAX) {
0784         dev->xtal_freq = cfg->xtal_freq;
0785     } else {
0786         ret = -EINVAL;
0787         dev_err(&client->dev, "xtal_freq invalid=%d", cfg->xtal_freq);
0788         goto err_kfree;
0789     }
0790     dev->if_dvbt_6 = cfg->if_dvbt_6;
0791     dev->if_dvbt_7 = cfg->if_dvbt_7;
0792     dev->if_dvbt_8 = cfg->if_dvbt_8;
0793     dev->if_dvbc_6 = cfg->if_dvbc_6;
0794     dev->if_dvbc_8 = cfg->if_dvbc_8;
0795     dev->if_atsc = cfg->if_atsc;
0796 
0797     dev->if_frequency = 0;
0798     dev->warm = false;
0799 
0800     dev->regmap = devm_regmap_init_i2c(client, &tda18250_regmap_config);
0801     if (IS_ERR(dev->regmap)) {
0802         ret = PTR_ERR(dev->regmap);
0803         goto err_kfree;
0804     }
0805 
0806     /* read the three chip ID registers */
0807     regmap_bulk_read(dev->regmap, R00_ID1, &chip_id, 3);
0808     dev_dbg(&client->dev, "chip_id=%02x:%02x:%02x",
0809             chip_id[0], chip_id[1], chip_id[2]);
0810 
0811     switch (chip_id[0]) {
0812     case 0xc7:
0813         dev->slave = false;
0814         break;
0815     case 0x47:
0816         dev->slave = true;
0817         break;
0818     default:
0819         ret = -ENODEV;
0820         goto err_kfree;
0821     }
0822 
0823     if (chip_id[1] != 0x4a) {
0824         ret = -ENODEV;
0825         goto err_kfree;
0826     }
0827 
0828     switch (chip_id[2]) {
0829     case 0x20:
0830         dev_info(&client->dev,
0831                 "NXP TDA18250AHN/%s successfully identified",
0832                 dev->slave ? "S" : "M");
0833         break;
0834     case 0x21:
0835         dev_info(&client->dev,
0836                 "NXP TDA18250BHN/%s successfully identified",
0837                 dev->slave ? "S" : "M");
0838         break;
0839     default:
0840         ret = -ENODEV;
0841         goto err_kfree;
0842     }
0843 
0844     fe->tuner_priv = client;
0845     memcpy(&fe->ops.tuner_ops, &tda18250_ops,
0846             sizeof(struct dvb_tuner_ops));
0847 
0848     /* put the tuner in standby */
0849     tda18250_power_control(fe, TDA18250_POWER_STANDBY);
0850 
0851     return 0;
0852 err_kfree:
0853     kfree(dev);
0854 err:
0855     dev_dbg(&client->dev, "failed=%d", ret);
0856     return ret;
0857 }
0858 
0859 static int tda18250_remove(struct i2c_client *client)
0860 {
0861     struct tda18250_dev *dev = i2c_get_clientdata(client);
0862     struct dvb_frontend *fe = dev->fe;
0863 
0864     dev_dbg(&client->dev, "\n");
0865 
0866     memset(&fe->ops.tuner_ops, 0, sizeof(struct dvb_tuner_ops));
0867     fe->tuner_priv = NULL;
0868     kfree(dev);
0869 
0870     return 0;
0871 }
0872 
0873 static const struct i2c_device_id tda18250_id_table[] = {
0874     {"tda18250", 0},
0875     {}
0876 };
0877 MODULE_DEVICE_TABLE(i2c, tda18250_id_table);
0878 
0879 static struct i2c_driver tda18250_driver = {
0880     .driver = {
0881         .name   = "tda18250",
0882     },
0883     .probe      = tda18250_probe,
0884     .remove     = tda18250_remove,
0885     .id_table   = tda18250_id_table,
0886 };
0887 
0888 module_i2c_driver(tda18250_driver);
0889 
0890 MODULE_DESCRIPTION("NXP TDA18250 silicon tuner driver");
0891 MODULE_AUTHOR("Olli Salonen <olli.salonen@iki.fi>");
0892 MODULE_LICENSE("GPL");
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