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0001 // SPDX-License-Identifier: GPL-2.0
0002 // Rafael Micro R820T driver
0003 //
0004 // Copyright (C) 2013 Mauro Carvalho Chehab
0005 //
0006 // This driver was written from scratch, based on an existing driver
0007 // that it is part of rtl-sdr git tree, released under GPLv2:
0008 //  https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
0009 //  https://github.com/n1gp/gr-baz
0010 //
0011 // From what I understood from the threads, the original driver was converted
0012 // to userspace from a Realtek tree. I couldn't find the original tree.
0013 // However, the original driver look awkward on my eyes. So, I decided to
0014 // write a new version from it from the scratch, while trying to reproduce
0015 // everything found there.
0016 //
0017 // TODO:
0018 //  After locking, the original driver seems to have some routines to
0019 //      improve reception. This was not implemented here yet.
0020 //
0021 //  RF Gain set/get is not implemented.
0022 
0023 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0024 
0025 #include <linux/videodev2.h>
0026 #include <linux/mutex.h>
0027 #include <linux/slab.h>
0028 #include <linux/bitrev.h>
0029 
0030 #include "tuner-i2c.h"
0031 #include "r820t.h"
0032 
0033 /*
0034  * FIXME: I think that there are only 32 registers, but better safe than
0035  *    sorry. After finishing the driver, we may review it.
0036  */
0037 #define REG_SHADOW_START    5
0038 #define NUM_REGS        27
0039 #define NUM_IMR         5
0040 #define IMR_TRIAL       9
0041 
0042 #define VER_NUM  49
0043 
0044 static int debug;
0045 module_param(debug, int, 0644);
0046 MODULE_PARM_DESC(debug, "enable verbose debug messages");
0047 
0048 static int no_imr_cal;
0049 module_param(no_imr_cal, int, 0444);
0050 MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
0051 
0052 
0053 /*
0054  * enums and structures
0055  */
0056 
0057 enum xtal_cap_value {
0058     XTAL_LOW_CAP_30P = 0,
0059     XTAL_LOW_CAP_20P,
0060     XTAL_LOW_CAP_10P,
0061     XTAL_LOW_CAP_0P,
0062     XTAL_HIGH_CAP_0P
0063 };
0064 
0065 struct r820t_sect_type {
0066     u8  phase_y;
0067     u8  gain_x;
0068     u16 value;
0069 };
0070 
0071 struct r820t_priv {
0072     struct list_head        hybrid_tuner_instance_list;
0073     const struct r820t_config   *cfg;
0074     struct tuner_i2c_props      i2c_props;
0075     struct mutex            lock;
0076 
0077     u8              regs[NUM_REGS];
0078     u8              buf[NUM_REGS + 1];
0079     enum xtal_cap_value     xtal_cap_sel;
0080     u16             pll;    /* kHz */
0081     u32             int_freq;
0082     u8              fil_cal_code;
0083     bool                imr_done;
0084     bool                has_lock;
0085     bool                init_done;
0086     struct r820t_sect_type      imr_data[NUM_IMR];
0087 
0088     /* Store current mode */
0089     u32             delsys;
0090     enum v4l2_tuner_type        type;
0091     v4l2_std_id         std;
0092     u32             bw; /* in MHz */
0093 };
0094 
0095 struct r820t_freq_range {
0096     u32 freq;
0097     u8  open_d;
0098     u8  rf_mux_ploy;
0099     u8  tf_c;
0100     u8  xtal_cap20p;
0101     u8  xtal_cap10p;
0102     u8  xtal_cap0p;
0103     u8  imr_mem;        /* Not used, currently */
0104 };
0105 
0106 #define VCO_POWER_REF   0x02
0107 #define DIP_FREQ    32000000
0108 
0109 /*
0110  * Static constants
0111  */
0112 
0113 static LIST_HEAD(hybrid_tuner_instance_list);
0114 static DEFINE_MUTEX(r820t_list_mutex);
0115 
0116 /* Those initial values start from REG_SHADOW_START */
0117 static const u8 r820t_init_array[NUM_REGS] = {
0118     0x83, 0x32, 0x75,           /* 05 to 07 */
0119     0xc0, 0x40, 0xd6, 0x6c,         /* 08 to 0b */
0120     0xf5, 0x63, 0x75, 0x68,         /* 0c to 0f */
0121     0x6c, 0x83, 0x80, 0x00,         /* 10 to 13 */
0122     0x0f, 0x00, 0xc0, 0x30,         /* 14 to 17 */
0123     0x48, 0xcc, 0x60, 0x00,         /* 18 to 1b */
0124     0x54, 0xae, 0x4a, 0xc0          /* 1c to 1f */
0125 };
0126 
0127 /* Tuner frequency ranges */
0128 static const struct r820t_freq_range freq_ranges[] = {
0129     {
0130         .freq = 0,
0131         .open_d = 0x08,     /* low */
0132         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0133         .tf_c = 0xdf,       /* R27[7:0]  band2,band0 */
0134         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0135         .xtal_cap10p = 0x01,
0136         .xtal_cap0p = 0x00,
0137         .imr_mem = 0,
0138     }, {
0139         .freq = 50,     /* Start freq, in MHz */
0140         .open_d = 0x08,     /* low */
0141         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0142         .tf_c = 0xbe,       /* R27[7:0]  band4,band1  */
0143         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0144         .xtal_cap10p = 0x01,
0145         .xtal_cap0p = 0x00,
0146         .imr_mem = 0,
0147     }, {
0148         .freq = 55,     /* Start freq, in MHz */
0149         .open_d = 0x08,     /* low */
0150         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0151         .tf_c = 0x8b,       /* R27[7:0]  band7,band4 */
0152         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0153         .xtal_cap10p = 0x01,
0154         .xtal_cap0p = 0x00,
0155         .imr_mem = 0,
0156     }, {
0157         .freq = 60,     /* Start freq, in MHz */
0158         .open_d = 0x08,     /* low */
0159         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0160         .tf_c = 0x7b,       /* R27[7:0]  band8,band4 */
0161         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0162         .xtal_cap10p = 0x01,
0163         .xtal_cap0p = 0x00,
0164         .imr_mem = 0,
0165     }, {
0166         .freq = 65,     /* Start freq, in MHz */
0167         .open_d = 0x08,     /* low */
0168         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0169         .tf_c = 0x69,       /* R27[7:0]  band9,band6 */
0170         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0171         .xtal_cap10p = 0x01,
0172         .xtal_cap0p = 0x00,
0173         .imr_mem = 0,
0174     }, {
0175         .freq = 70,     /* Start freq, in MHz */
0176         .open_d = 0x08,     /* low */
0177         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0178         .tf_c = 0x58,       /* R27[7:0]  band10,band7 */
0179         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0180         .xtal_cap10p = 0x01,
0181         .xtal_cap0p = 0x00,
0182         .imr_mem = 0,
0183     }, {
0184         .freq = 75,     /* Start freq, in MHz */
0185         .open_d = 0x00,     /* high */
0186         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0187         .tf_c = 0x44,       /* R27[7:0]  band11,band11 */
0188         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0189         .xtal_cap10p = 0x01,
0190         .xtal_cap0p = 0x00,
0191         .imr_mem = 0,
0192     }, {
0193         .freq = 80,     /* Start freq, in MHz */
0194         .open_d = 0x00,     /* high */
0195         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0196         .tf_c = 0x44,       /* R27[7:0]  band11,band11 */
0197         .xtal_cap20p = 0x02,    /* R16[1:0]  20pF (10)   */
0198         .xtal_cap10p = 0x01,
0199         .xtal_cap0p = 0x00,
0200         .imr_mem = 0,
0201     }, {
0202         .freq = 90,     /* Start freq, in MHz */
0203         .open_d = 0x00,     /* high */
0204         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0205         .tf_c = 0x34,       /* R27[7:0]  band12,band11 */
0206         .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
0207         .xtal_cap10p = 0x01,
0208         .xtal_cap0p = 0x00,
0209         .imr_mem = 0,
0210     }, {
0211         .freq = 100,        /* Start freq, in MHz */
0212         .open_d = 0x00,     /* high */
0213         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0214         .tf_c = 0x34,       /* R27[7:0]  band12,band11 */
0215         .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)    */
0216         .xtal_cap10p = 0x01,
0217         .xtal_cap0p = 0x00,
0218         .imr_mem = 0,
0219     }, {
0220         .freq = 110,        /* Start freq, in MHz */
0221         .open_d = 0x00,     /* high */
0222         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0223         .tf_c = 0x24,       /* R27[7:0]  band13,band11 */
0224         .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
0225         .xtal_cap10p = 0x01,
0226         .xtal_cap0p = 0x00,
0227         .imr_mem = 1,
0228     }, {
0229         .freq = 120,        /* Start freq, in MHz */
0230         .open_d = 0x00,     /* high */
0231         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0232         .tf_c = 0x24,       /* R27[7:0]  band13,band11 */
0233         .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
0234         .xtal_cap10p = 0x01,
0235         .xtal_cap0p = 0x00,
0236         .imr_mem = 1,
0237     }, {
0238         .freq = 140,        /* Start freq, in MHz */
0239         .open_d = 0x00,     /* high */
0240         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0241         .tf_c = 0x14,       /* R27[7:0]  band14,band11 */
0242         .xtal_cap20p = 0x01,    /* R16[1:0]  10pF (01)   */
0243         .xtal_cap10p = 0x01,
0244         .xtal_cap0p = 0x00,
0245         .imr_mem = 1,
0246     }, {
0247         .freq = 180,        /* Start freq, in MHz */
0248         .open_d = 0x00,     /* high */
0249         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0250         .tf_c = 0x13,       /* R27[7:0]  band14,band12 */
0251         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0252         .xtal_cap10p = 0x00,
0253         .xtal_cap0p = 0x00,
0254         .imr_mem = 1,
0255     }, {
0256         .freq = 220,        /* Start freq, in MHz */
0257         .open_d = 0x00,     /* high */
0258         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0259         .tf_c = 0x13,       /* R27[7:0]  band14,band12 */
0260         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0261         .xtal_cap10p = 0x00,
0262         .xtal_cap0p = 0x00,
0263         .imr_mem = 2,
0264     }, {
0265         .freq = 250,        /* Start freq, in MHz */
0266         .open_d = 0x00,     /* high */
0267         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0268         .tf_c = 0x11,       /* R27[7:0]  highest,highest */
0269         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0270         .xtal_cap10p = 0x00,
0271         .xtal_cap0p = 0x00,
0272         .imr_mem = 2,
0273     }, {
0274         .freq = 280,        /* Start freq, in MHz */
0275         .open_d = 0x00,     /* high */
0276         .rf_mux_ploy = 0x02,    /* R26[7:6]=0 (LPF)  R26[1:0]=2 (low) */
0277         .tf_c = 0x00,       /* R27[7:0]  highest,highest */
0278         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0279         .xtal_cap10p = 0x00,
0280         .xtal_cap0p = 0x00,
0281         .imr_mem = 2,
0282     }, {
0283         .freq = 310,        /* Start freq, in MHz */
0284         .open_d = 0x00,     /* high */
0285         .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
0286         .tf_c = 0x00,       /* R27[7:0]  highest,highest */
0287         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0288         .xtal_cap10p = 0x00,
0289         .xtal_cap0p = 0x00,
0290         .imr_mem = 2,
0291     }, {
0292         .freq = 450,        /* Start freq, in MHz */
0293         .open_d = 0x00,     /* high */
0294         .rf_mux_ploy = 0x41,    /* R26[7:6]=1 (bypass)  R26[1:0]=1 (middle) */
0295         .tf_c = 0x00,       /* R27[7:0]  highest,highest */
0296         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0297         .xtal_cap10p = 0x00,
0298         .xtal_cap0p = 0x00,
0299         .imr_mem = 3,
0300     }, {
0301         .freq = 588,        /* Start freq, in MHz */
0302         .open_d = 0x00,     /* high */
0303         .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
0304         .tf_c = 0x00,       /* R27[7:0]  highest,highest */
0305         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0306         .xtal_cap10p = 0x00,
0307         .xtal_cap0p = 0x00,
0308         .imr_mem = 3,
0309     }, {
0310         .freq = 650,        /* Start freq, in MHz */
0311         .open_d = 0x00,     /* high */
0312         .rf_mux_ploy = 0x40,    /* R26[7:6]=1 (bypass)  R26[1:0]=0 (highest) */
0313         .tf_c = 0x00,       /* R27[7:0]  highest,highest */
0314         .xtal_cap20p = 0x00,    /* R16[1:0]  0pF (00)   */
0315         .xtal_cap10p = 0x00,
0316         .xtal_cap0p = 0x00,
0317         .imr_mem = 4,
0318     }
0319 };
0320 
0321 static int r820t_xtal_capacitor[][2] = {
0322     { 0x0b, XTAL_LOW_CAP_30P },
0323     { 0x02, XTAL_LOW_CAP_20P },
0324     { 0x01, XTAL_LOW_CAP_10P },
0325     { 0x00, XTAL_LOW_CAP_0P  },
0326     { 0x10, XTAL_HIGH_CAP_0P },
0327 };
0328 
0329 static const char *r820t_chip_enum_to_str(enum r820t_chip chip)
0330 {
0331     switch (chip) {
0332     case CHIP_R820T:
0333         return "R820T";
0334     case CHIP_R620D:
0335         return "R620D";
0336     case CHIP_R828D:
0337         return "R828D";
0338     case CHIP_R828:
0339         return "R828";
0340     case CHIP_R828S:
0341         return "R828S";
0342     case CHIP_R820C:
0343         return "R820C";
0344     default:
0345         return "<unknown>";
0346     }
0347 }
0348 
0349 /*
0350  * I2C read/write code and shadow registers logic
0351  */
0352 static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
0353              int len)
0354 {
0355     int r = reg - REG_SHADOW_START;
0356 
0357     if (r < 0) {
0358         len += r;
0359         r = 0;
0360     }
0361     if (len <= 0)
0362         return;
0363     if (len > NUM_REGS - r)
0364         len = NUM_REGS - r;
0365 
0366     tuner_dbg("%s: prev  reg=%02x len=%d: %*ph\n",
0367           __func__, r + REG_SHADOW_START, len, len, val);
0368 
0369     memcpy(&priv->regs[r], val, len);
0370 }
0371 
0372 static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
0373                int len)
0374 {
0375     int rc, size, pos = 0;
0376 
0377     /* Store the shadow registers */
0378     shadow_store(priv, reg, val, len);
0379 
0380     do {
0381         if (len > priv->cfg->max_i2c_msg_len - 1)
0382             size = priv->cfg->max_i2c_msg_len - 1;
0383         else
0384             size = len;
0385 
0386         /* Fill I2C buffer */
0387         priv->buf[0] = reg;
0388         memcpy(&priv->buf[1], &val[pos], size);
0389 
0390         rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
0391         if (rc != size + 1) {
0392             tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
0393                    __func__, rc, reg, size, size, &priv->buf[1]);
0394             if (rc < 0)
0395                 return rc;
0396             return -EREMOTEIO;
0397         }
0398         tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
0399               __func__, reg, size, size, &priv->buf[1]);
0400 
0401         reg += size;
0402         len -= size;
0403         pos += size;
0404     } while (len > 0);
0405 
0406     return 0;
0407 }
0408 
0409 static inline int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
0410 {
0411     u8 tmp = val; /* work around GCC PR81715 with asan-stack=1 */
0412 
0413     return r820t_write(priv, reg, &tmp, 1);
0414 }
0415 
0416 static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
0417 {
0418     reg -= REG_SHADOW_START;
0419 
0420     if (reg >= 0 && reg < NUM_REGS)
0421         return priv->regs[reg];
0422     else
0423         return -EINVAL;
0424 }
0425 
0426 static inline int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
0427                 u8 bit_mask)
0428 {
0429     u8 tmp = val;
0430     int rc = r820t_read_cache_reg(priv, reg);
0431 
0432     if (rc < 0)
0433         return rc;
0434 
0435     tmp = (rc & ~bit_mask) | (tmp & bit_mask);
0436 
0437     return r820t_write(priv, reg, &tmp, 1);
0438 }
0439 
0440 static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
0441 {
0442     int rc, i;
0443     u8 *p = &priv->buf[1];
0444 
0445     priv->buf[0] = reg;
0446 
0447     rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
0448     if (rc != len) {
0449         tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
0450                __func__, rc, reg, len, len, p);
0451         if (rc < 0)
0452             return rc;
0453         return -EREMOTEIO;
0454     }
0455 
0456     /* Copy data to the output buffer */
0457     for (i = 0; i < len; i++)
0458         val[i] = bitrev8(p[i]);
0459 
0460     tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
0461           __func__, reg, len, len, val);
0462 
0463     return 0;
0464 }
0465 
0466 /*
0467  * r820t tuning logic
0468  */
0469 
0470 static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
0471 {
0472     const struct r820t_freq_range *range;
0473     int i, rc;
0474     u8 val, reg08, reg09;
0475 
0476     /* Get the proper frequency range */
0477     freq = freq / 1000000;
0478     for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
0479         if (freq < freq_ranges[i + 1].freq)
0480             break;
0481     }
0482     range = &freq_ranges[i];
0483 
0484     tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
0485 
0486     /* Open Drain */
0487     rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
0488     if (rc < 0)
0489         return rc;
0490 
0491     /* RF_MUX,Polymux */
0492     rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
0493     if (rc < 0)
0494         return rc;
0495 
0496     /* TF BAND */
0497     rc = r820t_write_reg(priv, 0x1b, range->tf_c);
0498     if (rc < 0)
0499         return rc;
0500 
0501     /* XTAL CAP & Drive */
0502     switch (priv->xtal_cap_sel) {
0503     case XTAL_LOW_CAP_30P:
0504     case XTAL_LOW_CAP_20P:
0505         val = range->xtal_cap20p | 0x08;
0506         break;
0507     case XTAL_LOW_CAP_10P:
0508         val = range->xtal_cap10p | 0x08;
0509         break;
0510     case XTAL_HIGH_CAP_0P:
0511         val = range->xtal_cap0p | 0x00;
0512         break;
0513     default:
0514     case XTAL_LOW_CAP_0P:
0515         val = range->xtal_cap0p | 0x08;
0516         break;
0517     }
0518     rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
0519     if (rc < 0)
0520         return rc;
0521 
0522     if (priv->imr_done) {
0523         reg08 = priv->imr_data[range->imr_mem].gain_x;
0524         reg09 = priv->imr_data[range->imr_mem].phase_y;
0525     } else {
0526         reg08 = 0;
0527         reg09 = 0;
0528     }
0529     rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
0530     if (rc < 0)
0531         return rc;
0532 
0533     rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
0534 
0535     return rc;
0536 }
0537 
0538 static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
0539              u32 freq)
0540 {
0541     u32 vco_freq;
0542     int rc, i;
0543     unsigned sleep_time = 10000;
0544     u32 vco_fra;        /* VCO contribution by SDM (kHz) */
0545     u32 vco_min  = 1770000;
0546     u32 vco_max  = vco_min * 2;
0547     u32 pll_ref;
0548     u16 n_sdm = 2;
0549     u16 sdm = 0;
0550     u8 mix_div = 2;
0551     u8 div_buf = 0;
0552     u8 div_num = 0;
0553     u8 refdiv2 = 0;
0554     u8 ni, si, nint, vco_fine_tune, val;
0555     u8 data[5];
0556 
0557     /* Frequency in kHz */
0558     freq = freq / 1000;
0559     pll_ref = priv->cfg->xtal / 1000;
0560 
0561 #if 0
0562     /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
0563     if ((priv->cfg->rafael_chip == CHIP_R620D) ||
0564        (priv->cfg->rafael_chip == CHIP_R828D) ||
0565        (priv->cfg->rafael_chip == CHIP_R828)) {
0566         /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
0567         if (type != V4L2_TUNER_DIGITAL_TV) {
0568             pll_ref /= 2;
0569             refdiv2 = 0x10;
0570             sleep_time = 20000;
0571         }
0572     } else {
0573         if (priv->cfg->xtal > 24000000) {
0574             pll_ref /= 2;
0575             refdiv2 = 0x10;
0576         }
0577     }
0578 #endif
0579 
0580     rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
0581     if (rc < 0)
0582         return rc;
0583 
0584     /* set pll autotune = 128kHz */
0585     rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
0586     if (rc < 0)
0587         return rc;
0588 
0589     /* set VCO current = 100 */
0590     rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
0591     if (rc < 0)
0592         return rc;
0593 
0594     /* Calculate divider */
0595     while (mix_div <= 64) {
0596         if (((freq * mix_div) >= vco_min) &&
0597            ((freq * mix_div) < vco_max)) {
0598             div_buf = mix_div;
0599             while (div_buf > 2) {
0600                 div_buf = div_buf >> 1;
0601                 div_num++;
0602             }
0603             break;
0604         }
0605         mix_div = mix_div << 1;
0606     }
0607 
0608     rc = r820t_read(priv, 0x00, data, sizeof(data));
0609     if (rc < 0)
0610         return rc;
0611 
0612     vco_fine_tune = (data[4] & 0x30) >> 4;
0613 
0614     tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
0615             mix_div, div_num, vco_fine_tune);
0616 
0617     /*
0618      * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
0619      * Due to that, this calculation goes wrong.
0620      */
0621     if (priv->cfg->rafael_chip != CHIP_R828D) {
0622         if (vco_fine_tune > VCO_POWER_REF)
0623             div_num = div_num - 1;
0624         else if (vco_fine_tune < VCO_POWER_REF)
0625             div_num = div_num + 1;
0626     }
0627 
0628     rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
0629     if (rc < 0)
0630         return rc;
0631 
0632     vco_freq = freq * mix_div;
0633     nint = vco_freq / (2 * pll_ref);
0634     vco_fra = vco_freq - 2 * pll_ref * nint;
0635 
0636     /* boundary spur prevention */
0637     if (vco_fra < pll_ref / 64) {
0638         vco_fra = 0;
0639     } else if (vco_fra > pll_ref * 127 / 64) {
0640         vco_fra = 0;
0641         nint++;
0642     } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
0643         vco_fra = pll_ref * 127 / 128;
0644     } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
0645         vco_fra = pll_ref * 129 / 128;
0646     }
0647 
0648     ni = (nint - 13) / 4;
0649     si = nint - 4 * ni - 13;
0650 
0651     rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
0652     if (rc < 0)
0653         return rc;
0654 
0655     /* pw_sdm */
0656     if (!vco_fra)
0657         val = 0x08;
0658     else
0659         val = 0x00;
0660 
0661     rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
0662     if (rc < 0)
0663         return rc;
0664 
0665     /* sdm calculator */
0666     while (vco_fra > 1) {
0667         if (vco_fra > (2 * pll_ref / n_sdm)) {
0668             sdm = sdm + 32768 / (n_sdm / 2);
0669             vco_fra = vco_fra - 2 * pll_ref / n_sdm;
0670             if (n_sdm >= 0x8000)
0671                 break;
0672         }
0673         n_sdm = n_sdm << 1;
0674     }
0675 
0676     tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
0677           freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
0678 
0679     rc = r820t_write_reg(priv, 0x16, sdm >> 8);
0680     if (rc < 0)
0681         return rc;
0682     rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
0683     if (rc < 0)
0684         return rc;
0685 
0686     for (i = 0; i < 2; i++) {
0687         usleep_range(sleep_time, sleep_time + 1000);
0688 
0689         /* Check if PLL has locked */
0690         rc = r820t_read(priv, 0x00, data, 3);
0691         if (rc < 0)
0692             return rc;
0693         if (data[2] & 0x40)
0694             break;
0695 
0696         if (!i) {
0697             /* Didn't lock. Increase VCO current */
0698             rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
0699             if (rc < 0)
0700                 return rc;
0701         }
0702     }
0703 
0704     if (!(data[2] & 0x40)) {
0705         priv->has_lock = false;
0706         return 0;
0707     }
0708 
0709     priv->has_lock = true;
0710     tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
0711 
0712     /* set pll autotune = 8kHz */
0713     rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
0714 
0715     return rc;
0716 }
0717 
0718 static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
0719                  enum v4l2_tuner_type type,
0720                  v4l2_std_id std,
0721                  u32 delsys)
0722 {
0723     int rc;
0724     u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
0725     u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
0726 
0727     tuner_dbg("adjusting tuner parameters for the standard\n");
0728 
0729     switch (delsys) {
0730     case SYS_DVBT:
0731         if ((freq == 506000000) || (freq == 666000000) ||
0732            (freq == 818000000)) {
0733             mixer_top = 0x14;   /* mixer top:14 , top-1, low-discharge */
0734             lna_top = 0xe5;     /* detect bw 3, lna top:4, predet top:2 */
0735             cp_cur = 0x28;      /* 101, 0.2 */
0736             div_buf_cur = 0x20; /* 10, 200u */
0737         } else {
0738             mixer_top = 0x24;   /* mixer top:13 , top-1, low-discharge */
0739             lna_top = 0xe5;     /* detect bw 3, lna top:4, predet top:2 */
0740             cp_cur = 0x38;      /* 111, auto */
0741             div_buf_cur = 0x30; /* 11, 150u */
0742         }
0743         lna_vth_l = 0x53;       /* lna vth 0.84 ,  vtl 0.64 */
0744         mixer_vth_l = 0x75;     /* mixer vth 1.04, vtl 0.84 */
0745         air_cable1_in = 0x00;
0746         cable2_in = 0x00;
0747         pre_dect = 0x40;
0748         lna_discharge = 14;
0749         filter_cur = 0x40;      /* 10, low */
0750         break;
0751     case SYS_DVBT2:
0752         mixer_top = 0x24;   /* mixer top:13 , top-1, low-discharge */
0753         lna_top = 0xe5;     /* detect bw 3, lna top:4, predet top:2 */
0754         lna_vth_l = 0x53;   /* lna vth 0.84 ,  vtl 0.64 */
0755         mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
0756         air_cable1_in = 0x00;
0757         cable2_in = 0x00;
0758         pre_dect = 0x40;
0759         lna_discharge = 14;
0760         cp_cur = 0x38;      /* 111, auto */
0761         div_buf_cur = 0x30; /* 11, 150u */
0762         filter_cur = 0x40;  /* 10, low */
0763         break;
0764     case SYS_ISDBT:
0765         mixer_top = 0x24;   /* mixer top:13 , top-1, low-discharge */
0766         lna_top = 0xe5;     /* detect bw 3, lna top:4, predet top:2 */
0767         lna_vth_l = 0x75;   /* lna vth 1.04 ,  vtl 0.84 */
0768         mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
0769         air_cable1_in = 0x00;
0770         cable2_in = 0x00;
0771         pre_dect = 0x40;
0772         lna_discharge = 14;
0773         cp_cur = 0x38;      /* 111, auto */
0774         div_buf_cur = 0x30; /* 11, 150u */
0775         filter_cur = 0x40;  /* 10, low */
0776         break;
0777     case SYS_DVBC_ANNEX_A:
0778         mixer_top = 0x24;       /* mixer top:13 , top-1, low-discharge */
0779         lna_top = 0xe5;
0780         lna_vth_l = 0x62;
0781         mixer_vth_l = 0x75;
0782         air_cable1_in = 0x60;
0783         cable2_in = 0x00;
0784         pre_dect = 0x40;
0785         lna_discharge = 14;
0786         cp_cur = 0x38;          /* 111, auto */
0787         div_buf_cur = 0x30;     /* 11, 150u */
0788         filter_cur = 0x40;      /* 10, low */
0789         break;
0790     default: /* DVB-T 8M */
0791         mixer_top = 0x24;   /* mixer top:13 , top-1, low-discharge */
0792         lna_top = 0xe5;     /* detect bw 3, lna top:4, predet top:2 */
0793         lna_vth_l = 0x53;   /* lna vth 0.84 ,  vtl 0.64 */
0794         mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
0795         air_cable1_in = 0x00;
0796         cable2_in = 0x00;
0797         pre_dect = 0x40;
0798         lna_discharge = 14;
0799         cp_cur = 0x38;      /* 111, auto */
0800         div_buf_cur = 0x30; /* 11, 150u */
0801         filter_cur = 0x40;  /* 10, low */
0802         break;
0803     }
0804 
0805     if (priv->cfg->use_diplexer &&
0806        ((priv->cfg->rafael_chip == CHIP_R820T) ||
0807        (priv->cfg->rafael_chip == CHIP_R828S) ||
0808        (priv->cfg->rafael_chip == CHIP_R820C))) {
0809         if (freq > DIP_FREQ)
0810             air_cable1_in = 0x00;
0811         else
0812             air_cable1_in = 0x60;
0813         cable2_in = 0x00;
0814     }
0815 
0816 
0817     if (priv->cfg->use_predetect) {
0818         rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
0819         if (rc < 0)
0820             return rc;
0821     }
0822 
0823     rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
0824     if (rc < 0)
0825         return rc;
0826     rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
0827     if (rc < 0)
0828         return rc;
0829     rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
0830     if (rc < 0)
0831         return rc;
0832     rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
0833     if (rc < 0)
0834         return rc;
0835 
0836     /* Air-IN only for Astrometa */
0837     rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
0838     if (rc < 0)
0839         return rc;
0840     rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
0841     if (rc < 0)
0842         return rc;
0843 
0844     rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
0845     if (rc < 0)
0846         return rc;
0847     rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
0848     if (rc < 0)
0849         return rc;
0850     rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
0851     if (rc < 0)
0852         return rc;
0853     /*
0854      * Original driver initializes regs 0x05 and 0x06 with the
0855      * same value again on this point. Probably, it is just an
0856      * error there
0857      */
0858 
0859     /*
0860      * Set LNA
0861      */
0862 
0863     tuner_dbg("adjusting LNA parameters\n");
0864     if (type != V4L2_TUNER_ANALOG_TV) {
0865         /* LNA TOP: lowest */
0866         rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
0867         if (rc < 0)
0868             return rc;
0869 
0870         /* 0: normal mode */
0871         rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
0872         if (rc < 0)
0873             return rc;
0874 
0875         /* 0: PRE_DECT off */
0876         rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
0877         if (rc < 0)
0878             return rc;
0879 
0880         /* agc clk 250hz */
0881         rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
0882         if (rc < 0)
0883             return rc;
0884 
0885         msleep(250);
0886 
0887         /* write LNA TOP = 3 */
0888         rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
0889         if (rc < 0)
0890             return rc;
0891 
0892         /*
0893          * write discharge mode
0894          * FIXME: IMHO, the mask here is wrong, but it matches
0895          * what's there at the original driver
0896          */
0897         rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
0898         if (rc < 0)
0899             return rc;
0900 
0901         /* LNA discharge current */
0902         rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
0903         if (rc < 0)
0904             return rc;
0905 
0906         /* agc clk 60hz */
0907         rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
0908         if (rc < 0)
0909             return rc;
0910     } else {
0911         /* PRE_DECT off */
0912         rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
0913         if (rc < 0)
0914             return rc;
0915 
0916         /* write LNA TOP */
0917         rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
0918         if (rc < 0)
0919             return rc;
0920 
0921         /*
0922          * write discharge mode
0923          * FIXME: IMHO, the mask here is wrong, but it matches
0924          * what's there at the original driver
0925          */
0926         rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
0927         if (rc < 0)
0928             return rc;
0929 
0930         /* LNA discharge current */
0931         rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
0932         if (rc < 0)
0933             return rc;
0934 
0935         /* agc clk 1Khz, external det1 cap 1u */
0936         rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
0937         if (rc < 0)
0938             return rc;
0939 
0940         rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
0941         if (rc < 0)
0942             return rc;
0943     }
0944     return 0;
0945 }
0946 
0947 static int r820t_set_tv_standard(struct r820t_priv *priv,
0948                  unsigned bw,
0949                  enum v4l2_tuner_type type,
0950                  v4l2_std_id std, u32 delsys)
0951 
0952 {
0953     int rc, i;
0954     u32 if_khz, filt_cal_lo;
0955     u8 data[5], val;
0956     u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
0957     u8 lt_att, flt_ext_widest, polyfil_cur;
0958     bool need_calibration;
0959 
0960     tuner_dbg("selecting the delivery system\n");
0961 
0962     if (delsys == SYS_ISDBT) {
0963         if_khz = 4063;
0964         filt_cal_lo = 59000;
0965         filt_gain = 0x10;   /* +3db, 6mhz on */
0966         img_r = 0x00;       /* image negative */
0967         filt_q = 0x10;      /* r10[4]:low q(1'b1) */
0968         hp_cor = 0x6a;      /* 1.7m disable, +2cap, 1.25mhz */
0969         ext_enable = 0x40;  /* r30[6], ext enable; r30[5]:0 ext at lna max */
0970         loop_through = 0x00;    /* r5[7], lt on */
0971         lt_att = 0x00;      /* r31[7], lt att enable */
0972         flt_ext_widest = 0x80;  /* r15[7]: flt_ext_wide on */
0973         polyfil_cur = 0x60; /* r25[6:5]:min */
0974     } else if (delsys == SYS_DVBC_ANNEX_A) {
0975         if_khz = 5070;
0976         filt_cal_lo = 73500;
0977         filt_gain = 0x10;   /* +3db, 6mhz on */
0978         img_r = 0x00;       /* image negative */
0979         filt_q = 0x10;      /* r10[4]:low q(1'b1) */
0980         hp_cor = 0x0b;      /* 1.7m disable, +0cap, 1.0mhz */
0981         ext_enable = 0x40;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
0982         loop_through = 0x00;    /* r5[7], lt on */
0983         lt_att = 0x00;      /* r31[7], lt att enable */
0984         flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
0985         polyfil_cur = 0x60; /* r25[6:5]:min */
0986     } else if (delsys == SYS_DVBC_ANNEX_C) {
0987         if_khz = 4063;
0988         filt_cal_lo = 55000;
0989         filt_gain = 0x10;   /* +3db, 6mhz on */
0990         img_r = 0x00;       /* image negative */
0991         filt_q = 0x10;      /* r10[4]:low q(1'b1) */
0992         hp_cor = 0x6a;      /* 1.7m disable, +0cap, 1.0mhz */
0993         ext_enable = 0x40;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
0994         loop_through = 0x00;    /* r5[7], lt on */
0995         lt_att = 0x00;      /* r31[7], lt att enable */
0996         flt_ext_widest = 0x80;  /* r15[7]: flt_ext_wide on */
0997         polyfil_cur = 0x60; /* r25[6:5]:min */
0998     } else {
0999         if (bw <= 6) {
1000             if_khz = 3570;
1001             filt_cal_lo = 56000;    /* 52000->56000 */
1002             filt_gain = 0x10;   /* +3db, 6mhz on */
1003             img_r = 0x00;       /* image negative */
1004             filt_q = 0x10;      /* r10[4]:low q(1'b1) */
1005             hp_cor = 0x6b;      /* 1.7m disable, +2cap, 1.0mhz */
1006             ext_enable = 0x60;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1007             loop_through = 0x00;    /* r5[7], lt on */
1008             lt_att = 0x00;      /* r31[7], lt att enable */
1009             flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1010             polyfil_cur = 0x60; /* r25[6:5]:min */
1011         } else if (bw == 7) {
1012 #if 0
1013             /*
1014              * There are two 7 MHz tables defined on the original
1015              * driver, but just the second one seems to be visible
1016              * by rtl2832. Keep this one here commented, as it
1017              * might be needed in the future
1018              */
1019 
1020             if_khz = 4070;
1021             filt_cal_lo = 60000;
1022             filt_gain = 0x10;   /* +3db, 6mhz on */
1023             img_r = 0x00;       /* image negative */
1024             filt_q = 0x10;      /* r10[4]:low q(1'b1) */
1025             hp_cor = 0x2b;      /* 1.7m disable, +1cap, 1.0mhz */
1026             ext_enable = 0x60;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1027             loop_through = 0x00;    /* r5[7], lt on */
1028             lt_att = 0x00;      /* r31[7], lt att enable */
1029             flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1030             polyfil_cur = 0x60; /* r25[6:5]:min */
1031 #endif
1032             /* 7 MHz, second table */
1033             if_khz = 4570;
1034             filt_cal_lo = 63000;
1035             filt_gain = 0x10;   /* +3db, 6mhz on */
1036             img_r = 0x00;       /* image negative */
1037             filt_q = 0x10;      /* r10[4]:low q(1'b1) */
1038             hp_cor = 0x2a;      /* 1.7m disable, +1cap, 1.25mhz */
1039             ext_enable = 0x60;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1040             loop_through = 0x00;    /* r5[7], lt on */
1041             lt_att = 0x00;      /* r31[7], lt att enable */
1042             flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1043             polyfil_cur = 0x60; /* r25[6:5]:min */
1044         } else {
1045             if_khz = 4570;
1046             filt_cal_lo = 68500;
1047             filt_gain = 0x10;   /* +3db, 6mhz on */
1048             img_r = 0x00;       /* image negative */
1049             filt_q = 0x10;      /* r10[4]:low q(1'b1) */
1050             hp_cor = 0x0b;      /* 1.7m disable, +0cap, 1.0mhz */
1051             ext_enable = 0x60;  /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
1052             loop_through = 0x00;    /* r5[7], lt on */
1053             lt_att = 0x00;      /* r31[7], lt att enable */
1054             flt_ext_widest = 0x00;  /* r15[7]: flt_ext_wide off */
1055             polyfil_cur = 0x60; /* r25[6:5]:min */
1056         }
1057     }
1058 
1059     /* Initialize the shadow registers */
1060     memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1061 
1062     /* Init Flag & Xtal_check Result */
1063     if (priv->imr_done)
1064         val = 1 | priv->xtal_cap_sel << 1;
1065     else
1066         val = 0;
1067     rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
1068     if (rc < 0)
1069         return rc;
1070 
1071     /* version */
1072     rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
1073     if (rc < 0)
1074         return rc;
1075 
1076     /* for LT Gain test */
1077     if (type != V4L2_TUNER_ANALOG_TV) {
1078         rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
1079         if (rc < 0)
1080             return rc;
1081         usleep_range(1000, 2000);
1082     }
1083     priv->int_freq = if_khz * 1000;
1084 
1085     /* Check if standard changed. If so, filter calibration is needed */
1086     if (type != priv->type)
1087         need_calibration = true;
1088     else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
1089         need_calibration = true;
1090     else if ((type == V4L2_TUNER_DIGITAL_TV) &&
1091          ((delsys != priv->delsys) || bw != priv->bw))
1092         need_calibration = true;
1093     else
1094         need_calibration = false;
1095 
1096     if (need_calibration) {
1097         tuner_dbg("calibrating the tuner\n");
1098         for (i = 0; i < 2; i++) {
1099             /* Set filt_cap */
1100             rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
1101             if (rc < 0)
1102                 return rc;
1103 
1104             /* set cali clk =on */
1105             rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
1106             if (rc < 0)
1107                 return rc;
1108 
1109             /* X'tal cap 0pF for PLL */
1110             rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
1111             if (rc < 0)
1112                 return rc;
1113 
1114             rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
1115             if (rc < 0 || !priv->has_lock)
1116                 return rc;
1117 
1118             /* Start Trigger */
1119             rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
1120             if (rc < 0)
1121                 return rc;
1122 
1123             usleep_range(1000, 2000);
1124 
1125             /* Stop Trigger */
1126             rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
1127             if (rc < 0)
1128                 return rc;
1129 
1130             /* set cali clk =off */
1131             rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
1132             if (rc < 0)
1133                 return rc;
1134 
1135             /* Check if calibration worked */
1136             rc = r820t_read(priv, 0x00, data, sizeof(data));
1137             if (rc < 0)
1138                 return rc;
1139 
1140             priv->fil_cal_code = data[4] & 0x0f;
1141             if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
1142                 break;
1143         }
1144         /* narrowest */
1145         if (priv->fil_cal_code == 0x0f)
1146             priv->fil_cal_code = 0;
1147     }
1148 
1149     rc = r820t_write_reg_mask(priv, 0x0a,
1150                   filt_q | priv->fil_cal_code, 0x1f);
1151     if (rc < 0)
1152         return rc;
1153 
1154     /* Set BW, Filter_gain, & HP corner */
1155     rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
1156     if (rc < 0)
1157         return rc;
1158 
1159 
1160     /* Set Img_R */
1161     rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
1162     if (rc < 0)
1163         return rc;
1164 
1165     /* Set filt_3dB, V6MHz */
1166     rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
1167     if (rc < 0)
1168         return rc;
1169 
1170     /* channel filter extension */
1171     rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
1172     if (rc < 0)
1173         return rc;
1174 
1175     /* Loop through */
1176     rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
1177     if (rc < 0)
1178         return rc;
1179 
1180     /* Loop through attenuation */
1181     rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
1182     if (rc < 0)
1183         return rc;
1184 
1185     /* filter extension widest */
1186     rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
1187     if (rc < 0)
1188         return rc;
1189 
1190     /* RF poly filter current */
1191     rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
1192     if (rc < 0)
1193         return rc;
1194 
1195     /* Store current standard. If it changes, re-calibrate the tuner */
1196     priv->delsys = delsys;
1197     priv->type = type;
1198     priv->std = std;
1199     priv->bw = bw;
1200 
1201     return 0;
1202 }
1203 
1204 static int r820t_read_gain(struct r820t_priv *priv)
1205 {
1206     u8 data[4];
1207     int rc;
1208 
1209     rc = r820t_read(priv, 0x00, data, sizeof(data));
1210     if (rc < 0)
1211         return rc;
1212 
1213     return ((data[3] & 0x08) << 1) + ((data[3] & 0xf0) >> 4);
1214 }
1215 
1216 #if 0
1217 /* FIXME: This routine requires more testing */
1218 
1219 /*
1220  * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
1221  * input power, for raw results see:
1222  *  http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
1223  */
1224 
1225 static const int r820t_lna_gain_steps[]  = {
1226     0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
1227 };
1228 
1229 static const int r820t_mixer_gain_steps[]  = {
1230     0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
1231 };
1232 
1233 static int r820t_set_gain_mode(struct r820t_priv *priv,
1234                    bool set_manual_gain,
1235                    int gain)
1236 {
1237     int rc;
1238 
1239     if (set_manual_gain) {
1240         int i, total_gain = 0;
1241         uint8_t mix_index = 0, lna_index = 0;
1242         u8 data[4];
1243 
1244         /* LNA auto off */
1245         rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
1246         if (rc < 0)
1247             return rc;
1248 
1249          /* Mixer auto off */
1250         rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1251         if (rc < 0)
1252             return rc;
1253 
1254         rc = r820t_read(priv, 0x00, data, sizeof(data));
1255         if (rc < 0)
1256             return rc;
1257 
1258         /* set fixed VGA gain for now (16.3 dB) */
1259         rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
1260         if (rc < 0)
1261             return rc;
1262 
1263         for (i = 0; i < 15; i++) {
1264             if (total_gain >= gain)
1265                 break;
1266 
1267             total_gain += r820t_lna_gain_steps[++lna_index];
1268 
1269             if (total_gain >= gain)
1270                 break;
1271 
1272             total_gain += r820t_mixer_gain_steps[++mix_index];
1273         }
1274 
1275         /* set LNA gain */
1276         rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
1277         if (rc < 0)
1278             return rc;
1279 
1280         /* set Mixer gain */
1281         rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
1282         if (rc < 0)
1283             return rc;
1284     } else {
1285         /* LNA */
1286         rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
1287         if (rc < 0)
1288             return rc;
1289 
1290         /* Mixer */
1291         rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
1292         if (rc < 0)
1293             return rc;
1294 
1295         /* set fixed VGA gain for now (26.5 dB) */
1296         rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1297         if (rc < 0)
1298             return rc;
1299     }
1300 
1301     return 0;
1302 }
1303 #endif
1304 
1305 static int generic_set_freq(struct dvb_frontend *fe,
1306                 u32 freq /* in HZ */,
1307                 unsigned bw,
1308                 enum v4l2_tuner_type type,
1309                 v4l2_std_id std, u32 delsys)
1310 {
1311     struct r820t_priv       *priv = fe->tuner_priv;
1312     int             rc;
1313     u32             lo_freq;
1314 
1315     tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
1316           freq / 1000, bw);
1317 
1318     rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
1319     if (rc < 0)
1320         goto err;
1321 
1322     if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
1323         lo_freq = freq - priv->int_freq;
1324      else
1325         lo_freq = freq + priv->int_freq;
1326 
1327     rc = r820t_set_mux(priv, lo_freq);
1328     if (rc < 0)
1329         goto err;
1330 
1331     rc = r820t_set_pll(priv, type, lo_freq);
1332     if (rc < 0 || !priv->has_lock)
1333         goto err;
1334 
1335     rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
1336     if (rc < 0)
1337         goto err;
1338 
1339     tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
1340           __func__, freq, r820t_read_gain(priv));
1341 
1342 err:
1343 
1344     if (rc < 0)
1345         tuner_dbg("%s: failed=%d\n", __func__, rc);
1346     return rc;
1347 }
1348 
1349 /*
1350  * r820t standby logic
1351  */
1352 
1353 static int r820t_standby(struct r820t_priv *priv)
1354 {
1355     int rc;
1356 
1357     /* If device was not initialized yet, don't need to standby */
1358     if (!priv->init_done)
1359         return 0;
1360 
1361     rc = r820t_write_reg(priv, 0x06, 0xb1);
1362     if (rc < 0)
1363         return rc;
1364     rc = r820t_write_reg(priv, 0x05, 0x03);
1365     if (rc < 0)
1366         return rc;
1367     rc = r820t_write_reg(priv, 0x07, 0x3a);
1368     if (rc < 0)
1369         return rc;
1370     rc = r820t_write_reg(priv, 0x08, 0x40);
1371     if (rc < 0)
1372         return rc;
1373     rc = r820t_write_reg(priv, 0x09, 0xc0);
1374     if (rc < 0)
1375         return rc;
1376     rc = r820t_write_reg(priv, 0x0a, 0x36);
1377     if (rc < 0)
1378         return rc;
1379     rc = r820t_write_reg(priv, 0x0c, 0x35);
1380     if (rc < 0)
1381         return rc;
1382     rc = r820t_write_reg(priv, 0x0f, 0x68);
1383     if (rc < 0)
1384         return rc;
1385     rc = r820t_write_reg(priv, 0x11, 0x03);
1386     if (rc < 0)
1387         return rc;
1388     rc = r820t_write_reg(priv, 0x17, 0xf4);
1389     if (rc < 0)
1390         return rc;
1391     rc = r820t_write_reg(priv, 0x19, 0x0c);
1392 
1393     /* Force initial calibration */
1394     priv->type = -1;
1395 
1396     return rc;
1397 }
1398 
1399 /*
1400  * r820t device init logic
1401  */
1402 
1403 static int r820t_xtal_check(struct r820t_priv *priv)
1404 {
1405     int rc, i;
1406     u8 data[3], val;
1407 
1408     /* Initialize the shadow registers */
1409     memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1410 
1411     /* cap 30pF & Drive Low */
1412     rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
1413     if (rc < 0)
1414         return rc;
1415 
1416     /* set pll autotune = 128kHz */
1417     rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
1418     if (rc < 0)
1419         return rc;
1420 
1421     /* set manual initial reg = 111111;  */
1422     rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
1423     if (rc < 0)
1424         return rc;
1425 
1426     /* set auto */
1427     rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
1428     if (rc < 0)
1429         return rc;
1430 
1431     /* Try several xtal capacitor alternatives */
1432     for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
1433         rc = r820t_write_reg_mask(priv, 0x10,
1434                       r820t_xtal_capacitor[i][0], 0x1b);
1435         if (rc < 0)
1436             return rc;
1437 
1438         usleep_range(5000, 6000);
1439 
1440         rc = r820t_read(priv, 0x00, data, sizeof(data));
1441         if (rc < 0)
1442             return rc;
1443         if (!(data[2] & 0x40))
1444             continue;
1445 
1446         val = data[2] & 0x3f;
1447 
1448         if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
1449             break;
1450 
1451         if (val != 0x3f)
1452             break;
1453     }
1454 
1455     if (i == ARRAY_SIZE(r820t_xtal_capacitor))
1456         return -EINVAL;
1457 
1458     return r820t_xtal_capacitor[i][1];
1459 }
1460 
1461 static int r820t_imr_prepare(struct r820t_priv *priv)
1462 {
1463     int rc;
1464 
1465     /* Initialize the shadow registers */
1466     memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
1467 
1468     /* lna off (air-in off) */
1469     rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
1470     if (rc < 0)
1471         return rc;
1472 
1473     /* mixer gain mode = manual */
1474     rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
1475     if (rc < 0)
1476         return rc;
1477 
1478     /* filter corner = lowest */
1479     rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
1480     if (rc < 0)
1481         return rc;
1482 
1483     /* filter bw=+2cap, hp=5M */
1484     rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
1485     if (rc < 0)
1486         return rc;
1487 
1488     /* adc=on, vga code mode, gain = 26.5dB   */
1489     rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
1490     if (rc < 0)
1491         return rc;
1492 
1493     /* ring clk = on */
1494     rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
1495     if (rc < 0)
1496         return rc;
1497 
1498     /* ring power = on */
1499     rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
1500     if (rc < 0)
1501         return rc;
1502 
1503     /* from ring = ring pll in */
1504     rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
1505     if (rc < 0)
1506         return rc;
1507 
1508     /* sw_pdect = det3 */
1509     rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
1510     if (rc < 0)
1511         return rc;
1512 
1513     /* Set filt_3dB */
1514     rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
1515 
1516     return rc;
1517 }
1518 
1519 static int r820t_multi_read(struct r820t_priv *priv)
1520 {
1521     int rc, i;
1522     u16 sum = 0;
1523     u8 data[2], min = 255, max = 0;
1524 
1525     usleep_range(5000, 6000);
1526 
1527     for (i = 0; i < 6; i++) {
1528         rc = r820t_read(priv, 0x00, data, sizeof(data));
1529         if (rc < 0)
1530             return rc;
1531 
1532         sum += data[1];
1533 
1534         if (data[1] < min)
1535             min = data[1];
1536 
1537         if (data[1] > max)
1538             max = data[1];
1539     }
1540     rc = sum - max - min;
1541 
1542     return rc;
1543 }
1544 
1545 static int r820t_imr_cross(struct r820t_priv *priv,
1546                struct r820t_sect_type iq_point[3],
1547                u8 *x_direct)
1548 {
1549     struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
1550     struct r820t_sect_type tmp;
1551     int i, rc;
1552     u8 reg08, reg09;
1553 
1554     reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
1555     reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
1556 
1557     tmp.gain_x = 0;
1558     tmp.phase_y = 0;
1559     tmp.value = 255;
1560 
1561     for (i = 0; i < 5; i++) {
1562         switch (i) {
1563         case 0:
1564             cross[i].gain_x  = reg08;
1565             cross[i].phase_y = reg09;
1566             break;
1567         case 1:
1568             cross[i].gain_x  = reg08;       /* 0 */
1569             cross[i].phase_y = reg09 + 1;       /* Q-1 */
1570             break;
1571         case 2:
1572             cross[i].gain_x  = reg08;       /* 0 */
1573             cross[i].phase_y = (reg09 | 0x20) + 1;  /* I-1 */
1574             break;
1575         case 3:
1576             cross[i].gain_x  = reg08 + 1;       /* Q-1 */
1577             cross[i].phase_y = reg09;
1578             break;
1579         default:
1580             cross[i].gain_x  = (reg08 | 0x20) + 1;  /* I-1 */
1581             cross[i].phase_y = reg09;
1582         }
1583 
1584         rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
1585         if (rc < 0)
1586             return rc;
1587 
1588         rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
1589         if (rc < 0)
1590             return rc;
1591 
1592         rc = r820t_multi_read(priv);
1593         if (rc < 0)
1594             return rc;
1595 
1596         cross[i].value = rc;
1597 
1598         if (cross[i].value < tmp.value)
1599             tmp = cross[i];
1600     }
1601 
1602     if ((tmp.phase_y & 0x1f) == 1) {    /* y-direction */
1603         *x_direct = 0;
1604 
1605         iq_point[0] = cross[0];
1606         iq_point[1] = cross[1];
1607         iq_point[2] = cross[2];
1608     } else {                /* (0,0) or x-direction */
1609         *x_direct = 1;
1610 
1611         iq_point[0] = cross[0];
1612         iq_point[1] = cross[3];
1613         iq_point[2] = cross[4];
1614     }
1615     return 0;
1616 }
1617 
1618 static void r820t_compre_cor(struct r820t_sect_type iq[3])
1619 {
1620     int i;
1621 
1622     for (i = 3; i > 0; i--) {
1623         if (iq[0].value > iq[i - 1].value)
1624             swap(iq[0], iq[i - 1]);
1625     }
1626 }
1627 
1628 static int r820t_compre_step(struct r820t_priv *priv,
1629                  struct r820t_sect_type iq[3], u8 reg)
1630 {
1631     int rc;
1632     struct r820t_sect_type tmp;
1633 
1634     /*
1635      * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
1636      * with min value:
1637      *  new < min => update to min and continue
1638      *  new > min => Exit
1639      */
1640 
1641     /* min value already saved in iq[0] */
1642     tmp.phase_y = iq[0].phase_y;
1643     tmp.gain_x  = iq[0].gain_x;
1644 
1645     while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
1646           ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
1647         if (reg == 0x08)
1648             tmp.gain_x++;
1649         else
1650             tmp.phase_y++;
1651 
1652         rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
1653         if (rc < 0)
1654             return rc;
1655 
1656         rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
1657         if (rc < 0)
1658             return rc;
1659 
1660         rc = r820t_multi_read(priv);
1661         if (rc < 0)
1662             return rc;
1663         tmp.value = rc;
1664 
1665         if (tmp.value <= iq[0].value) {
1666             iq[0].gain_x  = tmp.gain_x;
1667             iq[0].phase_y = tmp.phase_y;
1668             iq[0].value   = tmp.value;
1669         } else {
1670             return 0;
1671         }
1672 
1673     }
1674 
1675     return 0;
1676 }
1677 
1678 static int r820t_iq_tree(struct r820t_priv *priv,
1679              struct r820t_sect_type iq[3],
1680              u8 fix_val, u8 var_val, u8 fix_reg)
1681 {
1682     int rc, i;
1683     u8 tmp, var_reg;
1684 
1685     /*
1686      * record IMC results by input gain/phase location then adjust
1687      * gain or phase positive 1 step and negative 1 step,
1688      * both record results
1689      */
1690 
1691     if (fix_reg == 0x08)
1692         var_reg = 0x09;
1693     else
1694         var_reg = 0x08;
1695 
1696     for (i = 0; i < 3; i++) {
1697         rc = r820t_write_reg(priv, fix_reg, fix_val);
1698         if (rc < 0)
1699             return rc;
1700 
1701         rc = r820t_write_reg(priv, var_reg, var_val);
1702         if (rc < 0)
1703             return rc;
1704 
1705         rc = r820t_multi_read(priv);
1706         if (rc < 0)
1707             return rc;
1708         iq[i].value = rc;
1709 
1710         if (fix_reg == 0x08) {
1711             iq[i].gain_x  = fix_val;
1712             iq[i].phase_y = var_val;
1713         } else {
1714             iq[i].phase_y = fix_val;
1715             iq[i].gain_x  = var_val;
1716         }
1717 
1718         if (i == 0) {  /* try right-side point */
1719             var_val++;
1720         } else if (i == 1) { /* try left-side point */
1721              /* if absolute location is 1, change I/Q direction */
1722             if ((var_val & 0x1f) < 0x02) {
1723                 tmp = 2 - (var_val & 0x1f);
1724 
1725                 /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
1726                 if (var_val & 0x20) {
1727                     var_val &= 0xc0;
1728                     var_val |= tmp;
1729                 } else {
1730                     var_val |= 0x20 | tmp;
1731                 }
1732             } else {
1733                 var_val -= 2;
1734             }
1735         }
1736     }
1737 
1738     return 0;
1739 }
1740 
1741 static int r820t_section(struct r820t_priv *priv,
1742              struct r820t_sect_type *iq_point)
1743 {
1744     int rc;
1745     struct r820t_sect_type compare_iq[3], compare_bet[3];
1746 
1747     /* Try X-1 column and save min result to compare_bet[0] */
1748     if (!(iq_point->gain_x & 0x1f))
1749         compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1;  /* Q-path, Gain=1 */
1750     else
1751         compare_iq[0].gain_x  = iq_point->gain_x - 1;  /* left point */
1752     compare_iq[0].phase_y = iq_point->phase_y;
1753 
1754     /* y-direction */
1755     rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1756             compare_iq[0].phase_y, 0x08);
1757     if (rc < 0)
1758         return rc;
1759 
1760     r820t_compre_cor(compare_iq);
1761 
1762     compare_bet[0] = compare_iq[0];
1763 
1764     /* Try X column and save min result to compare_bet[1] */
1765     compare_iq[0].gain_x  = iq_point->gain_x;
1766     compare_iq[0].phase_y = iq_point->phase_y;
1767 
1768     rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1769                compare_iq[0].phase_y, 0x08);
1770     if (rc < 0)
1771         return rc;
1772 
1773     r820t_compre_cor(compare_iq);
1774 
1775     compare_bet[1] = compare_iq[0];
1776 
1777     /* Try X+1 column and save min result to compare_bet[2] */
1778     if ((iq_point->gain_x & 0x1f) == 0x00)
1779         compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1;  /* I-path, Gain=1 */
1780     else
1781         compare_iq[0].gain_x = iq_point->gain_x + 1;
1782     compare_iq[0].phase_y = iq_point->phase_y;
1783 
1784     rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1785                compare_iq[0].phase_y, 0x08);
1786     if (rc < 0)
1787         return rc;
1788 
1789     r820t_compre_cor(compare_iq);
1790 
1791     compare_bet[2] = compare_iq[0];
1792 
1793     r820t_compre_cor(compare_bet);
1794 
1795     *iq_point = compare_bet[0];
1796 
1797     return 0;
1798 }
1799 
1800 static int r820t_vga_adjust(struct r820t_priv *priv)
1801 {
1802     int rc;
1803     u8 vga_count;
1804 
1805     /* increase vga power to let image significant */
1806     for (vga_count = 12; vga_count < 16; vga_count++) {
1807         rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
1808         if (rc < 0)
1809             return rc;
1810 
1811         usleep_range(10000, 11000);
1812 
1813         rc = r820t_multi_read(priv);
1814         if (rc < 0)
1815             return rc;
1816 
1817         if (rc > 40 * 4)
1818             break;
1819     }
1820 
1821     return 0;
1822 }
1823 
1824 static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1825 {
1826     struct r820t_sect_type compare_iq[3];
1827     int rc;
1828     u8 x_direction = 0;  /* 1:x, 0:y */
1829     u8 dir_reg, other_reg;
1830 
1831     r820t_vga_adjust(priv);
1832 
1833     rc = r820t_imr_cross(priv, compare_iq, &x_direction);
1834     if (rc < 0)
1835         return rc;
1836 
1837     if (x_direction == 1) {
1838         dir_reg   = 0x08;
1839         other_reg = 0x09;
1840     } else {
1841         dir_reg   = 0x09;
1842         other_reg = 0x08;
1843     }
1844 
1845     /* compare and find min of 3 points. determine i/q direction */
1846     r820t_compre_cor(compare_iq);
1847 
1848     /* increase step to find min value of this direction */
1849     rc = r820t_compre_step(priv, compare_iq, dir_reg);
1850     if (rc < 0)
1851         return rc;
1852 
1853     /* the other direction */
1854     rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1855                 compare_iq[0].phase_y, dir_reg);
1856     if (rc < 0)
1857         return rc;
1858 
1859     /* compare and find min of 3 points. determine i/q direction */
1860     r820t_compre_cor(compare_iq);
1861 
1862     /* increase step to find min value on this direction */
1863     rc = r820t_compre_step(priv, compare_iq, other_reg);
1864     if (rc < 0)
1865         return rc;
1866 
1867     /* check 3 points again */
1868     rc = r820t_iq_tree(priv, compare_iq,  compare_iq[0].gain_x,
1869                 compare_iq[0].phase_y, other_reg);
1870     if (rc < 0)
1871         return rc;
1872 
1873     r820t_compre_cor(compare_iq);
1874 
1875     /* section-9 check */
1876     rc = r820t_section(priv, compare_iq);
1877 
1878     *iq_pont = compare_iq[0];
1879 
1880     /* reset gain/phase control setting */
1881     rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
1882     if (rc < 0)
1883         return rc;
1884 
1885     rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
1886 
1887     return rc;
1888 }
1889 
1890 static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
1891 {
1892     int rc;
1893 
1894     r820t_vga_adjust(priv);
1895 
1896     /*
1897      * search surrounding points from previous point
1898      * try (x-1), (x), (x+1) columns, and find min IMR result point
1899      */
1900     rc = r820t_section(priv, iq_pont);
1901     if (rc < 0)
1902         return rc;
1903 
1904     return 0;
1905 }
1906 
1907 static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
1908 {
1909     struct r820t_sect_type imr_point;
1910     int rc;
1911     u32 ring_vco, ring_freq, ring_ref;
1912     u8 n_ring, n;
1913     int reg18, reg19, reg1f;
1914 
1915     if (priv->cfg->xtal > 24000000)
1916         ring_ref = priv->cfg->xtal / 2000;
1917     else
1918         ring_ref = priv->cfg->xtal / 1000;
1919 
1920     n_ring = 15;
1921     for (n = 0; n < 16; n++) {
1922         if ((16 + n) * 8 * ring_ref >= 3100000) {
1923             n_ring = n;
1924             break;
1925         }
1926     }
1927 
1928     reg18 = r820t_read_cache_reg(priv, 0x18);
1929     reg19 = r820t_read_cache_reg(priv, 0x19);
1930     reg1f = r820t_read_cache_reg(priv, 0x1f);
1931 
1932     reg18 &= 0xf0;      /* set ring[3:0] */
1933     reg18 |= n_ring;
1934 
1935     ring_vco = (16 + n_ring) * 8 * ring_ref;
1936 
1937     reg18 &= 0xdf;   /* clear ring_se23 */
1938     reg19 &= 0xfc;   /* clear ring_seldiv */
1939     reg1f &= 0xfc;   /* clear ring_att */
1940 
1941     switch (imr_mem) {
1942     case 0:
1943         ring_freq = ring_vco / 48;
1944         reg18 |= 0x20;  /* ring_se23 = 1 */
1945         reg19 |= 0x03;  /* ring_seldiv = 3 */
1946         reg1f |= 0x02;  /* ring_att 10 */
1947         break;
1948     case 1:
1949         ring_freq = ring_vco / 16;
1950         reg18 |= 0x00;  /* ring_se23 = 0 */
1951         reg19 |= 0x02;  /* ring_seldiv = 2 */
1952         reg1f |= 0x00;  /* pw_ring 00 */
1953         break;
1954     case 2:
1955         ring_freq = ring_vco / 8;
1956         reg18 |= 0x00;  /* ring_se23 = 0 */
1957         reg19 |= 0x01;  /* ring_seldiv = 1 */
1958         reg1f |= 0x03;  /* pw_ring 11 */
1959         break;
1960     case 3:
1961         ring_freq = ring_vco / 6;
1962         reg18 |= 0x20;  /* ring_se23 = 1 */
1963         reg19 |= 0x00;  /* ring_seldiv = 0 */
1964         reg1f |= 0x03;  /* pw_ring 11 */
1965         break;
1966     case 4:
1967         ring_freq = ring_vco / 4;
1968         reg18 |= 0x00;  /* ring_se23 = 0 */
1969         reg19 |= 0x00;  /* ring_seldiv = 0 */
1970         reg1f |= 0x01;  /* pw_ring 01 */
1971         break;
1972     default:
1973         ring_freq = ring_vco / 4;
1974         reg18 |= 0x00;  /* ring_se23 = 0 */
1975         reg19 |= 0x00;  /* ring_seldiv = 0 */
1976         reg1f |= 0x01;  /* pw_ring 01 */
1977         break;
1978     }
1979 
1980 
1981     /* write pw_ring, n_ring, ringdiv2 registers */
1982 
1983     /* n_ring, ring_se23 */
1984     rc = r820t_write_reg(priv, 0x18, reg18);
1985     if (rc < 0)
1986         return rc;
1987 
1988     /* ring_sediv */
1989     rc = r820t_write_reg(priv, 0x19, reg19);
1990     if (rc < 0)
1991         return rc;
1992 
1993     /* pw_ring */
1994     rc = r820t_write_reg(priv, 0x1f, reg1f);
1995     if (rc < 0)
1996         return rc;
1997 
1998     /* mux input freq ~ rf_in freq */
1999     rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
2000     if (rc < 0)
2001         return rc;
2002 
2003     rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
2004                (ring_freq - 5300) * 1000);
2005     if (!priv->has_lock)
2006         rc = -EINVAL;
2007     if (rc < 0)
2008         return rc;
2009 
2010     if (im_flag) {
2011         rc = r820t_iq(priv, &imr_point);
2012     } else {
2013         imr_point.gain_x  = priv->imr_data[3].gain_x;
2014         imr_point.phase_y = priv->imr_data[3].phase_y;
2015         imr_point.value   = priv->imr_data[3].value;
2016 
2017         rc = r820t_f_imr(priv, &imr_point);
2018     }
2019     if (rc < 0)
2020         return rc;
2021 
2022     /* save IMR value */
2023     switch (imr_mem) {
2024     case 0:
2025         priv->imr_data[0].gain_x  = imr_point.gain_x;
2026         priv->imr_data[0].phase_y = imr_point.phase_y;
2027         priv->imr_data[0].value   = imr_point.value;
2028         break;
2029     case 1:
2030         priv->imr_data[1].gain_x  = imr_point.gain_x;
2031         priv->imr_data[1].phase_y = imr_point.phase_y;
2032         priv->imr_data[1].value   = imr_point.value;
2033         break;
2034     case 2:
2035         priv->imr_data[2].gain_x  = imr_point.gain_x;
2036         priv->imr_data[2].phase_y = imr_point.phase_y;
2037         priv->imr_data[2].value   = imr_point.value;
2038         break;
2039     case 3:
2040         priv->imr_data[3].gain_x  = imr_point.gain_x;
2041         priv->imr_data[3].phase_y = imr_point.phase_y;
2042         priv->imr_data[3].value   = imr_point.value;
2043         break;
2044     case 4:
2045         priv->imr_data[4].gain_x  = imr_point.gain_x;
2046         priv->imr_data[4].phase_y = imr_point.phase_y;
2047         priv->imr_data[4].value   = imr_point.value;
2048         break;
2049     default:
2050         priv->imr_data[4].gain_x  = imr_point.gain_x;
2051         priv->imr_data[4].phase_y = imr_point.phase_y;
2052         priv->imr_data[4].value   = imr_point.value;
2053         break;
2054     }
2055 
2056     return 0;
2057 }
2058 
2059 static int r820t_imr_callibrate(struct r820t_priv *priv)
2060 {
2061     int rc, i;
2062     int xtal_cap = 0;
2063 
2064     if (priv->init_done)
2065         return 0;
2066 
2067     /* Detect Xtal capacitance */
2068     if ((priv->cfg->rafael_chip == CHIP_R820T) ||
2069         (priv->cfg->rafael_chip == CHIP_R828S) ||
2070         (priv->cfg->rafael_chip == CHIP_R820C)) {
2071         priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
2072     } else {
2073         /* Initialize registers */
2074         rc = r820t_write(priv, 0x05,
2075                 r820t_init_array, sizeof(r820t_init_array));
2076         if (rc < 0)
2077             return rc;
2078         for (i = 0; i < 3; i++) {
2079             rc = r820t_xtal_check(priv);
2080             if (rc < 0)
2081                 return rc;
2082             if (!i || rc > xtal_cap)
2083                 xtal_cap = rc;
2084         }
2085         priv->xtal_cap_sel = xtal_cap;
2086     }
2087 
2088     /*
2089      * Disables IMR calibration. That emulates the same behaviour
2090      * as what is done by rtl-sdr userspace library. Useful for testing
2091      */
2092     if (no_imr_cal) {
2093         priv->init_done = true;
2094 
2095         return 0;
2096     }
2097 
2098     /* Initialize registers */
2099     rc = r820t_write(priv, 0x05,
2100              r820t_init_array, sizeof(r820t_init_array));
2101     if (rc < 0)
2102         return rc;
2103 
2104     rc = r820t_imr_prepare(priv);
2105     if (rc < 0)
2106         return rc;
2107 
2108     rc = r820t_imr(priv, 3, true);
2109     if (rc < 0)
2110         return rc;
2111     rc = r820t_imr(priv, 1, false);
2112     if (rc < 0)
2113         return rc;
2114     rc = r820t_imr(priv, 0, false);
2115     if (rc < 0)
2116         return rc;
2117     rc = r820t_imr(priv, 2, false);
2118     if (rc < 0)
2119         return rc;
2120     rc = r820t_imr(priv, 4, false);
2121     if (rc < 0)
2122         return rc;
2123 
2124     priv->init_done = true;
2125     priv->imr_done = true;
2126 
2127     return 0;
2128 }
2129 
2130 #if 0
2131 /* Not used, for now */
2132 static int r820t_gpio(struct r820t_priv *priv, bool enable)
2133 {
2134     return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
2135 }
2136 #endif
2137 
2138 /*
2139  *  r820t frontend operations and tuner attach code
2140  *
2141  * All driver locks and i2c control are only in this part of the code
2142  */
2143 
2144 static int r820t_init(struct dvb_frontend *fe)
2145 {
2146     struct r820t_priv *priv = fe->tuner_priv;
2147     int rc;
2148 
2149     tuner_dbg("%s:\n", __func__);
2150 
2151     mutex_lock(&priv->lock);
2152     if (fe->ops.i2c_gate_ctrl)
2153         fe->ops.i2c_gate_ctrl(fe, 1);
2154 
2155     rc = r820t_imr_callibrate(priv);
2156     if (rc < 0)
2157         goto err;
2158 
2159     /* Initialize registers */
2160     rc = r820t_write(priv, 0x05,
2161              r820t_init_array, sizeof(r820t_init_array));
2162 
2163 err:
2164     if (fe->ops.i2c_gate_ctrl)
2165         fe->ops.i2c_gate_ctrl(fe, 0);
2166     mutex_unlock(&priv->lock);
2167 
2168     if (rc < 0)
2169         tuner_dbg("%s: failed=%d\n", __func__, rc);
2170     return rc;
2171 }
2172 
2173 static int r820t_sleep(struct dvb_frontend *fe)
2174 {
2175     struct r820t_priv *priv = fe->tuner_priv;
2176     int rc;
2177 
2178     tuner_dbg("%s:\n", __func__);
2179 
2180     mutex_lock(&priv->lock);
2181     if (fe->ops.i2c_gate_ctrl)
2182         fe->ops.i2c_gate_ctrl(fe, 1);
2183 
2184     rc = r820t_standby(priv);
2185 
2186     if (fe->ops.i2c_gate_ctrl)
2187         fe->ops.i2c_gate_ctrl(fe, 0);
2188     mutex_unlock(&priv->lock);
2189 
2190     tuner_dbg("%s: failed=%d\n", __func__, rc);
2191     return rc;
2192 }
2193 
2194 static int r820t_set_analog_freq(struct dvb_frontend *fe,
2195                  struct analog_parameters *p)
2196 {
2197     struct r820t_priv *priv = fe->tuner_priv;
2198     unsigned bw;
2199     int rc;
2200 
2201     tuner_dbg("%s called\n", __func__);
2202 
2203     /* if std is not defined, choose one */
2204     if (!p->std)
2205         p->std = V4L2_STD_MN;
2206 
2207     if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
2208         bw = 6;
2209     else
2210         bw = 8;
2211 
2212     mutex_lock(&priv->lock);
2213     if (fe->ops.i2c_gate_ctrl)
2214         fe->ops.i2c_gate_ctrl(fe, 1);
2215 
2216     rc = generic_set_freq(fe, 62500l * p->frequency, bw,
2217                   V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
2218 
2219     if (fe->ops.i2c_gate_ctrl)
2220         fe->ops.i2c_gate_ctrl(fe, 0);
2221     mutex_unlock(&priv->lock);
2222 
2223     return rc;
2224 }
2225 
2226 static int r820t_set_params(struct dvb_frontend *fe)
2227 {
2228     struct r820t_priv *priv = fe->tuner_priv;
2229     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
2230     int rc;
2231     unsigned bw;
2232 
2233     tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
2234         __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
2235 
2236     mutex_lock(&priv->lock);
2237     if (fe->ops.i2c_gate_ctrl)
2238         fe->ops.i2c_gate_ctrl(fe, 1);
2239 
2240     bw = (c->bandwidth_hz + 500000) / 1000000;
2241     if (!bw)
2242         bw = 8;
2243 
2244     rc = generic_set_freq(fe, c->frequency, bw,
2245                   V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
2246 
2247     if (fe->ops.i2c_gate_ctrl)
2248         fe->ops.i2c_gate_ctrl(fe, 0);
2249     mutex_unlock(&priv->lock);
2250 
2251     if (rc)
2252         tuner_dbg("%s: failed=%d\n", __func__, rc);
2253     return rc;
2254 }
2255 
2256 static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
2257 {
2258     struct r820t_priv *priv = fe->tuner_priv;
2259     int rc = 0;
2260 
2261     mutex_lock(&priv->lock);
2262     if (fe->ops.i2c_gate_ctrl)
2263         fe->ops.i2c_gate_ctrl(fe, 1);
2264 
2265     if (priv->has_lock) {
2266         rc = r820t_read_gain(priv);
2267         if (rc < 0)
2268             goto err;
2269 
2270         /* A higher gain at LNA means a lower signal strength */
2271         *strength = (45 - rc) << 4 | 0xff;
2272         if (*strength == 0xff)
2273             *strength = 0;
2274     } else {
2275         *strength = 0;
2276     }
2277 
2278 err:
2279     if (fe->ops.i2c_gate_ctrl)
2280         fe->ops.i2c_gate_ctrl(fe, 0);
2281     mutex_unlock(&priv->lock);
2282 
2283     tuner_dbg("%s: %s, gain=%d strength=%d\n",
2284           __func__,
2285           priv->has_lock ? "PLL locked" : "no signal",
2286           rc, *strength);
2287 
2288     return 0;
2289 }
2290 
2291 static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
2292 {
2293     struct r820t_priv *priv = fe->tuner_priv;
2294 
2295     tuner_dbg("%s:\n", __func__);
2296 
2297     *frequency = priv->int_freq;
2298 
2299     return 0;
2300 }
2301 
2302 static void r820t_release(struct dvb_frontend *fe)
2303 {
2304     struct r820t_priv *priv = fe->tuner_priv;
2305 
2306     tuner_dbg("%s:\n", __func__);
2307 
2308     mutex_lock(&r820t_list_mutex);
2309 
2310     if (priv)
2311         hybrid_tuner_release_state(priv);
2312 
2313     mutex_unlock(&r820t_list_mutex);
2314 
2315     fe->tuner_priv = NULL;
2316 }
2317 
2318 static const struct dvb_tuner_ops r820t_tuner_ops = {
2319     .info = {
2320         .name             = "Rafael Micro R820T",
2321         .frequency_min_hz =   42 * MHz,
2322         .frequency_max_hz = 1002 * MHz,
2323     },
2324     .init = r820t_init,
2325     .release = r820t_release,
2326     .sleep = r820t_sleep,
2327     .set_params = r820t_set_params,
2328     .set_analog_params = r820t_set_analog_freq,
2329     .get_if_frequency = r820t_get_if_frequency,
2330     .get_rf_strength = r820t_signal,
2331 };
2332 
2333 struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
2334                   struct i2c_adapter *i2c,
2335                   const struct r820t_config *cfg)
2336 {
2337     struct r820t_priv *priv;
2338     int rc = -ENODEV;
2339     u8 data[5];
2340     int instance;
2341 
2342     mutex_lock(&r820t_list_mutex);
2343 
2344     instance = hybrid_tuner_request_state(struct r820t_priv, priv,
2345                           hybrid_tuner_instance_list,
2346                           i2c, cfg->i2c_addr,
2347                           "r820t");
2348     switch (instance) {
2349     case 0:
2350         /* memory allocation failure */
2351         goto err_no_gate;
2352     case 1:
2353         /* new tuner instance */
2354         priv->cfg = cfg;
2355 
2356         mutex_init(&priv->lock);
2357 
2358         fe->tuner_priv = priv;
2359         break;
2360     case 2:
2361         /* existing tuner instance */
2362         fe->tuner_priv = priv;
2363         break;
2364     }
2365 
2366     if (fe->ops.i2c_gate_ctrl)
2367         fe->ops.i2c_gate_ctrl(fe, 1);
2368 
2369     /* check if the tuner is there */
2370     rc = r820t_read(priv, 0x00, data, sizeof(data));
2371     if (rc < 0)
2372         goto err;
2373 
2374     rc = r820t_sleep(fe);
2375     if (rc < 0)
2376         goto err;
2377 
2378     tuner_info(
2379         "Rafael Micro r820t successfully identified, chip type: %s\n",
2380         r820t_chip_enum_to_str(cfg->rafael_chip));
2381 
2382     if (fe->ops.i2c_gate_ctrl)
2383         fe->ops.i2c_gate_ctrl(fe, 0);
2384 
2385     mutex_unlock(&r820t_list_mutex);
2386 
2387     memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
2388             sizeof(struct dvb_tuner_ops));
2389 
2390     return fe;
2391 err:
2392     if (fe->ops.i2c_gate_ctrl)
2393         fe->ops.i2c_gate_ctrl(fe, 0);
2394 
2395 err_no_gate:
2396     mutex_unlock(&r820t_list_mutex);
2397 
2398     pr_info("%s: failed=%d\n", __func__, rc);
2399     r820t_release(fe);
2400     return NULL;
2401 }
2402 EXPORT_SYMBOL_GPL(r820t_attach);
2403 
2404 MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
2405 MODULE_AUTHOR("Mauro Carvalho Chehab");
2406 MODULE_LICENSE("GPL v2");
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