OSCL-LXR |
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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Driver for Microtune MT2060 "Single chip dual conversion broadband tuner" 0004 * 0005 * Copyright (c) 2006 Olivier DANET <odanet@caramail.com> 0006 */ 0007 0008 #ifndef MT2060_PRIV_H 0009 #define MT2060_PRIV_H 0010 0011 // Uncomment the #define below to enable spurs checking. The results where quite unconvincing. 0012 // #define MT2060_SPURCHECK 0013 0014 /* This driver is based on the information available in the datasheet of the 0015 "Comtech SDVBT-3K6M" tuner ( K1000737843.pdf ) which features the MT2060 register map : 0016 0017 I2C Address : 0x60 0018 0019 Reg.No | B7 | B6 | B5 | B4 | B3 | B2 | B1 | B0 | ( defaults ) 0020 -------------------------------------------------------------------------------- 0021 00 | [ PART ] | [ REV ] | R = 0x63 0022 01 | [ LNABAND ] | [ NUM1(5:2) ] | RW = 0x3F 0023 02 | [ DIV1 ] | RW = 0x74 0024 03 | FM1CA | FM1SS | [ NUM1(1:0) ] | [ NUM2(3:0) ] | RW = 0x00 0025 04 | NUM2(11:4) ] | RW = 0x08 0026 05 | [ DIV2 ] |NUM2(12)| RW = 0x93 0027 06 | L1LK | [ TAD1 ] | L2LK | [ TAD2 ] | R 0028 07 | [ FMF ] | R 0029 08 | ? | FMCAL | ? | ? | ? | ? | ? | TEMP | R 0030 09 | 0 | 0 | [ FMGC ] | 0 | GP02 | GP01 | 0 | RW = 0x20 0031 0A | ?? 0032 0B | 0 | 0 | 1 | 1 | 0 | 0 | [ VGAG ] | RW = 0x30 0033 0C | V1CSE | 1 | 1 | 1 | 1 | 1 | 1 | 1 | RW = 0xFF 0034 0D | 1 | 0 | [ V1CS ] | RW = 0xB0 0035 0E | ?? 0036 0F | ?? 0037 10 | ?? 0038 11 | [ LOTO ] | 0 | 0 | 1 | 0 | RW = 0x42 0039 0040 PART : Part code : 6 for MT2060 0041 REV : Revision code : 3 for current revision 0042 LNABAND : Input frequency range : ( See code for details ) 0043 NUM1 / DIV1 / NUM2 / DIV2 : Frequencies programming ( See code for details ) 0044 FM1CA : Calibration Start Bit 0045 FM1SS : Calibration Single Step bit 0046 L1LK : LO1 Lock Detect 0047 TAD1 : Tune Line ADC ( ? ) 0048 L2LK : LO2 Lock Detect 0049 TAD2 : Tune Line ADC ( ? ) 0050 FMF : Estimated first IF Center frequency Offset ( ? ) 0051 FM1CAL : Calibration done bit 0052 TEMP : On chip temperature sensor 0053 FMCG : Mixer 1 Cap Gain ( ? ) 0054 GP01 / GP02 : Programmable digital outputs. Unconnected pins ? 0055 V1CSE : LO1 VCO Automatic Capacitor Select Enable ( ? ) 0056 V1CS : LO1 Capacitor Selection Value ( ? ) 0057 LOTO : LO Timeout ( ? ) 0058 VGAG : Tuner Output gain 0059 */ 0060 0061 #define I2C_ADDRESS 0x60 0062 0063 #define REG_PART_REV 0 0064 #define REG_LO1C1 1 0065 #define REG_LO1C2 2 0066 #define REG_LO2C1 3 0067 #define REG_LO2C2 4 0068 #define REG_LO2C3 5 0069 #define REG_LO_STATUS 6 0070 #define REG_FM_FREQ 7 0071 #define REG_MISC_STAT 8 0072 #define REG_MISC_CTRL 9 0073 #define REG_RESERVED_A 0x0A 0074 #define REG_VGAG 0x0B 0075 #define REG_LO1B1 0x0C 0076 #define REG_LO1B2 0x0D 0077 #define REG_LOTO 0x11 0078 0079 #define PART_REV 0x63 // The current driver works only with PART=6 and REV=3 chips 0080 0081 struct mt2060_priv { 0082 struct mt2060_config *cfg; 0083 struct i2c_adapter *i2c; 0084 struct i2c_client *client; 0085 struct mt2060_config config; 0086 0087 u8 i2c_max_regs; 0088 u32 frequency; 0089 u16 if1_freq; 0090 u8 fmfreq; 0091 0092 /* 0093 * Use REG_MISC_CTRL register for sleep. That drops sleep power usage 0094 * about 0.9W (huge!). Register bit meanings are unknown, so let it be 0095 * disabled by default to avoid possible regression. Convert driver to 0096 * i2c model in order to enable it. 0097 */ 0098 bool sleep; 0099 }; 0100 0101 #endif
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