media/tuners/max2165.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  Driver for Maxim MAX2165 silicon tuner
0004  *
0005  *  Copyright (c) 2009 David T. L. Wong <davidtlwong@gmail.com>
0006  */
0007
0008 #include <linux/module.h>
0009 #include <linux/moduleparam.h>
0010 #include <linux/videodev2.h>
0011 #include <linux/delay.h>
0012 #include <linux/dvb/frontend.h>
0013 #include <linux/i2c.h>
0014 #include <linux/slab.h>
0015
0016 #include <media/dvb_frontend.h>
0017
0018 #include "max2165.h"
0019 #include "max2165_priv.h"
0020 #include "tuner-i2c.h"
0021
0022 #define dprintk(args...) \
0023     do { \
0024         if (debug) \
0025             printk(KERN_DEBUG "max2165: " args); \
0026     } while (0)
0027
0028 static int debug;
0029 module_param(debug, int, 0644);
0030 MODULE_PARM_DESC(debug, "Turn on/off debugging (default:off).");
0031
0032 static int max2165_write_reg(struct max2165_priv *priv, u8 reg, u8 data)
0033 {
0034     int ret;
0035     u8 buf[] = { reg, data };
0036     struct i2c_msg msg = { .flags = 0, .buf = buf, .len = 2 };
0037
0038     msg.addr = priv->config->i2c_address;
0039
0040     if (debug >= 2)
0041         dprintk("%s: reg=0x%02X, data=0x%02X\n", __func__, reg, data);
0042
0043     ret = i2c_transfer(priv->i2c, &msg, 1);
0044
0045     if (ret != 1)
0046         dprintk("%s: error reg=0x%x, data=0x%x, ret=%i\n",
0047             __func__, reg, data, ret);
0048
0049     return (ret != 1) ? -EIO : 0;
0050 }
0051
0052 static int max2165_read_reg(struct max2165_priv *priv, u8 reg, u8 *p_data)
0053 {
0054     int ret;
0055     u8 dev_addr = priv->config->i2c_address;
0056
0057     u8 b0[] = { reg };
0058     u8 b1[] = { 0 };
0059     struct i2c_msg msg[] = {
0060         { .addr = dev_addr, .flags = 0, .buf = b0, .len = 1 },
0061         { .addr = dev_addr, .flags = I2C_M_RD, .buf = b1, .len = 1 },
0062     };
0063
0064     ret = i2c_transfer(priv->i2c, msg, 2);
0065     if (ret != 2) {
0066         dprintk("%s: error reg=0x%x, ret=%i\n", __func__, reg, ret);
0067         return -EIO;
0068     }
0069
0070     *p_data = b1[0];
0071     if (debug >= 2)
0072         dprintk("%s: reg=0x%02X, data=0x%02X\n",
0073             __func__, reg, b1[0]);
0074     return 0;
0075 }
0076
0077 static int max2165_mask_write_reg(struct max2165_priv *priv, u8 reg,
0078     u8 mask, u8 data)
0079 {
0080     int ret;
0081     u8 v;
0082
0083     data &= mask;
0084     ret = max2165_read_reg(priv, reg, &v);
0085     if (ret != 0)
0086         return ret;
0087     v &= ~mask;
0088     v |= data;
0089     ret = max2165_write_reg(priv, reg, v);
0090
0091     return ret;
0092 }
0093
0094 static int max2165_read_rom_table(struct max2165_priv *priv)
0095 {
0096     u8 dat[3];
0097     int i;
0098
0099     for (i = 0; i < 3; i++) {
0100         max2165_write_reg(priv, REG_ROM_TABLE_ADDR, i + 1);
0101         max2165_read_reg(priv, REG_ROM_TABLE_DATA, &dat[i]);
0102     }
0103
0104     priv->tf_ntch_low_cfg = dat[0] >> 4;
0105     priv->tf_ntch_hi_cfg = dat[0] & 0x0F;
0106     priv->tf_balun_low_ref = dat[1] & 0x0F;
0107     priv->tf_balun_hi_ref = dat[1] >> 4;
0108     priv->bb_filter_7mhz_cfg = dat[2] & 0x0F;
0109     priv->bb_filter_8mhz_cfg = dat[2] >> 4;
0110
0111     dprintk("tf_ntch_low_cfg = 0x%X\n", priv->tf_ntch_low_cfg);
0112     dprintk("tf_ntch_hi_cfg = 0x%X\n", priv->tf_ntch_hi_cfg);
0113     dprintk("tf_balun_low_ref = 0x%X\n", priv->tf_balun_low_ref);
0114     dprintk("tf_balun_hi_ref = 0x%X\n", priv->tf_balun_hi_ref);
0115     dprintk("bb_filter_7mhz_cfg = 0x%X\n", priv->bb_filter_7mhz_cfg);
0116     dprintk("bb_filter_8mhz_cfg = 0x%X\n", priv->bb_filter_8mhz_cfg);
0117
0118     return 0;
0119 }
0120
0121 static int max2165_set_osc(struct max2165_priv *priv, u8 osc /*MHz*/)
0122 {
0123     u8 v;
0124
0125     v = (osc / 2);
0126     if (v == 2)
0127         v = 0x7;
0128     else
0129         v -= 8;
0130
0131     max2165_mask_write_reg(priv, REG_PLL_CFG, 0x07, v);
0132
0133     return 0;
0134 }
0135
0136 static int max2165_set_bandwidth(struct max2165_priv *priv, u32 bw)
0137 {
0138     u8 val;
0139
0140     if (bw == 8000000)
0141         val = priv->bb_filter_8mhz_cfg;
0142     else
0143         val = priv->bb_filter_7mhz_cfg;
0144
0145     max2165_mask_write_reg(priv, REG_BASEBAND_CTRL, 0xF0, val << 4);
0146
0147     return 0;
0148 }
0149
0150 static int fixpt_div32(u32 dividend, u32 divisor, u32 *quotient, u32 *fraction)
0151 {
0152     u32 remainder;
0153     u32 q, f = 0;
0154     int i;
0155
0156     if (0 == divisor)
0157         return -EINVAL;
0158
0159     q = dividend / divisor;
0160     remainder = dividend - q * divisor;
0161
0162     for (i = 0; i < 31; i++) {
0163         remainder <<= 1;
0164         if (remainder >= divisor) {
0165             f += 1;
0166             remainder -= divisor;
0167         }
0168         f <<= 1;
0169     }
0170
0171     *quotient = q;
0172     *fraction = f;
0173
0174     return 0;
0175 }
0176
0177 static int max2165_set_rf(struct max2165_priv *priv, u32 freq)
0178 {
0179     u8 tf;
0180     u8 tf_ntch;
0181     u32 t;
0182     u32 quotient, fraction;
0183     int ret;
0184
0185     /* Set PLL divider according to RF frequency */
0186     ret = fixpt_div32(freq / 1000, priv->config->osc_clk * 1000,
0187              &quotient, &fraction);
0188     if (ret != 0)
0189         return ret;
0190
0191     /* 20-bit fraction */
0192     fraction >>= 12;
0193
0194     max2165_write_reg(priv, REG_NDIV_INT, quotient);
0195     max2165_mask_write_reg(priv, REG_NDIV_FRAC2, 0x0F, fraction >> 16);
0196     max2165_write_reg(priv, REG_NDIV_FRAC1, fraction >> 8);
0197     max2165_write_reg(priv, REG_NDIV_FRAC0, fraction);
0198
0199     /* Norch Filter */
0200     tf_ntch = (freq < 725000000) ?
0201         priv->tf_ntch_low_cfg : priv->tf_ntch_hi_cfg;
0202
0203     /* Tracking filter balun */
0204     t = priv->tf_balun_low_ref;
0205     t += (priv->tf_balun_hi_ref - priv->tf_balun_low_ref)
0206         * (freq / 1000 - 470000) / (780000 - 470000);
0207
0208     tf = t;
0209     dprintk("tf = %X\n", tf);
0210     tf |= tf_ntch << 4;
0211
0212     max2165_write_reg(priv, REG_TRACK_FILTER, tf);
0213
0214     return 0;
0215 }
0216
0217 static void max2165_debug_status(struct max2165_priv *priv)
0218 {
0219     u8 status, autotune;
0220     u8 auto_vco_success, auto_vco_active;
0221     u8 pll_locked;
0222     u8 dc_offset_low, dc_offset_hi;
0223     u8 signal_lv_over_threshold;
0224     u8 vco, vco_sub_band, adc;
0225
0226     max2165_read_reg(priv, REG_STATUS, &status);
0227     max2165_read_reg(priv, REG_AUTOTUNE, &autotune);
0228
0229     auto_vco_success = (status >> 6) & 0x01;
0230     auto_vco_active = (status >> 5) & 0x01;
0231     pll_locked = (status >> 4) & 0x01;
0232     dc_offset_low = (status >> 3) & 0x01;
0233     dc_offset_hi = (status >> 2) & 0x01;
0234     signal_lv_over_threshold = status & 0x01;
0235
0236     vco = autotune >> 6;
0237     vco_sub_band = (autotune >> 3) & 0x7;
0238     adc = autotune & 0x7;
0239
0240     dprintk("auto VCO active: %d, auto VCO success: %d\n",
0241         auto_vco_active, auto_vco_success);
0242     dprintk("PLL locked: %d\n", pll_locked);
0243     dprintk("DC offset low: %d, DC offset high: %d\n",
0244         dc_offset_low, dc_offset_hi);
0245     dprintk("Signal lvl over threshold: %d\n", signal_lv_over_threshold);
0246     dprintk("VCO: %d, VCO Sub-band: %d, ADC: %d\n", vco, vco_sub_band, adc);
0247 }
0248
0249 static int max2165_set_params(struct dvb_frontend *fe)
0250 {
0251     struct max2165_priv *priv = fe->tuner_priv;
0252     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0253     int ret;
0254
0255     switch (c->bandwidth_hz) {
0256     case 7000000:
0257     case 8000000:
0258         priv->frequency = c->frequency;
0259         break;
0260     default:
0261         printk(KERN_INFO "MAX2165: bandwidth %d Hz not supported.\n",
0262                c->bandwidth_hz);
0263         return -EINVAL;
0264     }
0265
0266     dprintk("%s() frequency=%d\n", __func__, c->frequency);
0267
0268     if (fe->ops.i2c_gate_ctrl)
0269         fe->ops.i2c_gate_ctrl(fe, 1);
0270     max2165_set_bandwidth(priv, c->bandwidth_hz);
0271     ret = max2165_set_rf(priv, priv->frequency);
0272     mdelay(50);
0273     max2165_debug_status(priv);
0274     if (fe->ops.i2c_gate_ctrl)
0275         fe->ops.i2c_gate_ctrl(fe, 0);
0276
0277     if (ret != 0)
0278         return -EREMOTEIO;
0279
0280     return 0;
0281 }
0282
0283 static int max2165_get_frequency(struct dvb_frontend *fe, u32 *freq)
0284 {
0285     struct max2165_priv *priv = fe->tuner_priv;
0286     dprintk("%s()\n", __func__);
0287     *freq = priv->frequency;
0288     return 0;
0289 }
0290
0291 static int max2165_get_bandwidth(struct dvb_frontend *fe, u32 *bw)
0292 {
0293     struct max2165_priv *priv = fe->tuner_priv;
0294     dprintk("%s()\n", __func__);
0295
0296     *bw = priv->bandwidth;
0297     return 0;
0298 }
0299
0300 static int max2165_get_status(struct dvb_frontend *fe, u32 *status)
0301 {
0302     struct max2165_priv *priv = fe->tuner_priv;
0303     u16 lock_status = 0;
0304
0305     dprintk("%s()\n", __func__);
0306
0307     if (fe->ops.i2c_gate_ctrl)
0308             fe->ops.i2c_gate_ctrl(fe, 1);
0309
0310     max2165_debug_status(priv);
0311     *status = lock_status;
0312
0313     if (fe->ops.i2c_gate_ctrl)
0314             fe->ops.i2c_gate_ctrl(fe, 0);
0315
0316     return 0;
0317 }
0318
0319 static int max2165_sleep(struct dvb_frontend *fe)
0320 {
0321     dprintk("%s()\n", __func__);
0322     return 0;
0323 }
0324
0325 static int max2165_init(struct dvb_frontend *fe)
0326 {
0327     struct max2165_priv *priv = fe->tuner_priv;
0328     dprintk("%s()\n", __func__);
0329
0330     if (fe->ops.i2c_gate_ctrl)
0331         fe->ops.i2c_gate_ctrl(fe, 1);
0332
0333     /* Setup initial values */
0334     /* Fractional Mode on */
0335     max2165_write_reg(priv, REG_NDIV_FRAC2, 0x18);
0336     /* LNA on */
0337     max2165_write_reg(priv, REG_LNA, 0x01);
0338     max2165_write_reg(priv, REG_PLL_CFG, 0x7A);
0339     max2165_write_reg(priv, REG_TEST, 0x08);
0340     max2165_write_reg(priv, REG_SHUTDOWN, 0x40);
0341     max2165_write_reg(priv, REG_VCO_CTRL, 0x84);
0342     max2165_write_reg(priv, REG_BASEBAND_CTRL, 0xC3);
0343     max2165_write_reg(priv, REG_DC_OFFSET_CTRL, 0x75);
0344     max2165_write_reg(priv, REG_DC_OFFSET_DAC, 0x00);
0345     max2165_write_reg(priv, REG_ROM_TABLE_ADDR, 0x00);
0346
0347     max2165_set_osc(priv, priv->config->osc_clk);
0348
0349     max2165_read_rom_table(priv);
0350
0351     max2165_set_bandwidth(priv, 8000000);
0352
0353     if (fe->ops.i2c_gate_ctrl)
0354             fe->ops.i2c_gate_ctrl(fe, 0);
0355
0356     return 0;
0357 }
0358
0359 static void max2165_release(struct dvb_frontend *fe)
0360 {
0361     struct max2165_priv *priv = fe->tuner_priv;
0362     dprintk("%s()\n", __func__);
0363
0364     kfree(priv);
0365     fe->tuner_priv = NULL;
0366 }
0367
0368 static const struct dvb_tuner_ops max2165_tuner_ops = {
0369     .info = {
0370         .name              = "Maxim MAX2165",
0371         .frequency_min_hz  = 470 * MHz,
0372         .frequency_max_hz  = 862 * MHz,
0373         .frequency_step_hz =  50 * kHz,
0374     },
0375
0376     .release       = max2165_release,
0377     .init          = max2165_init,
0378     .sleep         = max2165_sleep,
0379
0380     .set_params    = max2165_set_params,
0381     .set_analog_params = NULL,
0382     .get_frequency     = max2165_get_frequency,
0383     .get_bandwidth     = max2165_get_bandwidth,
0384     .get_status    = max2165_get_status
0385 };
0386
0387 struct dvb_frontend *max2165_attach(struct dvb_frontend *fe,
0388                    struct i2c_adapter *i2c,
0389                    struct max2165_config *cfg)
0390 {
0391     struct max2165_priv *priv = NULL;
0392
0393     dprintk("%s(%d-%04x)\n", __func__,
0394         i2c ? i2c_adapter_id(i2c) : -1,
0395         cfg ? cfg->i2c_address : -1);
0396
0397     priv = kzalloc(sizeof(struct max2165_priv), GFP_KERNEL);
0398     if (priv == NULL)
0399         return NULL;
0400
0401     memcpy(&fe->ops.tuner_ops, &max2165_tuner_ops,
0402         sizeof(struct dvb_tuner_ops));
0403
0404     priv->config = cfg;
0405     priv->i2c = i2c;
0406     fe->tuner_priv = priv;
0407
0408     max2165_init(fe);
0409     max2165_debug_status(priv);
0410
0411     return fe;
0412 }
0413 EXPORT_SYMBOL(max2165_attach);
0414
0415 MODULE_AUTHOR("David T. L. Wong <davidtlwong@gmail.com>");
0416 MODULE_DESCRIPTION("Maxim MAX2165 silicon tuner driver");
0417 MODULE_LICENSE("GPL");