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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Elonics E4000 silicon tuner driver
0004  *
0005  * Copyright (C) 2012 Antti Palosaari <crope@iki.fi>
0006  */
0007 
0008 #include "e4000_priv.h"
0009 
0010 static int e4000_init(struct e4000_dev *dev)
0011 {
0012     struct i2c_client *client = dev->client;
0013     int ret;
0014 
0015     dev_dbg(&client->dev, "\n");
0016 
0017     /* reset */
0018     ret = regmap_write(dev->regmap, 0x00, 0x01);
0019     if (ret)
0020         goto err;
0021 
0022     /* disable output clock */
0023     ret = regmap_write(dev->regmap, 0x06, 0x00);
0024     if (ret)
0025         goto err;
0026 
0027     ret = regmap_write(dev->regmap, 0x7a, 0x96);
0028     if (ret)
0029         goto err;
0030 
0031     /* configure gains */
0032     ret = regmap_bulk_write(dev->regmap, 0x7e, "\x01\xfe", 2);
0033     if (ret)
0034         goto err;
0035 
0036     ret = regmap_write(dev->regmap, 0x82, 0x00);
0037     if (ret)
0038         goto err;
0039 
0040     ret = regmap_write(dev->regmap, 0x24, 0x05);
0041     if (ret)
0042         goto err;
0043 
0044     ret = regmap_bulk_write(dev->regmap, 0x87, "\x20\x01", 2);
0045     if (ret)
0046         goto err;
0047 
0048     ret = regmap_bulk_write(dev->regmap, 0x9f, "\x7f\x07", 2);
0049     if (ret)
0050         goto err;
0051 
0052     /* DC offset control */
0053     ret = regmap_write(dev->regmap, 0x2d, 0x1f);
0054     if (ret)
0055         goto err;
0056 
0057     ret = regmap_bulk_write(dev->regmap, 0x70, "\x01\x01", 2);
0058     if (ret)
0059         goto err;
0060 
0061     /* gain control */
0062     ret = regmap_write(dev->regmap, 0x1a, 0x17);
0063     if (ret)
0064         goto err;
0065 
0066     ret = regmap_write(dev->regmap, 0x1f, 0x1a);
0067     if (ret)
0068         goto err;
0069 
0070     dev->active = true;
0071 
0072     return 0;
0073 err:
0074     dev_dbg(&client->dev, "failed=%d\n", ret);
0075     return ret;
0076 }
0077 
0078 static int e4000_sleep(struct e4000_dev *dev)
0079 {
0080     struct i2c_client *client = dev->client;
0081     int ret;
0082 
0083     dev_dbg(&client->dev, "\n");
0084 
0085     dev->active = false;
0086 
0087     ret = regmap_write(dev->regmap, 0x00, 0x00);
0088     if (ret)
0089         goto err;
0090 
0091     return 0;
0092 err:
0093     dev_dbg(&client->dev, "failed=%d\n", ret);
0094     return ret;
0095 }
0096 
0097 static int e4000_set_params(struct e4000_dev *dev)
0098 {
0099     struct i2c_client *client = dev->client;
0100     int ret, i;
0101     unsigned int div_n, k, k_cw, div_out;
0102     u64 f_vco;
0103     u8 buf[5], i_data[4], q_data[4];
0104 
0105     if (!dev->active) {
0106         dev_dbg(&client->dev, "tuner is sleeping\n");
0107         return 0;
0108     }
0109 
0110     /* gain control manual */
0111     ret = regmap_write(dev->regmap, 0x1a, 0x00);
0112     if (ret)
0113         goto err;
0114 
0115     /*
0116      * Fractional-N synthesizer
0117      *
0118      *           +----------------------------+
0119      *           v                            |
0120      *  Fref   +----+     +-------+         +------+     +---+
0121      * ------> | PD | --> |  VCO  | ------> | /N.F | <-- | K |
0122      *         +----+     +-------+         +------+     +---+
0123      *                      |
0124      *                      |
0125      *                      v
0126      *                    +-------+  Fout
0127      *                    | /Rout | ------>
0128      *                    +-------+
0129      */
0130     for (i = 0; i < ARRAY_SIZE(e4000_pll_lut); i++) {
0131         if (dev->f_frequency <= e4000_pll_lut[i].freq)
0132             break;
0133     }
0134     if (i == ARRAY_SIZE(e4000_pll_lut)) {
0135         ret = -EINVAL;
0136         goto err;
0137     }
0138 
0139     #define F_REF dev->clk
0140     div_out = e4000_pll_lut[i].div_out;
0141     f_vco = (u64) dev->f_frequency * div_out;
0142     /* calculate PLL integer and fractional control word */
0143     div_n = div_u64_rem(f_vco, F_REF, &k);
0144     k_cw = div_u64((u64) k * 0x10000, F_REF);
0145 
0146     dev_dbg(&client->dev,
0147         "frequency=%u bandwidth=%u f_vco=%llu F_REF=%u div_n=%u k=%u k_cw=%04x div_out=%u\n",
0148         dev->f_frequency, dev->f_bandwidth, f_vco, F_REF, div_n, k,
0149         k_cw, div_out);
0150 
0151     buf[0] = div_n;
0152     buf[1] = (k_cw >> 0) & 0xff;
0153     buf[2] = (k_cw >> 8) & 0xff;
0154     buf[3] = 0x00;
0155     buf[4] = e4000_pll_lut[i].div_out_reg;
0156     ret = regmap_bulk_write(dev->regmap, 0x09, buf, 5);
0157     if (ret)
0158         goto err;
0159 
0160     /* LNA filter (RF filter) */
0161     for (i = 0; i < ARRAY_SIZE(e400_lna_filter_lut); i++) {
0162         if (dev->f_frequency <= e400_lna_filter_lut[i].freq)
0163             break;
0164     }
0165     if (i == ARRAY_SIZE(e400_lna_filter_lut)) {
0166         ret = -EINVAL;
0167         goto err;
0168     }
0169 
0170     ret = regmap_write(dev->regmap, 0x10, e400_lna_filter_lut[i].val);
0171     if (ret)
0172         goto err;
0173 
0174     /* IF filters */
0175     for (i = 0; i < ARRAY_SIZE(e4000_if_filter_lut); i++) {
0176         if (dev->f_bandwidth <= e4000_if_filter_lut[i].freq)
0177             break;
0178     }
0179     if (i == ARRAY_SIZE(e4000_if_filter_lut)) {
0180         ret = -EINVAL;
0181         goto err;
0182     }
0183 
0184     buf[0] = e4000_if_filter_lut[i].reg11_val;
0185     buf[1] = e4000_if_filter_lut[i].reg12_val;
0186 
0187     ret = regmap_bulk_write(dev->regmap, 0x11, buf, 2);
0188     if (ret)
0189         goto err;
0190 
0191     /* frequency band */
0192     for (i = 0; i < ARRAY_SIZE(e4000_band_lut); i++) {
0193         if (dev->f_frequency <= e4000_band_lut[i].freq)
0194             break;
0195     }
0196     if (i == ARRAY_SIZE(e4000_band_lut)) {
0197         ret = -EINVAL;
0198         goto err;
0199     }
0200 
0201     ret = regmap_write(dev->regmap, 0x07, e4000_band_lut[i].reg07_val);
0202     if (ret)
0203         goto err;
0204 
0205     ret = regmap_write(dev->regmap, 0x78, e4000_band_lut[i].reg78_val);
0206     if (ret)
0207         goto err;
0208 
0209     /* DC offset */
0210     for (i = 0; i < 4; i++) {
0211         if (i == 0)
0212             ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7e\x24", 3);
0213         else if (i == 1)
0214             ret = regmap_bulk_write(dev->regmap, 0x15, "\x00\x7f", 2);
0215         else if (i == 2)
0216             ret = regmap_bulk_write(dev->regmap, 0x15, "\x01", 1);
0217         else
0218             ret = regmap_bulk_write(dev->regmap, 0x16, "\x7e", 1);
0219 
0220         if (ret)
0221             goto err;
0222 
0223         ret = regmap_write(dev->regmap, 0x29, 0x01);
0224         if (ret)
0225             goto err;
0226 
0227         ret = regmap_bulk_read(dev->regmap, 0x2a, buf, 3);
0228         if (ret)
0229             goto err;
0230 
0231         i_data[i] = (((buf[2] >> 0) & 0x3) << 6) | (buf[0] & 0x3f);
0232         q_data[i] = (((buf[2] >> 4) & 0x3) << 6) | (buf[1] & 0x3f);
0233     }
0234 
0235     swap(q_data[2], q_data[3]);
0236     swap(i_data[2], i_data[3]);
0237 
0238     ret = regmap_bulk_write(dev->regmap, 0x50, q_data, 4);
0239     if (ret)
0240         goto err;
0241 
0242     ret = regmap_bulk_write(dev->regmap, 0x60, i_data, 4);
0243     if (ret)
0244         goto err;
0245 
0246     /* gain control auto */
0247     ret = regmap_write(dev->regmap, 0x1a, 0x17);
0248     if (ret)
0249         goto err;
0250 
0251     return 0;
0252 err:
0253     dev_dbg(&client->dev, "failed=%d\n", ret);
0254     return ret;
0255 }
0256 
0257 /*
0258  * V4L2 API
0259  */
0260 #if IS_ENABLED(CONFIG_VIDEO_DEV)
0261 static const struct v4l2_frequency_band bands[] = {
0262     {
0263         .type = V4L2_TUNER_RF,
0264         .index = 0,
0265         .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
0266         .rangelow   =    59000000,
0267         .rangehigh  =  1105000000,
0268     },
0269     {
0270         .type = V4L2_TUNER_RF,
0271         .index = 1,
0272         .capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS,
0273         .rangelow   =  1249000000,
0274         .rangehigh  =  2208000000UL,
0275     },
0276 };
0277 
0278 static inline struct e4000_dev *e4000_subdev_to_dev(struct v4l2_subdev *sd)
0279 {
0280     return container_of(sd, struct e4000_dev, sd);
0281 }
0282 
0283 static int e4000_standby(struct v4l2_subdev *sd)
0284 {
0285     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0286     int ret;
0287 
0288     ret = e4000_sleep(dev);
0289     if (ret)
0290         return ret;
0291 
0292     return e4000_set_params(dev);
0293 }
0294 
0295 static int e4000_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *v)
0296 {
0297     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0298     struct i2c_client *client = dev->client;
0299 
0300     dev_dbg(&client->dev, "index=%d\n", v->index);
0301 
0302     strscpy(v->name, "Elonics E4000", sizeof(v->name));
0303     v->type = V4L2_TUNER_RF;
0304     v->capability = V4L2_TUNER_CAP_1HZ | V4L2_TUNER_CAP_FREQ_BANDS;
0305     v->rangelow  = bands[0].rangelow;
0306     v->rangehigh = bands[1].rangehigh;
0307     return 0;
0308 }
0309 
0310 static int e4000_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *v)
0311 {
0312     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0313     struct i2c_client *client = dev->client;
0314 
0315     dev_dbg(&client->dev, "index=%d\n", v->index);
0316     return 0;
0317 }
0318 
0319 static int e4000_g_frequency(struct v4l2_subdev *sd, struct v4l2_frequency *f)
0320 {
0321     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0322     struct i2c_client *client = dev->client;
0323 
0324     dev_dbg(&client->dev, "tuner=%d\n", f->tuner);
0325     f->frequency = dev->f_frequency;
0326     return 0;
0327 }
0328 
0329 static int e4000_s_frequency(struct v4l2_subdev *sd,
0330                   const struct v4l2_frequency *f)
0331 {
0332     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0333     struct i2c_client *client = dev->client;
0334 
0335     dev_dbg(&client->dev, "tuner=%d type=%d frequency=%u\n",
0336         f->tuner, f->type, f->frequency);
0337 
0338     dev->f_frequency = clamp_t(unsigned int, f->frequency,
0339                    bands[0].rangelow, bands[1].rangehigh);
0340     return e4000_set_params(dev);
0341 }
0342 
0343 static int e4000_enum_freq_bands(struct v4l2_subdev *sd,
0344                   struct v4l2_frequency_band *band)
0345 {
0346     struct e4000_dev *dev = e4000_subdev_to_dev(sd);
0347     struct i2c_client *client = dev->client;
0348 
0349     dev_dbg(&client->dev, "tuner=%d type=%d index=%d\n",
0350         band->tuner, band->type, band->index);
0351 
0352     if (band->index >= ARRAY_SIZE(bands))
0353         return -EINVAL;
0354 
0355     band->capability = bands[band->index].capability;
0356     band->rangelow = bands[band->index].rangelow;
0357     band->rangehigh = bands[band->index].rangehigh;
0358     return 0;
0359 }
0360 
0361 static const struct v4l2_subdev_tuner_ops e4000_subdev_tuner_ops = {
0362     .standby                  = e4000_standby,
0363     .g_tuner                  = e4000_g_tuner,
0364     .s_tuner                  = e4000_s_tuner,
0365     .g_frequency              = e4000_g_frequency,
0366     .s_frequency              = e4000_s_frequency,
0367     .enum_freq_bands          = e4000_enum_freq_bands,
0368 };
0369 
0370 static const struct v4l2_subdev_ops e4000_subdev_ops = {
0371     .tuner                    = &e4000_subdev_tuner_ops,
0372 };
0373 
0374 static int e4000_set_lna_gain(struct dvb_frontend *fe)
0375 {
0376     struct e4000_dev *dev = fe->tuner_priv;
0377     struct i2c_client *client = dev->client;
0378     int ret;
0379     u8 u8tmp;
0380 
0381     dev_dbg(&client->dev, "lna auto=%d->%d val=%d->%d\n",
0382         dev->lna_gain_auto->cur.val, dev->lna_gain_auto->val,
0383         dev->lna_gain->cur.val, dev->lna_gain->val);
0384 
0385     if (dev->lna_gain_auto->val && dev->if_gain_auto->cur.val)
0386         u8tmp = 0x17;
0387     else if (dev->lna_gain_auto->val)
0388         u8tmp = 0x19;
0389     else if (dev->if_gain_auto->cur.val)
0390         u8tmp = 0x16;
0391     else
0392         u8tmp = 0x10;
0393 
0394     ret = regmap_write(dev->regmap, 0x1a, u8tmp);
0395     if (ret)
0396         goto err;
0397 
0398     if (dev->lna_gain_auto->val == false) {
0399         ret = regmap_write(dev->regmap, 0x14, dev->lna_gain->val);
0400         if (ret)
0401             goto err;
0402     }
0403 
0404     return 0;
0405 err:
0406     dev_dbg(&client->dev, "failed=%d\n", ret);
0407     return ret;
0408 }
0409 
0410 static int e4000_set_mixer_gain(struct dvb_frontend *fe)
0411 {
0412     struct e4000_dev *dev = fe->tuner_priv;
0413     struct i2c_client *client = dev->client;
0414     int ret;
0415     u8 u8tmp;
0416 
0417     dev_dbg(&client->dev, "mixer auto=%d->%d val=%d->%d\n",
0418         dev->mixer_gain_auto->cur.val, dev->mixer_gain_auto->val,
0419         dev->mixer_gain->cur.val, dev->mixer_gain->val);
0420 
0421     if (dev->mixer_gain_auto->val)
0422         u8tmp = 0x15;
0423     else
0424         u8tmp = 0x14;
0425 
0426     ret = regmap_write(dev->regmap, 0x20, u8tmp);
0427     if (ret)
0428         goto err;
0429 
0430     if (dev->mixer_gain_auto->val == false) {
0431         ret = regmap_write(dev->regmap, 0x15, dev->mixer_gain->val);
0432         if (ret)
0433             goto err;
0434     }
0435 
0436     return 0;
0437 err:
0438     dev_dbg(&client->dev, "failed=%d\n", ret);
0439     return ret;
0440 }
0441 
0442 static int e4000_set_if_gain(struct dvb_frontend *fe)
0443 {
0444     struct e4000_dev *dev = fe->tuner_priv;
0445     struct i2c_client *client = dev->client;
0446     int ret;
0447     u8 buf[2];
0448     u8 u8tmp;
0449 
0450     dev_dbg(&client->dev, "if auto=%d->%d val=%d->%d\n",
0451         dev->if_gain_auto->cur.val, dev->if_gain_auto->val,
0452         dev->if_gain->cur.val, dev->if_gain->val);
0453 
0454     if (dev->if_gain_auto->val && dev->lna_gain_auto->cur.val)
0455         u8tmp = 0x17;
0456     else if (dev->lna_gain_auto->cur.val)
0457         u8tmp = 0x19;
0458     else if (dev->if_gain_auto->val)
0459         u8tmp = 0x16;
0460     else
0461         u8tmp = 0x10;
0462 
0463     ret = regmap_write(dev->regmap, 0x1a, u8tmp);
0464     if (ret)
0465         goto err;
0466 
0467     if (dev->if_gain_auto->val == false) {
0468         buf[0] = e4000_if_gain_lut[dev->if_gain->val].reg16_val;
0469         buf[1] = e4000_if_gain_lut[dev->if_gain->val].reg17_val;
0470         ret = regmap_bulk_write(dev->regmap, 0x16, buf, 2);
0471         if (ret)
0472             goto err;
0473     }
0474 
0475     return 0;
0476 err:
0477     dev_dbg(&client->dev, "failed=%d\n", ret);
0478     return ret;
0479 }
0480 
0481 static int e4000_pll_lock(struct dvb_frontend *fe)
0482 {
0483     struct e4000_dev *dev = fe->tuner_priv;
0484     struct i2c_client *client = dev->client;
0485     int ret;
0486     unsigned int uitmp;
0487 
0488     ret = regmap_read(dev->regmap, 0x07, &uitmp);
0489     if (ret)
0490         goto err;
0491 
0492     dev->pll_lock->val = (uitmp & 0x01);
0493 
0494     return 0;
0495 err:
0496     dev_dbg(&client->dev, "failed=%d\n", ret);
0497     return ret;
0498 }
0499 
0500 static int e4000_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
0501 {
0502     struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
0503     struct i2c_client *client = dev->client;
0504     int ret;
0505 
0506     if (!dev->active)
0507         return 0;
0508 
0509     switch (ctrl->id) {
0510     case  V4L2_CID_RF_TUNER_PLL_LOCK:
0511         ret = e4000_pll_lock(dev->fe);
0512         break;
0513     default:
0514         dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
0515             ctrl->id, ctrl->name);
0516         ret = -EINVAL;
0517     }
0518 
0519     return ret;
0520 }
0521 
0522 static int e4000_s_ctrl(struct v4l2_ctrl *ctrl)
0523 {
0524     struct e4000_dev *dev = container_of(ctrl->handler, struct e4000_dev, hdl);
0525     struct i2c_client *client = dev->client;
0526     int ret;
0527 
0528     if (!dev->active)
0529         return 0;
0530 
0531     switch (ctrl->id) {
0532     case V4L2_CID_RF_TUNER_BANDWIDTH_AUTO:
0533     case V4L2_CID_RF_TUNER_BANDWIDTH:
0534         /*
0535          * TODO: Auto logic does not work 100% correctly as tuner driver
0536          * do not have information to calculate maximum suitable
0537          * bandwidth. Calculating it is responsible of master driver.
0538          */
0539         dev->f_bandwidth = dev->bandwidth->val;
0540         ret = e4000_set_params(dev);
0541         break;
0542     case  V4L2_CID_RF_TUNER_LNA_GAIN_AUTO:
0543     case  V4L2_CID_RF_TUNER_LNA_GAIN:
0544         ret = e4000_set_lna_gain(dev->fe);
0545         break;
0546     case  V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO:
0547     case  V4L2_CID_RF_TUNER_MIXER_GAIN:
0548         ret = e4000_set_mixer_gain(dev->fe);
0549         break;
0550     case  V4L2_CID_RF_TUNER_IF_GAIN_AUTO:
0551     case  V4L2_CID_RF_TUNER_IF_GAIN:
0552         ret = e4000_set_if_gain(dev->fe);
0553         break;
0554     default:
0555         dev_dbg(&client->dev, "unknown ctrl: id=%d name=%s\n",
0556             ctrl->id, ctrl->name);
0557         ret = -EINVAL;
0558     }
0559 
0560     return ret;
0561 }
0562 
0563 static const struct v4l2_ctrl_ops e4000_ctrl_ops = {
0564     .g_volatile_ctrl = e4000_g_volatile_ctrl,
0565     .s_ctrl = e4000_s_ctrl,
0566 };
0567 #endif
0568 
0569 /*
0570  * DVB API
0571  */
0572 static int e4000_dvb_set_params(struct dvb_frontend *fe)
0573 {
0574     struct e4000_dev *dev = fe->tuner_priv;
0575     struct dtv_frontend_properties *c = &fe->dtv_property_cache;
0576 
0577     dev->f_frequency = c->frequency;
0578     dev->f_bandwidth = c->bandwidth_hz;
0579     return e4000_set_params(dev);
0580 }
0581 
0582 static int e4000_dvb_init(struct dvb_frontend *fe)
0583 {
0584     return e4000_init(fe->tuner_priv);
0585 }
0586 
0587 static int e4000_dvb_sleep(struct dvb_frontend *fe)
0588 {
0589     return e4000_sleep(fe->tuner_priv);
0590 }
0591 
0592 static int e4000_dvb_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
0593 {
0594     *frequency = 0; /* Zero-IF */
0595     return 0;
0596 }
0597 
0598 static const struct dvb_tuner_ops e4000_dvb_tuner_ops = {
0599     .info = {
0600         .name              = "Elonics E4000",
0601         .frequency_min_hz  = 174 * MHz,
0602         .frequency_max_hz  = 862 * MHz,
0603     },
0604 
0605     .init = e4000_dvb_init,
0606     .sleep = e4000_dvb_sleep,
0607     .set_params = e4000_dvb_set_params,
0608 
0609     .get_if_frequency = e4000_dvb_get_if_frequency,
0610 };
0611 
0612 static int e4000_probe(struct i2c_client *client,
0613                const struct i2c_device_id *id)
0614 {
0615     struct e4000_dev *dev;
0616     struct e4000_config *cfg = client->dev.platform_data;
0617     struct dvb_frontend *fe = cfg->fe;
0618     int ret;
0619     unsigned int uitmp;
0620     static const struct regmap_config regmap_config = {
0621         .reg_bits = 8,
0622         .val_bits = 8,
0623     };
0624 
0625     dev = kzalloc(sizeof(*dev), GFP_KERNEL);
0626     if (!dev) {
0627         ret = -ENOMEM;
0628         goto err;
0629     }
0630 
0631     dev->clk = cfg->clock;
0632     dev->client = client;
0633     dev->fe = cfg->fe;
0634     dev->regmap = devm_regmap_init_i2c(client, &regmap_config);
0635     if (IS_ERR(dev->regmap)) {
0636         ret = PTR_ERR(dev->regmap);
0637         goto err_kfree;
0638     }
0639 
0640     /* check if the tuner is there */
0641     ret = regmap_read(dev->regmap, 0x02, &uitmp);
0642     if (ret)
0643         goto err_kfree;
0644 
0645     dev_dbg(&client->dev, "chip id=%02x\n", uitmp);
0646 
0647     if (uitmp != 0x40) {
0648         ret = -ENODEV;
0649         goto err_kfree;
0650     }
0651 
0652     /* put sleep as chip seems to be in normal mode by default */
0653     ret = regmap_write(dev->regmap, 0x00, 0x00);
0654     if (ret)
0655         goto err_kfree;
0656 
0657 #if IS_ENABLED(CONFIG_VIDEO_DEV)
0658     /* Register controls */
0659     v4l2_ctrl_handler_init(&dev->hdl, 9);
0660     dev->bandwidth_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0661             V4L2_CID_RF_TUNER_BANDWIDTH_AUTO, 0, 1, 1, 1);
0662     dev->bandwidth = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0663             V4L2_CID_RF_TUNER_BANDWIDTH, 4300000, 11000000, 100000, 4300000);
0664     v4l2_ctrl_auto_cluster(2, &dev->bandwidth_auto, 0, false);
0665     dev->lna_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0666             V4L2_CID_RF_TUNER_LNA_GAIN_AUTO, 0, 1, 1, 1);
0667     dev->lna_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0668             V4L2_CID_RF_TUNER_LNA_GAIN, 0, 15, 1, 10);
0669     v4l2_ctrl_auto_cluster(2, &dev->lna_gain_auto, 0, false);
0670     dev->mixer_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0671             V4L2_CID_RF_TUNER_MIXER_GAIN_AUTO, 0, 1, 1, 1);
0672     dev->mixer_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0673             V4L2_CID_RF_TUNER_MIXER_GAIN, 0, 1, 1, 1);
0674     v4l2_ctrl_auto_cluster(2, &dev->mixer_gain_auto, 0, false);
0675     dev->if_gain_auto = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0676             V4L2_CID_RF_TUNER_IF_GAIN_AUTO, 0, 1, 1, 1);
0677     dev->if_gain = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0678             V4L2_CID_RF_TUNER_IF_GAIN, 0, 54, 1, 0);
0679     v4l2_ctrl_auto_cluster(2, &dev->if_gain_auto, 0, false);
0680     dev->pll_lock = v4l2_ctrl_new_std(&dev->hdl, &e4000_ctrl_ops,
0681             V4L2_CID_RF_TUNER_PLL_LOCK,  0, 1, 1, 0);
0682     if (dev->hdl.error) {
0683         ret = dev->hdl.error;
0684         dev_err(&client->dev, "Could not initialize controls\n");
0685         v4l2_ctrl_handler_free(&dev->hdl);
0686         goto err_kfree;
0687     }
0688 
0689     dev->sd.ctrl_handler = &dev->hdl;
0690     dev->f_frequency = bands[0].rangelow;
0691     dev->f_bandwidth = dev->bandwidth->val;
0692     v4l2_i2c_subdev_init(&dev->sd, client, &e4000_subdev_ops);
0693 #endif
0694     fe->tuner_priv = dev;
0695     memcpy(&fe->ops.tuner_ops, &e4000_dvb_tuner_ops,
0696            sizeof(fe->ops.tuner_ops));
0697     v4l2_set_subdevdata(&dev->sd, client);
0698     i2c_set_clientdata(client, &dev->sd);
0699 
0700     dev_info(&client->dev, "Elonics E4000 successfully identified\n");
0701     return 0;
0702 err_kfree:
0703     kfree(dev);
0704 err:
0705     dev_dbg(&client->dev, "failed=%d\n", ret);
0706     return ret;
0707 }
0708 
0709 static int e4000_remove(struct i2c_client *client)
0710 {
0711     struct v4l2_subdev *sd = i2c_get_clientdata(client);
0712     struct e4000_dev *dev = container_of(sd, struct e4000_dev, sd);
0713 
0714     dev_dbg(&client->dev, "\n");
0715 
0716 #if IS_ENABLED(CONFIG_VIDEO_DEV)
0717     v4l2_ctrl_handler_free(&dev->hdl);
0718 #endif
0719     kfree(dev);
0720 
0721     return 0;
0722 }
0723 
0724 static const struct i2c_device_id e4000_id_table[] = {
0725     {"e4000", 0},
0726     {}
0727 };
0728 MODULE_DEVICE_TABLE(i2c, e4000_id_table);
0729 
0730 static struct i2c_driver e4000_driver = {
0731     .driver = {
0732         .name   = "e4000",
0733         .suppress_bind_attrs = true,
0734     },
0735     .probe      = e4000_probe,
0736     .remove     = e4000_remove,
0737     .id_table   = e4000_id_table,
0738 };
0739 
0740 module_i2c_driver(e4000_driver);
0741 
0742 MODULE_DESCRIPTION("Elonics E4000 silicon tuner driver");
0743 MODULE_AUTHOR("Antti Palosaari <crope@iki.fi>");
0744 MODULE_LICENSE("GPL");
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