media/rc/st_rc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2013 STMicroelectronics Limited
0004  * Author: Srinivas Kandagatla <srinivas.kandagatla@st.com>
0005  */
0006 #include <linux/kernel.h>
0007 #include <linux/clk.h>
0008 #include <linux/interrupt.h>
0009 #include <linux/module.h>
0010 #include <linux/of.h>
0011 #include <linux/platform_device.h>
0012 #include <linux/reset.h>
0013 #include <media/rc-core.h>
0014 #include <linux/pinctrl/consumer.h>
0015 #include <linux/pm_wakeirq.h>
0016
0017 struct st_rc_device {
0018     struct device           *dev;
0019     int             irq;
0020     int             irq_wake;
0021     struct clk          *sys_clock;
0022     void __iomem            *base;  /* Register base address */
0023     void __iomem            *rx_base;/* RX Register base address */
0024     struct rc_dev           *rdev;
0025     bool                overclocking;
0026     int             sample_mult;
0027     int             sample_div;
0028     bool                rxuhfmode;
0029     struct  reset_control       *rstc;
0030 };
0031
0032 /* Registers */
0033 #define IRB_SAMPLE_RATE_COMM    0x64    /* sample freq divisor*/
0034 #define IRB_CLOCK_SEL       0x70    /* clock select       */
0035 #define IRB_CLOCK_SEL_STATUS    0x74    /* clock status       */
0036 /* IRB IR/UHF receiver registers */
0037 #define IRB_RX_ON               0x40    /* pulse time capture */
0038 #define IRB_RX_SYS              0X44    /* sym period capture */
0039 #define IRB_RX_INT_EN           0x48    /* IRQ enable (R/W)   */
0040 #define IRB_RX_INT_STATUS       0x4c    /* IRQ status (R/W)   */
0041 #define IRB_RX_EN               0x50    /* Receive enable     */
0042 #define IRB_MAX_SYM_PERIOD      0x54    /* max sym value      */
0043 #define IRB_RX_INT_CLEAR        0x58    /* overrun status     */
0044 #define IRB_RX_STATUS           0x6c    /* receive status     */
0045 #define IRB_RX_NOISE_SUPPR      0x5c    /* noise suppression  */
0046 #define IRB_RX_POLARITY_INV     0x68    /* polarity inverter  */
0047
0048 /*
0049  * IRQ set: Enable full FIFO                 1  -> bit  3;
0050  *          Enable overrun IRQ               1  -> bit  2;
0051  *          Enable last symbol IRQ           1  -> bit  1:
0052  *          Enable RX interrupt              1  -> bit  0;
0053  */
0054 #define IRB_RX_INTS     0x0f
0055 #define IRB_RX_OVERRUN_INT  0x04
0056  /* maximum symbol period (microsecs),timeout to detect end of symbol train */
0057 #define MAX_SYMB_TIME       0x5000
0058 #define IRB_SAMPLE_FREQ     10000000
0059 #define IRB_FIFO_NOT_EMPTY  0xff00
0060 #define IRB_OVERFLOW        0x4
0061 #define IRB_TIMEOUT     0xffff
0062 #define IR_ST_NAME "st-rc"
0063
0064 static void st_rc_send_lirc_timeout(struct rc_dev *rdev)
0065 {
0066     struct ir_raw_event ev = { .timeout = true, .duration = rdev->timeout };
0067     ir_raw_event_store(rdev, &ev);
0068 }
0069
0070 /*
0071  * RX graphical example to better understand the difference between ST IR block
0072  * output and standard definition used by LIRC (and most of the world!)
0073  *
0074  *           mark                                     mark
0075  *      |-IRB_RX_ON-|                            |-IRB_RX_ON-|
0076  *      ___  ___  ___                            ___  ___  ___             _
0077  *      | |  | |  | |                            | |  | |  | |             |
0078  *      | |  | |  | |         space 0            | |  | |  | |   space 1   |
0079  * _____| |__| |__| |____________________________| |__| |__| |_____________|
0080  *
0081  *      |--------------- IRB_RX_SYS -------------|------ IRB_RX_SYS -------|
0082  *
0083  *      |------------- encoding bit 0 -----------|---- encoding bit 1 -----|
0084  *
0085  * ST hardware returns mark (IRB_RX_ON) and total symbol time (IRB_RX_SYS), so
0086  * convert to standard mark/space we have to calculate space=(IRB_RX_SYS-mark)
0087  * The mark time represents the amount of time the carrier (usually 36-40kHz)
0088  * is detected.The above examples shows Pulse Width Modulation encoding where
0089  * bit 0 is represented by space>mark.
0090  */
0091
0092 static irqreturn_t st_rc_rx_interrupt(int irq, void *data)
0093 {
0094     unsigned long timeout;
0095     unsigned int symbol, mark = 0;
0096     struct st_rc_device *dev = data;
0097     int last_symbol = 0;
0098     u32 status, int_status;
0099     struct ir_raw_event ev = {};
0100
0101     if (dev->irq_wake)
0102         pm_wakeup_event(dev->dev, 0);
0103
0104     /* FIXME: is 10ms good enough ? */
0105     timeout = jiffies +  msecs_to_jiffies(10);
0106     do {
0107         status  = readl(dev->rx_base + IRB_RX_STATUS);
0108         if (!(status & (IRB_FIFO_NOT_EMPTY | IRB_OVERFLOW)))
0109             break;
0110
0111         int_status = readl(dev->rx_base + IRB_RX_INT_STATUS);
0112         if (unlikely(int_status & IRB_RX_OVERRUN_INT)) {
0113             /* discard the entire collection in case of errors!  */
0114             ir_raw_event_overflow(dev->rdev);
0115             dev_info(dev->dev, "IR RX overrun\n");
0116             writel(IRB_RX_OVERRUN_INT,
0117                     dev->rx_base + IRB_RX_INT_CLEAR);
0118             continue;
0119         }
0120
0121         symbol = readl(dev->rx_base + IRB_RX_SYS);
0122         mark = readl(dev->rx_base + IRB_RX_ON);
0123
0124         if (symbol == IRB_TIMEOUT)
0125             last_symbol = 1;
0126
0127          /* Ignore any noise */
0128         if ((mark > 2) && (symbol > 1)) {
0129             symbol -= mark;
0130             if (dev->overclocking) { /* adjustments to timings */
0131                 symbol *= dev->sample_mult;
0132                 symbol /= dev->sample_div;
0133                 mark *= dev->sample_mult;
0134                 mark /= dev->sample_div;
0135             }
0136
0137             ev.duration = mark;
0138             ev.pulse = true;
0139             ir_raw_event_store(dev->rdev, &ev);
0140
0141             if (!last_symbol) {
0142                 ev.duration = symbol;
0143                 ev.pulse = false;
0144                 ir_raw_event_store(dev->rdev, &ev);
0145             } else  {
0146                 st_rc_send_lirc_timeout(dev->rdev);
0147             }
0148
0149         }
0150         last_symbol = 0;
0151     } while (time_is_after_jiffies(timeout));
0152
0153     writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_CLEAR);
0154
0155     /* Empty software fifo */
0156     ir_raw_event_handle(dev->rdev);
0157     return IRQ_HANDLED;
0158 }
0159
0160 static int st_rc_hardware_init(struct st_rc_device *dev)
0161 {
0162     int ret;
0163     int baseclock, freqdiff;
0164     unsigned int rx_max_symbol_per = MAX_SYMB_TIME;
0165     unsigned int rx_sampling_freq_div;
0166
0167     /* Enable the IP */
0168     reset_control_deassert(dev->rstc);
0169
0170     ret = clk_prepare_enable(dev->sys_clock);
0171     if (ret) {
0172         dev_err(dev->dev, "Failed to prepare/enable system clock\n");
0173         return ret;
0174     }
0175
0176     baseclock = clk_get_rate(dev->sys_clock);
0177
0178     /* IRB input pins are inverted internally from high to low. */
0179     writel(1, dev->rx_base + IRB_RX_POLARITY_INV);
0180
0181     rx_sampling_freq_div = baseclock / IRB_SAMPLE_FREQ;
0182     writel(rx_sampling_freq_div, dev->base + IRB_SAMPLE_RATE_COMM);
0183
0184     freqdiff = baseclock - (rx_sampling_freq_div * IRB_SAMPLE_FREQ);
0185     if (freqdiff) { /* over clocking, workout the adjustment factors */
0186         dev->overclocking = true;
0187         dev->sample_mult = 1000;
0188         dev->sample_div = baseclock / (10000 * rx_sampling_freq_div);
0189         rx_max_symbol_per = (rx_max_symbol_per * 1000)/dev->sample_div;
0190     }
0191
0192     writel(rx_max_symbol_per, dev->rx_base + IRB_MAX_SYM_PERIOD);
0193
0194     return 0;
0195 }
0196
0197 static int st_rc_remove(struct platform_device *pdev)
0198 {
0199     struct st_rc_device *rc_dev = platform_get_drvdata(pdev);
0200
0201     dev_pm_clear_wake_irq(&pdev->dev);
0202     device_init_wakeup(&pdev->dev, false);
0203     clk_disable_unprepare(rc_dev->sys_clock);
0204     rc_unregister_device(rc_dev->rdev);
0205     return 0;
0206 }
0207
0208 static int st_rc_open(struct rc_dev *rdev)
0209 {
0210     struct st_rc_device *dev = rdev->priv;
0211     unsigned long flags;
0212     local_irq_save(flags);
0213     /* enable interrupts and receiver */
0214     writel(IRB_RX_INTS, dev->rx_base + IRB_RX_INT_EN);
0215     writel(0x01, dev->rx_base + IRB_RX_EN);
0216     local_irq_restore(flags);
0217
0218     return 0;
0219 }
0220
0221 static void st_rc_close(struct rc_dev *rdev)
0222 {
0223     struct st_rc_device *dev = rdev->priv;
0224     /* disable interrupts and receiver */
0225     writel(0x00, dev->rx_base + IRB_RX_EN);
0226     writel(0x00, dev->rx_base + IRB_RX_INT_EN);
0227 }
0228
0229 static int st_rc_probe(struct platform_device *pdev)
0230 {
0231     int ret = -EINVAL;
0232     struct rc_dev *rdev;
0233     struct device *dev = &pdev->dev;
0234     struct st_rc_device *rc_dev;
0235     struct device_node *np = pdev->dev.of_node;
0236     const char *rx_mode;
0237
0238     rc_dev = devm_kzalloc(dev, sizeof(struct st_rc_device), GFP_KERNEL);
0239
0240     if (!rc_dev)
0241         return -ENOMEM;
0242
0243     rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
0244
0245     if (!rdev)
0246         return -ENOMEM;
0247
0248     if (np && !of_property_read_string(np, "rx-mode", &rx_mode)) {
0249
0250         if (!strcmp(rx_mode, "uhf")) {
0251             rc_dev->rxuhfmode = true;
0252         } else if (!strcmp(rx_mode, "infrared")) {
0253             rc_dev->rxuhfmode = false;
0254         } else {
0255             dev_err(dev, "Unsupported rx mode [%s]\n", rx_mode);
0256             goto err;
0257         }
0258
0259     } else {
0260         goto err;
0261     }
0262
0263     rc_dev->sys_clock = devm_clk_get(dev, NULL);
0264     if (IS_ERR(rc_dev->sys_clock)) {
0265         dev_err(dev, "System clock not found\n");
0266         ret = PTR_ERR(rc_dev->sys_clock);
0267         goto err;
0268     }
0269
0270     rc_dev->irq = platform_get_irq(pdev, 0);
0271     if (rc_dev->irq < 0) {
0272         ret = rc_dev->irq;
0273         goto err;
0274     }
0275
0276     rc_dev->base = devm_platform_ioremap_resource(pdev, 0);
0277     if (IS_ERR(rc_dev->base)) {
0278         ret = PTR_ERR(rc_dev->base);
0279         goto err;
0280     }
0281
0282     if (rc_dev->rxuhfmode)
0283         rc_dev->rx_base = rc_dev->base + 0x40;
0284     else
0285         rc_dev->rx_base = rc_dev->base;
0286
0287     rc_dev->rstc = reset_control_get_optional_exclusive(dev, NULL);
0288     if (IS_ERR(rc_dev->rstc)) {
0289         ret = PTR_ERR(rc_dev->rstc);
0290         goto err;
0291     }
0292
0293     rc_dev->dev = dev;
0294     platform_set_drvdata(pdev, rc_dev);
0295     ret = st_rc_hardware_init(rc_dev);
0296     if (ret)
0297         goto err;
0298
0299     rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
0300     /* rx sampling rate is 10Mhz */
0301     rdev->rx_resolution = 100;
0302     rdev->timeout = MAX_SYMB_TIME;
0303     rdev->priv = rc_dev;
0304     rdev->open = st_rc_open;
0305     rdev->close = st_rc_close;
0306     rdev->driver_name = IR_ST_NAME;
0307     rdev->map_name = RC_MAP_EMPTY;
0308     rdev->device_name = "ST Remote Control Receiver";
0309
0310     ret = rc_register_device(rdev);
0311     if (ret < 0)
0312         goto clkerr;
0313
0314     rc_dev->rdev = rdev;
0315     if (devm_request_irq(dev, rc_dev->irq, st_rc_rx_interrupt,
0316                  0, IR_ST_NAME, rc_dev) < 0) {
0317         dev_err(dev, "IRQ %d register failed\n", rc_dev->irq);
0318         ret = -EINVAL;
0319         goto rcerr;
0320     }
0321
0322     /* enable wake via this device */
0323     device_init_wakeup(dev, true);
0324     dev_pm_set_wake_irq(dev, rc_dev->irq);
0325
0326     /*
0327      * for LIRC_MODE_MODE2 or LIRC_MODE_PULSE or LIRC_MODE_RAW
0328      * lircd expects a long space first before a signal train to sync.
0329      */
0330     st_rc_send_lirc_timeout(rdev);
0331
0332     dev_info(dev, "setup in %s mode\n", rc_dev->rxuhfmode ? "UHF" : "IR");
0333
0334     return ret;
0335 rcerr:
0336     rc_unregister_device(rdev);
0337     rdev = NULL;
0338 clkerr:
0339     clk_disable_unprepare(rc_dev->sys_clock);
0340 err:
0341     rc_free_device(rdev);
0342     dev_err(dev, "Unable to register device (%d)\n", ret);
0343     return ret;
0344 }
0345
0346 #ifdef CONFIG_PM_SLEEP
0347 static int st_rc_suspend(struct device *dev)
0348 {
0349     struct st_rc_device *rc_dev = dev_get_drvdata(dev);
0350
0351     if (device_may_wakeup(dev)) {
0352         if (!enable_irq_wake(rc_dev->irq))
0353             rc_dev->irq_wake = 1;
0354         else
0355             return -EINVAL;
0356     } else {
0357         pinctrl_pm_select_sleep_state(dev);
0358         writel(0x00, rc_dev->rx_base + IRB_RX_EN);
0359         writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN);
0360         clk_disable_unprepare(rc_dev->sys_clock);
0361         reset_control_assert(rc_dev->rstc);
0362     }
0363
0364     return 0;
0365 }
0366
0367 static int st_rc_resume(struct device *dev)
0368 {
0369     int ret;
0370     struct st_rc_device *rc_dev = dev_get_drvdata(dev);
0371     struct rc_dev   *rdev = rc_dev->rdev;
0372
0373     if (rc_dev->irq_wake) {
0374         disable_irq_wake(rc_dev->irq);
0375         rc_dev->irq_wake = 0;
0376     } else {
0377         pinctrl_pm_select_default_state(dev);
0378         ret = st_rc_hardware_init(rc_dev);
0379         if (ret)
0380             return ret;
0381
0382         if (rdev->users) {
0383             writel(IRB_RX_INTS, rc_dev->rx_base + IRB_RX_INT_EN);
0384             writel(0x01, rc_dev->rx_base + IRB_RX_EN);
0385         }
0386     }
0387
0388     return 0;
0389 }
0390
0391 #endif
0392
0393 static SIMPLE_DEV_PM_OPS(st_rc_pm_ops, st_rc_suspend, st_rc_resume);
0394
0395 #ifdef CONFIG_OF
0396 static const struct of_device_id st_rc_match[] = {
0397     { .compatible = "st,comms-irb", },
0398     {},
0399 };
0400
0401 MODULE_DEVICE_TABLE(of, st_rc_match);
0402 #endif
0403
0404 static struct platform_driver st_rc_driver = {
0405     .driver = {
0406         .name = IR_ST_NAME,
0407         .of_match_table = of_match_ptr(st_rc_match),
0408         .pm     = &st_rc_pm_ops,
0409     },
0410     .probe = st_rc_probe,
0411     .remove = st_rc_remove,
0412 };
0413
0414 module_platform_driver(st_rc_driver);
0415
0416 MODULE_DESCRIPTION("RC Transceiver driver for STMicroelectronics platforms");
0417 MODULE_AUTHOR("STMicroelectronics (R&D) Ltd");
0418 MODULE_LICENSE("GPL");