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0001 /*
0002  * Driver for Nuvoton Technology Corporation w83667hg/w83677hg-i CIR
0003  *
0004  * Copyright (C) 2010 Jarod Wilson <jarod@redhat.com>
0005  * Copyright (C) 2009 Nuvoton PS Team
0006  *
0007  * Special thanks to Nuvoton for providing hardware, spec sheets and
0008  * sample code upon which portions of this driver are based. Indirect
0009  * thanks also to Maxim Levitsky, whose ene_ir driver this driver is
0010  * modeled after.
0011  *
0012  * This program is free software; you can redistribute it and/or
0013  * modify it under the terms of the GNU General Public License as
0014  * published by the Free Software Foundation; either version 2 of the
0015  * License, or (at your option) any later version.
0016  *
0017  * This program is distributed in the hope that it will be useful, but
0018  * WITHOUT ANY WARRANTY; without even the implied warranty of
0019  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
0020  * General Public License for more details.
0021  */
0022 
0023 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
0024 
0025 #include <linux/kernel.h>
0026 #include <linux/module.h>
0027 #include <linux/pnp.h>
0028 #include <linux/io.h>
0029 #include <linux/interrupt.h>
0030 #include <linux/sched.h>
0031 #include <linux/slab.h>
0032 #include <media/rc-core.h>
0033 #include <linux/pci_ids.h>
0034 
0035 #include "nuvoton-cir.h"
0036 
0037 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt);
0038 
0039 static const struct nvt_chip nvt_chips[] = {
0040     { "w83667hg", NVT_W83667HG },
0041     { "NCT6775F", NVT_6775F },
0042     { "NCT6776F", NVT_6776F },
0043     { "NCT6779D", NVT_6779D },
0044 };
0045 
0046 static inline struct device *nvt_get_dev(const struct nvt_dev *nvt)
0047 {
0048     return nvt->rdev->dev.parent;
0049 }
0050 
0051 static inline bool is_w83667hg(struct nvt_dev *nvt)
0052 {
0053     return nvt->chip_ver == NVT_W83667HG;
0054 }
0055 
0056 /* write val to config reg */
0057 static inline void nvt_cr_write(struct nvt_dev *nvt, u8 val, u8 reg)
0058 {
0059     outb(reg, nvt->cr_efir);
0060     outb(val, nvt->cr_efdr);
0061 }
0062 
0063 /* read val from config reg */
0064 static inline u8 nvt_cr_read(struct nvt_dev *nvt, u8 reg)
0065 {
0066     outb(reg, nvt->cr_efir);
0067     return inb(nvt->cr_efdr);
0068 }
0069 
0070 /* update config register bit without changing other bits */
0071 static inline void nvt_set_reg_bit(struct nvt_dev *nvt, u8 val, u8 reg)
0072 {
0073     u8 tmp = nvt_cr_read(nvt, reg) | val;
0074     nvt_cr_write(nvt, tmp, reg);
0075 }
0076 
0077 /* enter extended function mode */
0078 static inline int nvt_efm_enable(struct nvt_dev *nvt)
0079 {
0080     if (!request_muxed_region(nvt->cr_efir, 2, NVT_DRIVER_NAME))
0081         return -EBUSY;
0082 
0083     /* Enabling Extended Function Mode explicitly requires writing 2x */
0084     outb(EFER_EFM_ENABLE, nvt->cr_efir);
0085     outb(EFER_EFM_ENABLE, nvt->cr_efir);
0086 
0087     return 0;
0088 }
0089 
0090 /* exit extended function mode */
0091 static inline void nvt_efm_disable(struct nvt_dev *nvt)
0092 {
0093     outb(EFER_EFM_DISABLE, nvt->cr_efir);
0094 
0095     release_region(nvt->cr_efir, 2);
0096 }
0097 
0098 /*
0099  * When you want to address a specific logical device, write its logical
0100  * device number to CR_LOGICAL_DEV_SEL, then enable/disable by writing
0101  * 0x1/0x0 respectively to CR_LOGICAL_DEV_EN.
0102  */
0103 static inline void nvt_select_logical_dev(struct nvt_dev *nvt, u8 ldev)
0104 {
0105     nvt_cr_write(nvt, ldev, CR_LOGICAL_DEV_SEL);
0106 }
0107 
0108 /* select and enable logical device with setting EFM mode*/
0109 static inline void nvt_enable_logical_dev(struct nvt_dev *nvt, u8 ldev)
0110 {
0111     nvt_efm_enable(nvt);
0112     nvt_select_logical_dev(nvt, ldev);
0113     nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
0114     nvt_efm_disable(nvt);
0115 }
0116 
0117 /* select and disable logical device with setting EFM mode*/
0118 static inline void nvt_disable_logical_dev(struct nvt_dev *nvt, u8 ldev)
0119 {
0120     nvt_efm_enable(nvt);
0121     nvt_select_logical_dev(nvt, ldev);
0122     nvt_cr_write(nvt, LOGICAL_DEV_DISABLE, CR_LOGICAL_DEV_EN);
0123     nvt_efm_disable(nvt);
0124 }
0125 
0126 /* write val to cir config register */
0127 static inline void nvt_cir_reg_write(struct nvt_dev *nvt, u8 val, u8 offset)
0128 {
0129     outb(val, nvt->cir_addr + offset);
0130 }
0131 
0132 /* read val from cir config register */
0133 static u8 nvt_cir_reg_read(struct nvt_dev *nvt, u8 offset)
0134 {
0135     return inb(nvt->cir_addr + offset);
0136 }
0137 
0138 /* write val to cir wake register */
0139 static inline void nvt_cir_wake_reg_write(struct nvt_dev *nvt,
0140                       u8 val, u8 offset)
0141 {
0142     outb(val, nvt->cir_wake_addr + offset);
0143 }
0144 
0145 /* read val from cir wake config register */
0146 static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
0147 {
0148     return inb(nvt->cir_wake_addr + offset);
0149 }
0150 
0151 /* don't override io address if one is set already */
0152 static void nvt_set_ioaddr(struct nvt_dev *nvt, unsigned long *ioaddr)
0153 {
0154     unsigned long old_addr;
0155 
0156     old_addr = nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8;
0157     old_addr |= nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO);
0158 
0159     if (old_addr)
0160         *ioaddr = old_addr;
0161     else {
0162         nvt_cr_write(nvt, *ioaddr >> 8, CR_CIR_BASE_ADDR_HI);
0163         nvt_cr_write(nvt, *ioaddr & 0xff, CR_CIR_BASE_ADDR_LO);
0164     }
0165 }
0166 
0167 static void nvt_write_wakeup_codes(struct rc_dev *dev,
0168                    const u8 *wbuf, int count)
0169 {
0170     u8 tolerance, config;
0171     struct nvt_dev *nvt = dev->priv;
0172     unsigned long flags;
0173     int i;
0174 
0175     /* hardcode the tolerance to 10% */
0176     tolerance = DIV_ROUND_UP(count, 10);
0177 
0178     spin_lock_irqsave(&nvt->lock, flags);
0179 
0180     nvt_clear_cir_wake_fifo(nvt);
0181     nvt_cir_wake_reg_write(nvt, count, CIR_WAKE_FIFO_CMP_DEEP);
0182     nvt_cir_wake_reg_write(nvt, tolerance, CIR_WAKE_FIFO_CMP_TOL);
0183 
0184     config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
0185 
0186     /* enable writes to wake fifo */
0187     nvt_cir_wake_reg_write(nvt, config | CIR_WAKE_IRCON_MODE1,
0188                    CIR_WAKE_IRCON);
0189 
0190     if (count)
0191         pr_info("Wake samples (%d) =", count);
0192     else
0193         pr_info("Wake sample fifo cleared");
0194 
0195     for (i = 0; i < count; i++)
0196         nvt_cir_wake_reg_write(nvt, wbuf[i], CIR_WAKE_WR_FIFO_DATA);
0197 
0198     nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
0199 
0200     spin_unlock_irqrestore(&nvt->lock, flags);
0201 }
0202 
0203 static ssize_t wakeup_data_show(struct device *dev,
0204                 struct device_attribute *attr,
0205                 char *buf)
0206 {
0207     struct rc_dev *rc_dev = to_rc_dev(dev);
0208     struct nvt_dev *nvt = rc_dev->priv;
0209     int fifo_len, duration;
0210     unsigned long flags;
0211     ssize_t buf_len = 0;
0212     int i;
0213 
0214     spin_lock_irqsave(&nvt->lock, flags);
0215 
0216     fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
0217     fifo_len = min(fifo_len, WAKEUP_MAX_SIZE);
0218 
0219     /* go to first element to be read */
0220     while (nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX))
0221         nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
0222 
0223     for (i = 0; i < fifo_len; i++) {
0224         duration = nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY);
0225         duration = (duration & BUF_LEN_MASK) * SAMPLE_PERIOD;
0226         buf_len += scnprintf(buf + buf_len, PAGE_SIZE - buf_len,
0227                     "%d ", duration);
0228     }
0229     buf_len += scnprintf(buf + buf_len, PAGE_SIZE - buf_len, "\n");
0230 
0231     spin_unlock_irqrestore(&nvt->lock, flags);
0232 
0233     return buf_len;
0234 }
0235 
0236 static ssize_t wakeup_data_store(struct device *dev,
0237                  struct device_attribute *attr,
0238                  const char *buf, size_t len)
0239 {
0240     struct rc_dev *rc_dev = to_rc_dev(dev);
0241     u8 wake_buf[WAKEUP_MAX_SIZE];
0242     char **argv;
0243     int i, count;
0244     unsigned int val;
0245     ssize_t ret;
0246 
0247     argv = argv_split(GFP_KERNEL, buf, &count);
0248     if (!argv)
0249         return -ENOMEM;
0250     if (!count || count > WAKEUP_MAX_SIZE) {
0251         ret = -EINVAL;
0252         goto out;
0253     }
0254 
0255     for (i = 0; i < count; i++) {
0256         ret = kstrtouint(argv[i], 10, &val);
0257         if (ret)
0258             goto out;
0259         val = DIV_ROUND_CLOSEST(val, SAMPLE_PERIOD);
0260         if (!val || val > 0x7f) {
0261             ret = -EINVAL;
0262             goto out;
0263         }
0264         wake_buf[i] = val;
0265         /* sequence must start with a pulse */
0266         if (i % 2 == 0)
0267             wake_buf[i] |= BUF_PULSE_BIT;
0268     }
0269 
0270     nvt_write_wakeup_codes(rc_dev, wake_buf, count);
0271 
0272     ret = len;
0273 out:
0274     argv_free(argv);
0275     return ret;
0276 }
0277 static DEVICE_ATTR_RW(wakeup_data);
0278 
0279 /* dump current cir register contents */
0280 static void cir_dump_regs(struct nvt_dev *nvt)
0281 {
0282     nvt_efm_enable(nvt);
0283     nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
0284 
0285     pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
0286     pr_info(" * CR CIR ACTIVE :   0x%x\n",
0287         nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
0288     pr_info(" * CR CIR BASE ADDR: 0x%x\n",
0289         (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
0290         nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
0291     pr_info(" * CR CIR IRQ NUM:   0x%x\n",
0292         nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
0293 
0294     nvt_efm_disable(nvt);
0295 
0296     pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
0297     pr_info(" * IRCON:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
0298     pr_info(" * IRSTS:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
0299     pr_info(" * IREN:      0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
0300     pr_info(" * RXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
0301     pr_info(" * CP:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
0302     pr_info(" * CC:        0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
0303     pr_info(" * SLCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
0304     pr_info(" * SLCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
0305     pr_info(" * FIFOCON:   0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
0306     pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
0307     pr_info(" * SRXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
0308     pr_info(" * TXFCONT:   0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
0309     pr_info(" * STXFIFO:   0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
0310     pr_info(" * FCCH:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
0311     pr_info(" * FCCL:      0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
0312     pr_info(" * IRFSM:     0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
0313 }
0314 
0315 /* dump current cir wake register contents */
0316 static void cir_wake_dump_regs(struct nvt_dev *nvt)
0317 {
0318     u8 i, fifo_len;
0319 
0320     nvt_efm_enable(nvt);
0321     nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
0322 
0323     pr_info("%s: Dump CIR WAKE logical device registers:\n",
0324         NVT_DRIVER_NAME);
0325     pr_info(" * CR CIR WAKE ACTIVE :   0x%x\n",
0326         nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
0327     pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
0328         (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
0329         nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
0330     pr_info(" * CR CIR WAKE IRQ NUM:   0x%x\n",
0331         nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
0332 
0333     nvt_efm_disable(nvt);
0334 
0335     pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
0336     pr_info(" * IRCON:          0x%x\n",
0337         nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
0338     pr_info(" * IRSTS:          0x%x\n",
0339         nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
0340     pr_info(" * IREN:           0x%x\n",
0341         nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
0342     pr_info(" * FIFO CMP DEEP:  0x%x\n",
0343         nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
0344     pr_info(" * FIFO CMP TOL:   0x%x\n",
0345         nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
0346     pr_info(" * FIFO COUNT:     0x%x\n",
0347         nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
0348     pr_info(" * SLCH:           0x%x\n",
0349         nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
0350     pr_info(" * SLCL:           0x%x\n",
0351         nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
0352     pr_info(" * FIFOCON:        0x%x\n",
0353         nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
0354     pr_info(" * SRXFSTS:        0x%x\n",
0355         nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
0356     pr_info(" * SAMPLE RX FIFO: 0x%x\n",
0357         nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
0358     pr_info(" * WR FIFO DATA:   0x%x\n",
0359         nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
0360     pr_info(" * RD FIFO ONLY:   0x%x\n",
0361         nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
0362     pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
0363         nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
0364     pr_info(" * FIFO IGNORE:    0x%x\n",
0365         nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
0366     pr_info(" * IRFSM:          0x%x\n",
0367         nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
0368 
0369     fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
0370     pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
0371     pr_info("* Contents =");
0372     for (i = 0; i < fifo_len; i++)
0373         pr_cont(" %02x",
0374             nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
0375     pr_cont("\n");
0376 }
0377 
0378 static inline const char *nvt_find_chip(struct nvt_dev *nvt, int id)
0379 {
0380     int i;
0381 
0382     for (i = 0; i < ARRAY_SIZE(nvt_chips); i++)
0383         if ((id & SIO_ID_MASK) == nvt_chips[i].chip_ver) {
0384             nvt->chip_ver = nvt_chips[i].chip_ver;
0385             return nvt_chips[i].name;
0386         }
0387 
0388     return NULL;
0389 }
0390 
0391 
0392 /* detect hardware features */
0393 static int nvt_hw_detect(struct nvt_dev *nvt)
0394 {
0395     struct device *dev = nvt_get_dev(nvt);
0396     const char *chip_name;
0397     int chip_id;
0398 
0399     nvt_efm_enable(nvt);
0400 
0401     /* Check if we're wired for the alternate EFER setup */
0402     nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
0403     if (nvt->chip_major == 0xff) {
0404         nvt_efm_disable(nvt);
0405         nvt->cr_efir = CR_EFIR2;
0406         nvt->cr_efdr = CR_EFDR2;
0407         nvt_efm_enable(nvt);
0408         nvt->chip_major = nvt_cr_read(nvt, CR_CHIP_ID_HI);
0409     }
0410     nvt->chip_minor = nvt_cr_read(nvt, CR_CHIP_ID_LO);
0411 
0412     nvt_efm_disable(nvt);
0413 
0414     chip_id = nvt->chip_major << 8 | nvt->chip_minor;
0415     if (chip_id == NVT_INVALID) {
0416         dev_err(dev, "No device found on either EFM port\n");
0417         return -ENODEV;
0418     }
0419 
0420     chip_name = nvt_find_chip(nvt, chip_id);
0421 
0422     /* warn, but still let the driver load, if we don't know this chip */
0423     if (!chip_name)
0424         dev_warn(dev,
0425              "unknown chip, id: 0x%02x 0x%02x, it may not work...",
0426              nvt->chip_major, nvt->chip_minor);
0427     else
0428         dev_info(dev, "found %s or compatible: chip id: 0x%02x 0x%02x",
0429              chip_name, nvt->chip_major, nvt->chip_minor);
0430 
0431     return 0;
0432 }
0433 
0434 static void nvt_cir_ldev_init(struct nvt_dev *nvt)
0435 {
0436     u8 val, psreg, psmask, psval;
0437 
0438     if (is_w83667hg(nvt)) {
0439         psreg = CR_MULTIFUNC_PIN_SEL;
0440         psmask = MULTIFUNC_PIN_SEL_MASK;
0441         psval = MULTIFUNC_ENABLE_CIR | MULTIFUNC_ENABLE_CIRWB;
0442     } else {
0443         psreg = CR_OUTPUT_PIN_SEL;
0444         psmask = OUTPUT_PIN_SEL_MASK;
0445         psval = OUTPUT_ENABLE_CIR | OUTPUT_ENABLE_CIRWB;
0446     }
0447 
0448     /* output pin selection: enable CIR, with WB sensor enabled */
0449     val = nvt_cr_read(nvt, psreg);
0450     val &= psmask;
0451     val |= psval;
0452     nvt_cr_write(nvt, val, psreg);
0453 
0454     /* Select CIR logical device */
0455     nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
0456 
0457     nvt_set_ioaddr(nvt, &nvt->cir_addr);
0458 
0459     nvt_cr_write(nvt, nvt->cir_irq, CR_CIR_IRQ_RSRC);
0460 
0461     nvt_dbg("CIR initialized, base io port address: 0x%lx, irq: %d",
0462         nvt->cir_addr, nvt->cir_irq);
0463 }
0464 
0465 static void nvt_cir_wake_ldev_init(struct nvt_dev *nvt)
0466 {
0467     /* Select ACPI logical device and anable it */
0468     nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
0469     nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
0470 
0471     /* Enable CIR Wake via PSOUT# (Pin60) */
0472     nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
0473 
0474     /* enable pme interrupt of cir wakeup event */
0475     nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
0476 
0477     /* Select CIR Wake logical device */
0478     nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
0479 
0480     nvt_set_ioaddr(nvt, &nvt->cir_wake_addr);
0481 
0482     nvt_dbg("CIR Wake initialized, base io port address: 0x%lx",
0483         nvt->cir_wake_addr);
0484 }
0485 
0486 /* clear out the hardware's cir rx fifo */
0487 static void nvt_clear_cir_fifo(struct nvt_dev *nvt)
0488 {
0489     u8 val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
0490     nvt_cir_reg_write(nvt, val | CIR_FIFOCON_RXFIFOCLR, CIR_FIFOCON);
0491 }
0492 
0493 /* clear out the hardware's cir wake rx fifo */
0494 static void nvt_clear_cir_wake_fifo(struct nvt_dev *nvt)
0495 {
0496     u8 val, config;
0497 
0498     config = nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON);
0499 
0500     /* clearing wake fifo works in learning mode only */
0501     nvt_cir_wake_reg_write(nvt, config & ~CIR_WAKE_IRCON_MODE0,
0502                    CIR_WAKE_IRCON);
0503 
0504     val = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON);
0505     nvt_cir_wake_reg_write(nvt, val | CIR_WAKE_FIFOCON_RXFIFOCLR,
0506                    CIR_WAKE_FIFOCON);
0507 
0508     nvt_cir_wake_reg_write(nvt, config, CIR_WAKE_IRCON);
0509 }
0510 
0511 /* clear out the hardware's cir tx fifo */
0512 static void nvt_clear_tx_fifo(struct nvt_dev *nvt)
0513 {
0514     u8 val;
0515 
0516     val = nvt_cir_reg_read(nvt, CIR_FIFOCON);
0517     nvt_cir_reg_write(nvt, val | CIR_FIFOCON_TXFIFOCLR, CIR_FIFOCON);
0518 }
0519 
0520 /* enable RX Trigger Level Reach and Packet End interrupts */
0521 static void nvt_set_cir_iren(struct nvt_dev *nvt)
0522 {
0523     u8 iren;
0524 
0525     iren = CIR_IREN_RTR | CIR_IREN_PE | CIR_IREN_RFO;
0526     nvt_cir_reg_write(nvt, iren, CIR_IREN);
0527 }
0528 
0529 static void nvt_cir_regs_init(struct nvt_dev *nvt)
0530 {
0531     nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
0532 
0533     /* set sample limit count (PE interrupt raised when reached) */
0534     nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT >> 8, CIR_SLCH);
0535     nvt_cir_reg_write(nvt, CIR_RX_LIMIT_COUNT & 0xff, CIR_SLCL);
0536 
0537     /* set fifo irq trigger levels */
0538     nvt_cir_reg_write(nvt, CIR_FIFOCON_TX_TRIGGER_LEV |
0539               CIR_FIFOCON_RX_TRIGGER_LEV, CIR_FIFOCON);
0540 
0541     /* clear hardware rx and tx fifos */
0542     nvt_clear_cir_fifo(nvt);
0543     nvt_clear_tx_fifo(nvt);
0544 
0545     nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
0546 }
0547 
0548 static void nvt_cir_wake_regs_init(struct nvt_dev *nvt)
0549 {
0550     nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
0551 
0552     /*
0553      * Disable RX, set specific carrier on = low, off = high,
0554      * and sample period (currently 50us)
0555      */
0556     nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 |
0557                    CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
0558                    CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
0559                    CIR_WAKE_IRCON);
0560 
0561     /* clear any and all stray interrupts */
0562     nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
0563 }
0564 
0565 static void nvt_enable_wake(struct nvt_dev *nvt)
0566 {
0567     unsigned long flags;
0568 
0569     nvt_efm_enable(nvt);
0570 
0571     nvt_select_logical_dev(nvt, LOGICAL_DEV_ACPI);
0572     nvt_set_reg_bit(nvt, CIR_WAKE_ENABLE_BIT, CR_ACPI_CIR_WAKE);
0573     nvt_set_reg_bit(nvt, PME_INTR_CIR_PASS_BIT, CR_ACPI_IRQ_EVENTS2);
0574 
0575     nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
0576     nvt_cr_write(nvt, LOGICAL_DEV_ENABLE, CR_LOGICAL_DEV_EN);
0577 
0578     nvt_efm_disable(nvt);
0579 
0580     spin_lock_irqsave(&nvt->lock, flags);
0581 
0582     nvt_cir_wake_reg_write(nvt, CIR_WAKE_IRCON_MODE0 | CIR_WAKE_IRCON_RXEN |
0583                    CIR_WAKE_IRCON_R | CIR_WAKE_IRCON_RXINV |
0584                    CIR_WAKE_IRCON_SAMPLE_PERIOD_SEL,
0585                    CIR_WAKE_IRCON);
0586     nvt_cir_wake_reg_write(nvt, 0xff, CIR_WAKE_IRSTS);
0587     nvt_cir_wake_reg_write(nvt, 0, CIR_WAKE_IREN);
0588 
0589     spin_unlock_irqrestore(&nvt->lock, flags);
0590 }
0591 
0592 #if 0 /* Currently unused */
0593 /* rx carrier detect only works in learning mode, must be called w/lock */
0594 static u32 nvt_rx_carrier_detect(struct nvt_dev *nvt)
0595 {
0596     u32 count, carrier, duration = 0;
0597     int i;
0598 
0599     count = nvt_cir_reg_read(nvt, CIR_FCCL) |
0600         nvt_cir_reg_read(nvt, CIR_FCCH) << 8;
0601 
0602     for (i = 0; i < nvt->pkts; i++) {
0603         if (nvt->buf[i] & BUF_PULSE_BIT)
0604             duration += nvt->buf[i] & BUF_LEN_MASK;
0605     }
0606 
0607     duration *= SAMPLE_PERIOD;
0608 
0609     if (!count || !duration) {
0610         dev_notice(nvt_get_dev(nvt),
0611                "Unable to determine carrier! (c:%u, d:%u)",
0612                count, duration);
0613         return 0;
0614     }
0615 
0616     carrier = MS_TO_NS(count) / duration;
0617 
0618     if ((carrier > MAX_CARRIER) || (carrier < MIN_CARRIER))
0619         nvt_dbg("WTF? Carrier frequency out of range!");
0620 
0621     nvt_dbg("Carrier frequency: %u (count %u, duration %u)",
0622         carrier, count, duration);
0623 
0624     return carrier;
0625 }
0626 #endif
0627 
0628 static int nvt_ir_raw_set_wakeup_filter(struct rc_dev *dev,
0629                     struct rc_scancode_filter *sc_filter)
0630 {
0631     u8 buf_val;
0632     int i, ret, count;
0633     unsigned int val;
0634     struct ir_raw_event *raw;
0635     u8 wake_buf[WAKEUP_MAX_SIZE];
0636     bool complete;
0637 
0638     /* Require mask to be set */
0639     if (!sc_filter->mask)
0640         return 0;
0641 
0642     raw = kmalloc_array(WAKEUP_MAX_SIZE, sizeof(*raw), GFP_KERNEL);
0643     if (!raw)
0644         return -ENOMEM;
0645 
0646     ret = ir_raw_encode_scancode(dev->wakeup_protocol, sc_filter->data,
0647                      raw, WAKEUP_MAX_SIZE);
0648     complete = (ret != -ENOBUFS);
0649     if (!complete)
0650         ret = WAKEUP_MAX_SIZE;
0651     else if (ret < 0)
0652         goto out_raw;
0653 
0654     /* Inspect the ir samples */
0655     for (i = 0, count = 0; i < ret && count < WAKEUP_MAX_SIZE; ++i) {
0656         val = raw[i].duration / SAMPLE_PERIOD;
0657 
0658         /* Split too large values into several smaller ones */
0659         while (val > 0 && count < WAKEUP_MAX_SIZE) {
0660             /* Skip last value for better comparison tolerance */
0661             if (complete && i == ret - 1 && val < BUF_LEN_MASK)
0662                 break;
0663 
0664             /* Clamp values to BUF_LEN_MASK at most */
0665             buf_val = (val > BUF_LEN_MASK) ? BUF_LEN_MASK : val;
0666 
0667             wake_buf[count] = buf_val;
0668             val -= buf_val;
0669             if ((raw[i]).pulse)
0670                 wake_buf[count] |= BUF_PULSE_BIT;
0671             count++;
0672         }
0673     }
0674 
0675     nvt_write_wakeup_codes(dev, wake_buf, count);
0676     ret = 0;
0677 out_raw:
0678     kfree(raw);
0679 
0680     return ret;
0681 }
0682 
0683 /* dump contents of the last rx buffer we got from the hw rx fifo */
0684 static void nvt_dump_rx_buf(struct nvt_dev *nvt)
0685 {
0686     int i;
0687 
0688     printk(KERN_DEBUG "%s (len %d): ", __func__, nvt->pkts);
0689     for (i = 0; (i < nvt->pkts) && (i < RX_BUF_LEN); i++)
0690         printk(KERN_CONT "0x%02x ", nvt->buf[i]);
0691     printk(KERN_CONT "\n");
0692 }
0693 
0694 /*
0695  * Process raw data in rx driver buffer, store it in raw IR event kfifo,
0696  * trigger decode when appropriate.
0697  *
0698  * We get IR data samples one byte at a time. If the msb is set, its a pulse,
0699  * otherwise its a space. The lower 7 bits are the count of SAMPLE_PERIOD
0700  * (default 50us) intervals for that pulse/space. A discrete signal is
0701  * followed by a series of 0x7f packets, then either 0x7<something> or 0x80
0702  * to signal more IR coming (repeats) or end of IR, respectively. We store
0703  * sample data in the raw event kfifo until we see 0x7<something> (except f)
0704  * or 0x80, at which time, we trigger a decode operation.
0705  */
0706 static void nvt_process_rx_ir_data(struct nvt_dev *nvt)
0707 {
0708     struct ir_raw_event rawir = {};
0709     u8 sample;
0710     int i;
0711 
0712     nvt_dbg_verbose("%s firing", __func__);
0713 
0714     if (debug)
0715         nvt_dump_rx_buf(nvt);
0716 
0717     nvt_dbg_verbose("Processing buffer of len %d", nvt->pkts);
0718 
0719     for (i = 0; i < nvt->pkts; i++) {
0720         sample = nvt->buf[i];
0721 
0722         rawir.pulse = ((sample & BUF_PULSE_BIT) != 0);
0723         rawir.duration = (sample & BUF_LEN_MASK) * SAMPLE_PERIOD;
0724 
0725         nvt_dbg("Storing %s with duration %d",
0726             rawir.pulse ? "pulse" : "space", rawir.duration);
0727 
0728         ir_raw_event_store_with_filter(nvt->rdev, &rawir);
0729     }
0730 
0731     nvt->pkts = 0;
0732 
0733     nvt_dbg("Calling ir_raw_event_handle\n");
0734     ir_raw_event_handle(nvt->rdev);
0735 
0736     nvt_dbg_verbose("%s done", __func__);
0737 }
0738 
0739 static void nvt_handle_rx_fifo_overrun(struct nvt_dev *nvt)
0740 {
0741     dev_warn(nvt_get_dev(nvt), "RX FIFO overrun detected, flushing data!");
0742 
0743     nvt->pkts = 0;
0744     nvt_clear_cir_fifo(nvt);
0745     ir_raw_event_overflow(nvt->rdev);
0746 }
0747 
0748 /* copy data from hardware rx fifo into driver buffer */
0749 static void nvt_get_rx_ir_data(struct nvt_dev *nvt)
0750 {
0751     u8 fifocount;
0752     int i;
0753 
0754     /* Get count of how many bytes to read from RX FIFO */
0755     fifocount = nvt_cir_reg_read(nvt, CIR_RXFCONT);
0756 
0757     nvt_dbg("attempting to fetch %u bytes from hw rx fifo", fifocount);
0758 
0759     /* Read fifocount bytes from CIR Sample RX FIFO register */
0760     for (i = 0; i < fifocount; i++)
0761         nvt->buf[i] = nvt_cir_reg_read(nvt, CIR_SRXFIFO);
0762 
0763     nvt->pkts = fifocount;
0764     nvt_dbg("%s: pkts now %d", __func__, nvt->pkts);
0765 
0766     nvt_process_rx_ir_data(nvt);
0767 }
0768 
0769 static void nvt_cir_log_irqs(u8 status, u8 iren)
0770 {
0771     nvt_dbg("IRQ 0x%02x (IREN 0x%02x) :%s%s%s%s%s%s%s%s%s",
0772         status, iren,
0773         status & CIR_IRSTS_RDR  ? " RDR"    : "",
0774         status & CIR_IRSTS_RTR  ? " RTR"    : "",
0775         status & CIR_IRSTS_PE   ? " PE"     : "",
0776         status & CIR_IRSTS_RFO  ? " RFO"    : "",
0777         status & CIR_IRSTS_TE   ? " TE"     : "",
0778         status & CIR_IRSTS_TTR  ? " TTR"    : "",
0779         status & CIR_IRSTS_TFU  ? " TFU"    : "",
0780         status & CIR_IRSTS_GH   ? " GH"     : "",
0781         status & ~(CIR_IRSTS_RDR | CIR_IRSTS_RTR | CIR_IRSTS_PE |
0782                CIR_IRSTS_RFO | CIR_IRSTS_TE | CIR_IRSTS_TTR |
0783                CIR_IRSTS_TFU | CIR_IRSTS_GH) ? " ?" : "");
0784 }
0785 
0786 /* interrupt service routine for incoming and outgoing CIR data */
0787 static irqreturn_t nvt_cir_isr(int irq, void *data)
0788 {
0789     struct nvt_dev *nvt = data;
0790     u8 status, iren;
0791 
0792     nvt_dbg_verbose("%s firing", __func__);
0793 
0794     spin_lock(&nvt->lock);
0795 
0796     /*
0797      * Get IR Status register contents. Write 1 to ack/clear
0798      *
0799      * bit: reg name      - description
0800      *   7: CIR_IRSTS_RDR - RX Data Ready
0801      *   6: CIR_IRSTS_RTR - RX FIFO Trigger Level Reach
0802      *   5: CIR_IRSTS_PE  - Packet End
0803      *   4: CIR_IRSTS_RFO - RX FIFO Overrun (RDR will also be set)
0804      *   3: CIR_IRSTS_TE  - TX FIFO Empty
0805      *   2: CIR_IRSTS_TTR - TX FIFO Trigger Level Reach
0806      *   1: CIR_IRSTS_TFU - TX FIFO Underrun
0807      *   0: CIR_IRSTS_GH  - Min Length Detected
0808      */
0809     status = nvt_cir_reg_read(nvt, CIR_IRSTS);
0810     iren = nvt_cir_reg_read(nvt, CIR_IREN);
0811 
0812     /* At least NCT6779D creates a spurious interrupt when the
0813      * logical device is being disabled.
0814      */
0815     if (status == 0xff && iren == 0xff) {
0816         spin_unlock(&nvt->lock);
0817         nvt_dbg_verbose("Spurious interrupt detected");
0818         return IRQ_HANDLED;
0819     }
0820 
0821     /* IRQ may be shared with CIR WAKE, therefore check for each
0822      * status bit whether the related interrupt source is enabled
0823      */
0824     if (!(status & iren)) {
0825         spin_unlock(&nvt->lock);
0826         nvt_dbg_verbose("%s exiting, IRSTS 0x0", __func__);
0827         return IRQ_NONE;
0828     }
0829 
0830     /* ack/clear all irq flags we've got */
0831     nvt_cir_reg_write(nvt, status, CIR_IRSTS);
0832     nvt_cir_reg_write(nvt, 0, CIR_IRSTS);
0833 
0834     nvt_cir_log_irqs(status, iren);
0835 
0836     if (status & CIR_IRSTS_RFO)
0837         nvt_handle_rx_fifo_overrun(nvt);
0838     else if (status & (CIR_IRSTS_RTR | CIR_IRSTS_PE))
0839         nvt_get_rx_ir_data(nvt);
0840 
0841     spin_unlock(&nvt->lock);
0842 
0843     nvt_dbg_verbose("%s done", __func__);
0844     return IRQ_HANDLED;
0845 }
0846 
0847 static void nvt_enable_cir(struct nvt_dev *nvt)
0848 {
0849     unsigned long flags;
0850 
0851     /* enable the CIR logical device */
0852     nvt_enable_logical_dev(nvt, LOGICAL_DEV_CIR);
0853 
0854     spin_lock_irqsave(&nvt->lock, flags);
0855 
0856     /*
0857      * Enable TX and RX, specify carrier on = low, off = high, and set
0858      * sample period (currently 50us)
0859      */
0860     nvt_cir_reg_write(nvt, CIR_IRCON_TXEN | CIR_IRCON_RXEN |
0861               CIR_IRCON_RXINV | CIR_IRCON_SAMPLE_PERIOD_SEL,
0862               CIR_IRCON);
0863 
0864     /* clear all pending interrupts */
0865     nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
0866 
0867     /* enable interrupts */
0868     nvt_set_cir_iren(nvt);
0869 
0870     spin_unlock_irqrestore(&nvt->lock, flags);
0871 }
0872 
0873 static void nvt_disable_cir(struct nvt_dev *nvt)
0874 {
0875     unsigned long flags;
0876 
0877     spin_lock_irqsave(&nvt->lock, flags);
0878 
0879     /* disable CIR interrupts */
0880     nvt_cir_reg_write(nvt, 0, CIR_IREN);
0881 
0882     /* clear any and all pending interrupts */
0883     nvt_cir_reg_write(nvt, 0xff, CIR_IRSTS);
0884 
0885     /* clear all function enable flags */
0886     nvt_cir_reg_write(nvt, 0, CIR_IRCON);
0887 
0888     /* clear hardware rx and tx fifos */
0889     nvt_clear_cir_fifo(nvt);
0890     nvt_clear_tx_fifo(nvt);
0891 
0892     spin_unlock_irqrestore(&nvt->lock, flags);
0893 
0894     /* disable the CIR logical device */
0895     nvt_disable_logical_dev(nvt, LOGICAL_DEV_CIR);
0896 }
0897 
0898 static int nvt_open(struct rc_dev *dev)
0899 {
0900     struct nvt_dev *nvt = dev->priv;
0901 
0902     nvt_enable_cir(nvt);
0903 
0904     return 0;
0905 }
0906 
0907 static void nvt_close(struct rc_dev *dev)
0908 {
0909     struct nvt_dev *nvt = dev->priv;
0910 
0911     nvt_disable_cir(nvt);
0912 }
0913 
0914 /* Allocate memory, probe hardware, and initialize everything */
0915 static int nvt_probe(struct pnp_dev *pdev, const struct pnp_device_id *dev_id)
0916 {
0917     struct nvt_dev *nvt;
0918     struct rc_dev *rdev;
0919     int ret;
0920 
0921     nvt = devm_kzalloc(&pdev->dev, sizeof(struct nvt_dev), GFP_KERNEL);
0922     if (!nvt)
0923         return -ENOMEM;
0924 
0925     /* input device for IR remote */
0926     nvt->rdev = devm_rc_allocate_device(&pdev->dev, RC_DRIVER_IR_RAW);
0927     if (!nvt->rdev)
0928         return -ENOMEM;
0929     rdev = nvt->rdev;
0930 
0931     /* activate pnp device */
0932     ret = pnp_activate_dev(pdev);
0933     if (ret) {
0934         dev_err(&pdev->dev, "Could not activate PNP device!\n");
0935         return ret;
0936     }
0937 
0938     /* validate pnp resources */
0939     if (!pnp_port_valid(pdev, 0) ||
0940         pnp_port_len(pdev, 0) < CIR_IOREG_LENGTH) {
0941         dev_err(&pdev->dev, "IR PNP Port not valid!\n");
0942         return -EINVAL;
0943     }
0944 
0945     if (!pnp_irq_valid(pdev, 0)) {
0946         dev_err(&pdev->dev, "PNP IRQ not valid!\n");
0947         return -EINVAL;
0948     }
0949 
0950     if (!pnp_port_valid(pdev, 1) ||
0951         pnp_port_len(pdev, 1) < CIR_IOREG_LENGTH) {
0952         dev_err(&pdev->dev, "Wake PNP Port not valid!\n");
0953         return -EINVAL;
0954     }
0955 
0956     nvt->cir_addr = pnp_port_start(pdev, 0);
0957     nvt->cir_irq  = pnp_irq(pdev, 0);
0958 
0959     nvt->cir_wake_addr = pnp_port_start(pdev, 1);
0960 
0961     nvt->cr_efir = CR_EFIR;
0962     nvt->cr_efdr = CR_EFDR;
0963 
0964     spin_lock_init(&nvt->lock);
0965 
0966     pnp_set_drvdata(pdev, nvt);
0967 
0968     ret = nvt_hw_detect(nvt);
0969     if (ret)
0970         return ret;
0971 
0972     /* Initialize CIR & CIR Wake Logical Devices */
0973     nvt_efm_enable(nvt);
0974     nvt_cir_ldev_init(nvt);
0975     nvt_cir_wake_ldev_init(nvt);
0976     nvt_efm_disable(nvt);
0977 
0978     /*
0979      * Initialize CIR & CIR Wake Config Registers
0980      * and enable logical devices
0981      */
0982     nvt_cir_regs_init(nvt);
0983     nvt_cir_wake_regs_init(nvt);
0984 
0985     /* Set up the rc device */
0986     rdev->priv = nvt;
0987     rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
0988     rdev->allowed_wakeup_protocols = RC_PROTO_BIT_ALL_IR_ENCODER;
0989     rdev->encode_wakeup = true;
0990     rdev->open = nvt_open;
0991     rdev->close = nvt_close;
0992     rdev->s_wakeup_filter = nvt_ir_raw_set_wakeup_filter;
0993     rdev->device_name = "Nuvoton w836x7hg Infrared Remote Transceiver";
0994     rdev->input_phys = "nuvoton/cir0";
0995     rdev->input_id.bustype = BUS_HOST;
0996     rdev->input_id.vendor = PCI_VENDOR_ID_WINBOND2;
0997     rdev->input_id.product = nvt->chip_major;
0998     rdev->input_id.version = nvt->chip_minor;
0999     rdev->driver_name = NVT_DRIVER_NAME;
1000     rdev->map_name = RC_MAP_RC6_MCE;
1001     rdev->timeout = MS_TO_US(100);
1002     /* rx resolution is hardwired to 50us atm, 1, 25, 100 also possible */
1003     rdev->rx_resolution = CIR_SAMPLE_PERIOD;
1004 #if 0
1005     rdev->min_timeout = XYZ;
1006     rdev->max_timeout = XYZ;
1007 #endif
1008     ret = devm_rc_register_device(&pdev->dev, rdev);
1009     if (ret)
1010         return ret;
1011 
1012     /* now claim resources */
1013     if (!devm_request_region(&pdev->dev, nvt->cir_addr,
1014                 CIR_IOREG_LENGTH, NVT_DRIVER_NAME))
1015         return -EBUSY;
1016 
1017     ret = devm_request_irq(&pdev->dev, nvt->cir_irq, nvt_cir_isr,
1018                    IRQF_SHARED, NVT_DRIVER_NAME, nvt);
1019     if (ret)
1020         return ret;
1021 
1022     if (!devm_request_region(&pdev->dev, nvt->cir_wake_addr,
1023                 CIR_IOREG_LENGTH, NVT_DRIVER_NAME "-wake"))
1024         return -EBUSY;
1025 
1026     ret = device_create_file(&rdev->dev, &dev_attr_wakeup_data);
1027     if (ret)
1028         return ret;
1029 
1030     device_init_wakeup(&pdev->dev, true);
1031 
1032     dev_notice(&pdev->dev, "driver has been successfully loaded\n");
1033     if (debug) {
1034         cir_dump_regs(nvt);
1035         cir_wake_dump_regs(nvt);
1036     }
1037 
1038     return 0;
1039 }
1040 
1041 static void nvt_remove(struct pnp_dev *pdev)
1042 {
1043     struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1044 
1045     device_remove_file(&nvt->rdev->dev, &dev_attr_wakeup_data);
1046 
1047     nvt_disable_cir(nvt);
1048 
1049     /* enable CIR Wake (for IR power-on) */
1050     nvt_enable_wake(nvt);
1051 }
1052 
1053 static int nvt_suspend(struct pnp_dev *pdev, pm_message_t state)
1054 {
1055     struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1056 
1057     nvt_dbg("%s called", __func__);
1058 
1059     mutex_lock(&nvt->rdev->lock);
1060     if (nvt->rdev->users)
1061         nvt_disable_cir(nvt);
1062     mutex_unlock(&nvt->rdev->lock);
1063 
1064     /* make sure wake is enabled */
1065     nvt_enable_wake(nvt);
1066 
1067     return 0;
1068 }
1069 
1070 static int nvt_resume(struct pnp_dev *pdev)
1071 {
1072     struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1073 
1074     nvt_dbg("%s called", __func__);
1075 
1076     nvt_cir_regs_init(nvt);
1077     nvt_cir_wake_regs_init(nvt);
1078 
1079     mutex_lock(&nvt->rdev->lock);
1080     if (nvt->rdev->users)
1081         nvt_enable_cir(nvt);
1082     mutex_unlock(&nvt->rdev->lock);
1083 
1084     return 0;
1085 }
1086 
1087 static void nvt_shutdown(struct pnp_dev *pdev)
1088 {
1089     struct nvt_dev *nvt = pnp_get_drvdata(pdev);
1090 
1091     nvt_enable_wake(nvt);
1092 }
1093 
1094 static const struct pnp_device_id nvt_ids[] = {
1095     { "WEC0530", 0 },   /* CIR */
1096     { "NTN0530", 0 },   /* CIR for new chip's pnp id*/
1097     { "", 0 },
1098 };
1099 
1100 static struct pnp_driver nvt_driver = {
1101     .name       = NVT_DRIVER_NAME,
1102     .id_table   = nvt_ids,
1103     .flags      = PNP_DRIVER_RES_DO_NOT_CHANGE,
1104     .probe      = nvt_probe,
1105     .remove     = nvt_remove,
1106     .suspend    = nvt_suspend,
1107     .resume     = nvt_resume,
1108     .shutdown   = nvt_shutdown,
1109 };
1110 
1111 module_param(debug, int, S_IRUGO | S_IWUSR);
1112 MODULE_PARM_DESC(debug, "Enable debugging output");
1113 
1114 MODULE_DEVICE_TABLE(pnp, nvt_ids);
1115 MODULE_DESCRIPTION("Nuvoton W83667HG-A & W83677HG-I CIR driver");
1116 
1117 MODULE_AUTHOR("Jarod Wilson <jarod@redhat.com>");
1118 MODULE_LICENSE("GPL");
1119 
1120 module_pnp_driver(nvt_driver);
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