media/rc/mtk-cir.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for Mediatek IR Receiver Controller
0004  *
0005  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
0006  */
0007
0008 #include <linux/clk.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/module.h>
0011 #include <linux/of_platform.h>
0012 #include <linux/reset.h>
0013 #include <media/rc-core.h>
0014
0015 #define MTK_IR_DEV KBUILD_MODNAME
0016
0017 /* Register to enable PWM and IR */
0018 #define MTK_CONFIG_HIGH_REG       0x0c
0019
0020 /* Bit to enable IR pulse width detection */
0021 #define MTK_PWM_EN        BIT(13)
0022
0023 /*
0024  * Register to setting ok count whose unit based on hardware sampling period
0025  * indicating IR receiving completion and then making IRQ fires
0026  */
0027 #define MTK_OK_COUNT_MASK     (GENMASK(22, 16))
0028 #define MTK_OK_COUNT(x)       ((x) << 16)
0029
0030 /* Bit to enable IR hardware function */
0031 #define MTK_IR_EN         BIT(0)
0032
0033 /* Bit to restart IR receiving */
0034 #define MTK_IRCLR         BIT(0)
0035
0036 /* Fields containing pulse width data */
0037 #define MTK_WIDTH_MASK        (GENMASK(7, 0))
0038
0039 /* IR threshold */
0040 #define MTK_IRTHD        0x14
0041 #define MTK_DG_CNT_MASK      (GENMASK(12, 8))
0042 #define MTK_DG_CNT(x)        ((x) << 8)
0043
0044 /* Bit to enable interrupt */
0045 #define MTK_IRINT_EN          BIT(0)
0046
0047 /* Bit to clear interrupt status */
0048 #define MTK_IRINT_CLR         BIT(0)
0049
0050 /* Maximum count of samples */
0051 #define MTK_MAX_SAMPLES       0xff
0052 /* Indicate the end of IR message */
0053 #define MTK_IR_END(v, p)      ((v) == MTK_MAX_SAMPLES && (p) == 0)
0054 /* Number of registers to record the pulse width */
0055 #define MTK_CHKDATA_SZ        17
0056 /* Sample period in us */
0057 #define MTK_IR_SAMPLE         46
0058
0059 enum mtk_fields {
0060     /* Register to setting software sampling period */
0061     MTK_CHK_PERIOD,
0062     /* Register to setting hardware sampling period */
0063     MTK_HW_PERIOD,
0064 };
0065
0066 enum mtk_regs {
0067     /* Register to clear state of state machine */
0068     MTK_IRCLR_REG,
0069     /* Register containing pulse width data */
0070     MTK_CHKDATA_REG,
0071     /* Register to enable IR interrupt */
0072     MTK_IRINT_EN_REG,
0073     /* Register to ack IR interrupt */
0074     MTK_IRINT_CLR_REG
0075 };
0076
0077 static const u32 mt7623_regs[] = {
0078     [MTK_IRCLR_REG] =   0x20,
0079     [MTK_CHKDATA_REG] = 0x88,
0080     [MTK_IRINT_EN_REG] =    0xcc,
0081     [MTK_IRINT_CLR_REG] =   0xd0,
0082 };
0083
0084 static const u32 mt7622_regs[] = {
0085     [MTK_IRCLR_REG] =   0x18,
0086     [MTK_CHKDATA_REG] = 0x30,
0087     [MTK_IRINT_EN_REG] =    0x1c,
0088     [MTK_IRINT_CLR_REG] =   0x20,
0089 };
0090
0091 struct mtk_field_type {
0092     u32 reg;
0093     u8 offset;
0094     u32 mask;
0095 };
0096
0097 /*
0098  * struct mtk_ir_data - This is the structure holding all differences among
0099             various hardwares
0100  * @regs:       The pointer to the array holding registers offset
0101  * @fields:     The pointer to the array holding fields location
0102  * @div:        The internal divisor for the based reference clock
0103  * @ok_count:       The count indicating the completion of IR data
0104  *          receiving when count is reached
0105  * @hw_period:      The value indicating the hardware sampling period
0106  */
0107 struct mtk_ir_data {
0108     const u32 *regs;
0109     const struct mtk_field_type *fields;
0110     u8 div;
0111     u8 ok_count;
0112     u32 hw_period;
0113 };
0114
0115 static const struct mtk_field_type mt7623_fields[] = {
0116     [MTK_CHK_PERIOD] = {0x10, 8, GENMASK(20, 8)},
0117     [MTK_HW_PERIOD] = {0x10, 0, GENMASK(7, 0)},
0118 };
0119
0120 static const struct mtk_field_type mt7622_fields[] = {
0121     [MTK_CHK_PERIOD] = {0x24, 0, GENMASK(24, 0)},
0122     [MTK_HW_PERIOD] = {0x10, 0, GENMASK(24, 0)},
0123 };
0124
0125 /*
0126  * struct mtk_ir -  This is the main datasructure for holding the state
0127  *          of the driver
0128  * @dev:        The device pointer
0129  * @rc:         The rc instrance
0130  * @base:       The mapped register i/o base
0131  * @irq:        The IRQ that we are using
0132  * @clk:        The clock that IR internal is using
0133  * @bus:        The clock that software decoder is using
0134  * @data:       Holding specific data for vaious platform
0135  */
0136 struct mtk_ir {
0137     struct device   *dev;
0138     struct rc_dev   *rc;
0139     void __iomem    *base;
0140     int     irq;
0141     struct clk  *clk;
0142     struct clk  *bus;
0143     const struct mtk_ir_data *data;
0144 };
0145
0146 static inline u32 mtk_chkdata_reg(struct mtk_ir *ir, u32 i)
0147 {
0148     return ir->data->regs[MTK_CHKDATA_REG] + 4 * i;
0149 }
0150
0151 static inline u32 mtk_chk_period(struct mtk_ir *ir)
0152 {
0153     u32 val;
0154
0155     /*
0156      * Period for software decoder used in the
0157      * unit of raw software sampling
0158      */
0159     val = DIV_ROUND_CLOSEST(clk_get_rate(ir->bus),
0160                 USEC_PER_SEC * ir->data->div / MTK_IR_SAMPLE);
0161
0162     dev_dbg(ir->dev, "@pwm clk  = \t%lu\n",
0163         clk_get_rate(ir->bus) / ir->data->div);
0164     dev_dbg(ir->dev, "@chkperiod = %08x\n", val);
0165
0166     return val;
0167 }
0168
0169 static void mtk_w32_mask(struct mtk_ir *ir, u32 val, u32 mask, unsigned int reg)
0170 {
0171     u32 tmp;
0172
0173     tmp = __raw_readl(ir->base + reg);
0174     tmp = (tmp & ~mask) | val;
0175     __raw_writel(tmp, ir->base + reg);
0176 }
0177
0178 static void mtk_w32(struct mtk_ir *ir, u32 val, unsigned int reg)
0179 {
0180     __raw_writel(val, ir->base + reg);
0181 }
0182
0183 static u32 mtk_r32(struct mtk_ir *ir, unsigned int reg)
0184 {
0185     return __raw_readl(ir->base + reg);
0186 }
0187
0188 static inline void mtk_irq_disable(struct mtk_ir *ir, u32 mask)
0189 {
0190     u32 val;
0191
0192     val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
0193     mtk_w32(ir, val & ~mask, ir->data->regs[MTK_IRINT_EN_REG]);
0194 }
0195
0196 static inline void mtk_irq_enable(struct mtk_ir *ir, u32 mask)
0197 {
0198     u32 val;
0199
0200     val = mtk_r32(ir, ir->data->regs[MTK_IRINT_EN_REG]);
0201     mtk_w32(ir, val | mask, ir->data->regs[MTK_IRINT_EN_REG]);
0202 }
0203
0204 static irqreturn_t mtk_ir_irq(int irqno, void *dev_id)
0205 {
0206     struct ir_raw_event rawir = {};
0207     struct mtk_ir *ir = dev_id;
0208     u32 i, j, val;
0209     u8 wid;
0210
0211     /*
0212      * Each pulse and space is encoded as a single byte, each byte
0213      * alternating between pulse and space. If a pulse or space is longer
0214      * than can be encoded in a single byte, it is encoded as the maximum
0215      * value 0xff.
0216      *
0217      * If a space is longer than ok_count (about 23ms), the value is
0218      * encoded as zero, and all following bytes are zero. Any IR that
0219      * follows will be presented in the next interrupt.
0220      *
0221      * If there are more than 68 (=MTK_CHKDATA_SZ * 4) pulses and spaces,
0222      * then the only the first 68 will be presented; the rest is lost.
0223      */
0224
0225     /* Handle all pulse and space IR controller captures */
0226     for (i = 0 ; i < MTK_CHKDATA_SZ ; i++) {
0227         val = mtk_r32(ir, mtk_chkdata_reg(ir, i));
0228         dev_dbg(ir->dev, "@reg%d=0x%08x\n", i, val);
0229
0230         for (j = 0 ; j < 4 ; j++) {
0231             wid = val & MTK_WIDTH_MASK;
0232             val >>= 8;
0233             rawir.pulse = !rawir.pulse;
0234             rawir.duration = wid * (MTK_IR_SAMPLE + 1);
0235             ir_raw_event_store_with_filter(ir->rc, &rawir);
0236         }
0237     }
0238
0239     /*
0240      * The maximum number of edges the IR controller can
0241      * hold is MTK_CHKDATA_SZ * 4. So if received IR messages
0242      * is over the limit, the last incomplete IR message would
0243      * be appended trailing space and still would be sent into
0244      * ir-rc-raw to decode. That helps it is possible that it
0245      * has enough information to decode a scancode even if the
0246      * trailing end of the message is missing.
0247      */
0248     if (!MTK_IR_END(wid, rawir.pulse)) {
0249         rawir.pulse = false;
0250         rawir.duration = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
0251         ir_raw_event_store_with_filter(ir->rc, &rawir);
0252     }
0253
0254     ir_raw_event_handle(ir->rc);
0255
0256     /*
0257      * Restart controller for the next receive that would
0258      * clear up all CHKDATA registers
0259      */
0260     mtk_w32_mask(ir, 0x1, MTK_IRCLR, ir->data->regs[MTK_IRCLR_REG]);
0261
0262     /* Clear interrupt status */
0263     mtk_w32_mask(ir, 0x1, MTK_IRINT_CLR,
0264              ir->data->regs[MTK_IRINT_CLR_REG]);
0265
0266     return IRQ_HANDLED;
0267 }
0268
0269 static const struct mtk_ir_data mt7623_data = {
0270     .regs = mt7623_regs,
0271     .fields = mt7623_fields,
0272     .ok_count = 3,
0273     .hw_period = 0xff,
0274     .div    = 4,
0275 };
0276
0277 static const struct mtk_ir_data mt7622_data = {
0278     .regs = mt7622_regs,
0279     .fields = mt7622_fields,
0280     .ok_count = 3,
0281     .hw_period = 0xffff,
0282     .div    = 32,
0283 };
0284
0285 static const struct of_device_id mtk_ir_match[] = {
0286     { .compatible = "mediatek,mt7623-cir", .data = &mt7623_data},
0287     { .compatible = "mediatek,mt7622-cir", .data = &mt7622_data},
0288     {},
0289 };
0290 MODULE_DEVICE_TABLE(of, mtk_ir_match);
0291
0292 static int mtk_ir_probe(struct platform_device *pdev)
0293 {
0294     struct device *dev = &pdev->dev;
0295     struct device_node *dn = dev->of_node;
0296     struct mtk_ir *ir;
0297     u32 val;
0298     int ret = 0;
0299     const char *map_name;
0300
0301     ir = devm_kzalloc(dev, sizeof(struct mtk_ir), GFP_KERNEL);
0302     if (!ir)
0303         return -ENOMEM;
0304
0305     ir->dev = dev;
0306     ir->data = of_device_get_match_data(dev);
0307
0308     ir->clk = devm_clk_get(dev, "clk");
0309     if (IS_ERR(ir->clk)) {
0310         dev_err(dev, "failed to get a ir clock.\n");
0311         return PTR_ERR(ir->clk);
0312     }
0313
0314     ir->bus = devm_clk_get(dev, "bus");
0315     if (IS_ERR(ir->bus)) {
0316         /*
0317          * For compatibility with older device trees try unnamed
0318          * ir->bus uses the same clock as ir->clock.
0319          */
0320         ir->bus = ir->clk;
0321     }
0322
0323     ir->base = devm_platform_ioremap_resource(pdev, 0);
0324     if (IS_ERR(ir->base))
0325         return PTR_ERR(ir->base);
0326
0327     ir->rc = devm_rc_allocate_device(dev, RC_DRIVER_IR_RAW);
0328     if (!ir->rc) {
0329         dev_err(dev, "failed to allocate device\n");
0330         return -ENOMEM;
0331     }
0332
0333     ir->rc->priv = ir;
0334     ir->rc->device_name = MTK_IR_DEV;
0335     ir->rc->input_phys = MTK_IR_DEV "/input0";
0336     ir->rc->input_id.bustype = BUS_HOST;
0337     ir->rc->input_id.vendor = 0x0001;
0338     ir->rc->input_id.product = 0x0001;
0339     ir->rc->input_id.version = 0x0001;
0340     map_name = of_get_property(dn, "linux,rc-map-name", NULL);
0341     ir->rc->map_name = map_name ?: RC_MAP_EMPTY;
0342     ir->rc->dev.parent = dev;
0343     ir->rc->driver_name = MTK_IR_DEV;
0344     ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
0345     ir->rc->rx_resolution = MTK_IR_SAMPLE;
0346     ir->rc->timeout = MTK_MAX_SAMPLES * (MTK_IR_SAMPLE + 1);
0347
0348     ret = devm_rc_register_device(dev, ir->rc);
0349     if (ret) {
0350         dev_err(dev, "failed to register rc device\n");
0351         return ret;
0352     }
0353
0354     platform_set_drvdata(pdev, ir);
0355
0356     ir->irq = platform_get_irq(pdev, 0);
0357     if (ir->irq < 0)
0358         return -ENODEV;
0359
0360     if (clk_prepare_enable(ir->clk)) {
0361         dev_err(dev, "try to enable ir_clk failed\n");
0362         return -EINVAL;
0363     }
0364
0365     if (clk_prepare_enable(ir->bus)) {
0366         dev_err(dev, "try to enable ir_clk failed\n");
0367         ret = -EINVAL;
0368         goto exit_clkdisable_clk;
0369     }
0370
0371     /*
0372      * Enable interrupt after proper hardware
0373      * setup and IRQ handler registration
0374      */
0375     mtk_irq_disable(ir, MTK_IRINT_EN);
0376
0377     ret = devm_request_irq(dev, ir->irq, mtk_ir_irq, 0, MTK_IR_DEV, ir);
0378     if (ret) {
0379         dev_err(dev, "failed request irq\n");
0380         goto exit_clkdisable_bus;
0381     }
0382
0383     /*
0384      * Setup software sample period as the reference of software decoder
0385      */
0386     val = (mtk_chk_period(ir) << ir->data->fields[MTK_CHK_PERIOD].offset) &
0387            ir->data->fields[MTK_CHK_PERIOD].mask;
0388     mtk_w32_mask(ir, val, ir->data->fields[MTK_CHK_PERIOD].mask,
0389              ir->data->fields[MTK_CHK_PERIOD].reg);
0390
0391     /*
0392      * Setup hardware sampling period used to setup the proper timeout for
0393      * indicating end of IR receiving completion
0394      */
0395     val = (ir->data->hw_period << ir->data->fields[MTK_HW_PERIOD].offset) &
0396            ir->data->fields[MTK_HW_PERIOD].mask;
0397     mtk_w32_mask(ir, val, ir->data->fields[MTK_HW_PERIOD].mask,
0398              ir->data->fields[MTK_HW_PERIOD].reg);
0399
0400     /* Set de-glitch counter */
0401     mtk_w32_mask(ir, MTK_DG_CNT(1), MTK_DG_CNT_MASK, MTK_IRTHD);
0402
0403     /* Enable IR and PWM */
0404     val = mtk_r32(ir, MTK_CONFIG_HIGH_REG) & ~MTK_OK_COUNT_MASK;
0405     val |= MTK_OK_COUNT(ir->data->ok_count) |  MTK_PWM_EN | MTK_IR_EN;
0406     mtk_w32(ir, val, MTK_CONFIG_HIGH_REG);
0407
0408     mtk_irq_enable(ir, MTK_IRINT_EN);
0409
0410     dev_info(dev, "Initialized MT7623 IR driver, sample period = %dus\n",
0411          MTK_IR_SAMPLE);
0412
0413     return 0;
0414
0415 exit_clkdisable_bus:
0416     clk_disable_unprepare(ir->bus);
0417 exit_clkdisable_clk:
0418     clk_disable_unprepare(ir->clk);
0419
0420     return ret;
0421 }
0422
0423 static int mtk_ir_remove(struct platform_device *pdev)
0424 {
0425     struct mtk_ir *ir = platform_get_drvdata(pdev);
0426
0427     /*
0428      * Avoid contention between remove handler and
0429      * IRQ handler so that disabling IR interrupt and
0430      * waiting for pending IRQ handler to complete
0431      */
0432     mtk_irq_disable(ir, MTK_IRINT_EN);
0433     synchronize_irq(ir->irq);
0434
0435     clk_disable_unprepare(ir->bus);
0436     clk_disable_unprepare(ir->clk);
0437
0438     return 0;
0439 }
0440
0441 static struct platform_driver mtk_ir_driver = {
0442     .probe          = mtk_ir_probe,
0443     .remove         = mtk_ir_remove,
0444     .driver = {
0445         .name = MTK_IR_DEV,
0446         .of_match_table = mtk_ir_match,
0447     },
0448 };
0449
0450 module_platform_driver(mtk_ir_driver);
0451
0452 MODULE_DESCRIPTION("Mediatek IR Receiver Controller Driver");
0453 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
0454 MODULE_LICENSE("GPL");