OSCL-LXR |
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0001 /* SPDX-License-Identifier: GPL-2.0-or-later */ 0002 /* 0003 * Driver for ITE Tech Inc. IT8712F/IT8512F CIR 0004 * 0005 * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com> 0006 */ 0007 0008 /* platform driver name to register */ 0009 #define ITE_DRIVER_NAME "ite-cir" 0010 0011 /* FIFO sizes */ 0012 #define ITE_TX_FIFO_LEN 32 0013 #define ITE_RX_FIFO_LEN 32 0014 0015 /* interrupt types */ 0016 #define ITE_IRQ_TX_FIFO 1 0017 #define ITE_IRQ_RX_FIFO 2 0018 #define ITE_IRQ_RX_FIFO_OVERRUN 4 0019 0020 /* forward declaration */ 0021 struct ite_dev; 0022 0023 /* struct for storing the parameters of different recognized devices */ 0024 struct ite_dev_params { 0025 /* model of the device */ 0026 const char *model; 0027 0028 /* size of the I/O region */ 0029 int io_region_size; 0030 0031 /* IR pnp I/O resource number */ 0032 int io_rsrc_no; 0033 0034 /* hw-specific operation function pointers; most of these must be 0035 * called while holding the spin lock, except for the TX FIFO length 0036 * one */ 0037 /* get pending interrupt causes */ 0038 int (*get_irq_causes) (struct ite_dev *dev); 0039 0040 /* enable rx */ 0041 void (*enable_rx) (struct ite_dev *dev); 0042 0043 /* make rx enter the idle state; keep listening for a pulse, but stop 0044 * streaming space bytes */ 0045 void (*idle_rx) (struct ite_dev *dev); 0046 0047 /* disable rx completely */ 0048 void (*disable_rx) (struct ite_dev *dev); 0049 0050 /* read bytes from RX FIFO; return read count */ 0051 int (*get_rx_bytes) (struct ite_dev *dev, u8 *buf, int buf_size); 0052 0053 /* enable tx FIFO space available interrupt */ 0054 void (*enable_tx_interrupt) (struct ite_dev *dev); 0055 0056 /* disable tx FIFO space available interrupt */ 0057 void (*disable_tx_interrupt) (struct ite_dev *dev); 0058 0059 /* get number of full TX FIFO slots */ 0060 int (*get_tx_used_slots) (struct ite_dev *dev); 0061 0062 /* put a byte to the TX FIFO */ 0063 void (*put_tx_byte) (struct ite_dev *dev, u8 value); 0064 0065 /* disable hardware completely */ 0066 void (*disable) (struct ite_dev *dev); 0067 0068 /* initialize the hardware */ 0069 void (*init_hardware) (struct ite_dev *dev); 0070 0071 /* set the carrier parameters */ 0072 void (*set_carrier_params) (struct ite_dev *dev, bool high_freq, 0073 bool use_demodulator, u8 carrier_freq_bits, 0074 u8 allowance_bits, u8 pulse_width_bits); 0075 }; 0076 0077 /* ITE CIR device structure */ 0078 struct ite_dev { 0079 struct pnp_dev *pdev; 0080 struct rc_dev *rdev; 0081 0082 /* sync data */ 0083 spinlock_t lock; 0084 bool transmitting; 0085 0086 /* transmit support */ 0087 wait_queue_head_t tx_queue, tx_ended; 0088 0089 /* rx low carrier frequency, in Hz, 0 means no demodulation */ 0090 unsigned int rx_low_carrier_freq; 0091 0092 /* tx high carrier frequency, in Hz, 0 means no demodulation */ 0093 unsigned int rx_high_carrier_freq; 0094 0095 /* tx carrier frequency, in Hz */ 0096 unsigned int tx_carrier_freq; 0097 0098 /* duty cycle, 0-100 */ 0099 int tx_duty_cycle; 0100 0101 /* hardware I/O settings */ 0102 unsigned long cir_addr; 0103 int cir_irq; 0104 0105 /* overridable copy of model parameters */ 0106 const struct ite_dev_params *params; 0107 }; 0108 0109 /* common values for all kinds of hardware */ 0110 0111 /* baud rate divisor default */ 0112 #define ITE_BAUDRATE_DIVISOR 1 0113 0114 /* low-speed carrier frequency limits (Hz) */ 0115 #define ITE_LCF_MIN_CARRIER_FREQ 27000 0116 #define ITE_LCF_MAX_CARRIER_FREQ 58000 0117 0118 /* high-speed carrier frequency limits (Hz) */ 0119 #define ITE_HCF_MIN_CARRIER_FREQ 400000 0120 #define ITE_HCF_MAX_CARRIER_FREQ 500000 0121 0122 /* default carrier freq for when demodulator is off (Hz) */ 0123 #define ITE_DEFAULT_CARRIER_FREQ 38000 0124 0125 /* convert bits to us */ 0126 #define ITE_BITS_TO_US(bits, sample_period) \ 0127 ((u32)((bits) * ITE_BAUDRATE_DIVISOR * (sample_period) / 1000)) 0128 0129 /* 0130 * n in RDCR produces a tolerance of +/- n * 6.25% around the center 0131 * carrier frequency... 0132 * 0133 * From two limit frequencies, L (low) and H (high), we can get both the 0134 * center frequency F = (L + H) / 2 and the variation from the center 0135 * frequency A = (H - L) / (H + L). We can use this in order to honor the 0136 * s_rx_carrier_range() call in ir-core. We'll suppose that any request 0137 * setting L=0 means we must shut down the demodulator. 0138 */ 0139 #define ITE_RXDCR_PER_10000_STEP 625 0140 0141 /* high speed carrier freq values */ 0142 #define ITE_CFQ_400 0x03 0143 #define ITE_CFQ_450 0x08 0144 #define ITE_CFQ_480 0x0b 0145 #define ITE_CFQ_500 0x0d 0146 0147 /* values for pulse widths */ 0148 #define ITE_TXMPW_A 0x02 0149 #define ITE_TXMPW_B 0x03 0150 #define ITE_TXMPW_C 0x04 0151 #define ITE_TXMPW_D 0x05 0152 #define ITE_TXMPW_E 0x06 0153 0154 /* values for demodulator carrier range allowance */ 0155 #define ITE_RXDCR_DEFAULT 0x01 /* default carrier range */ 0156 #define ITE_RXDCR_MAX 0x07 /* default carrier range */ 0157 0158 /* DR TX bits */ 0159 #define ITE_TX_PULSE 0x00 0160 #define ITE_TX_SPACE 0x80 0161 #define ITE_TX_MAX_RLE 0x80 0162 #define ITE_TX_RLE_MASK 0x7f 0163 0164 /* 0165 * IT8712F 0166 * 0167 * hardware data obtained from: 0168 * 0169 * IT8712F 0170 * Environment Control - Low Pin Count Input / Output 0171 * (EC - LPC I/O) 0172 * Preliminary Specification V0. 81 0173 */ 0174 0175 /* register offsets */ 0176 #define IT87_DR 0x00 /* data register */ 0177 #define IT87_IER 0x01 /* interrupt enable register */ 0178 #define IT87_RCR 0x02 /* receiver control register */ 0179 #define IT87_TCR1 0x03 /* transmitter control register 1 */ 0180 #define IT87_TCR2 0x04 /* transmitter control register 2 */ 0181 #define IT87_TSR 0x05 /* transmitter status register */ 0182 #define IT87_RSR 0x06 /* receiver status register */ 0183 #define IT87_BDLR 0x05 /* baud rate divisor low byte register */ 0184 #define IT87_BDHR 0x06 /* baud rate divisor high byte register */ 0185 #define IT87_IIR 0x07 /* interrupt identification register */ 0186 0187 #define IT87_IOREG_LENGTH 0x08 /* length of register file */ 0188 0189 /* IER bits */ 0190 #define IT87_TLDLIE 0x01 /* transmitter low data interrupt enable */ 0191 #define IT87_RDAIE 0x02 /* receiver data available interrupt enable */ 0192 #define IT87_RFOIE 0x04 /* receiver FIFO overrun interrupt enable */ 0193 #define IT87_IEC 0x08 /* interrupt enable control */ 0194 #define IT87_BR 0x10 /* baud rate register enable */ 0195 #define IT87_RESET 0x20 /* reset */ 0196 0197 /* RCR bits */ 0198 #define IT87_RXDCR 0x07 /* receiver demodulation carrier range mask */ 0199 #define IT87_RXACT 0x08 /* receiver active */ 0200 #define IT87_RXEND 0x10 /* receiver demodulation enable */ 0201 #define IT87_RXEN 0x20 /* receiver enable */ 0202 #define IT87_HCFS 0x40 /* high-speed carrier frequency select */ 0203 #define IT87_RDWOS 0x80 /* receiver data without sync */ 0204 0205 /* TCR1 bits */ 0206 #define IT87_TXMPM 0x03 /* transmitter modulation pulse mode mask */ 0207 #define IT87_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 0208 #define IT87_TXENDF 0x04 /* transmitter deferral */ 0209 #define IT87_TXRLE 0x08 /* transmitter run length enable */ 0210 #define IT87_FIFOTL 0x30 /* FIFO level threshold mask */ 0211 #define IT87_FIFOTL_DEFAULT 0x20 /* FIFO level threshold default 0212 * 0x00 -> 1, 0x10 -> 7, 0x20 -> 17, 0213 * 0x30 -> 25 */ 0214 #define IT87_ILE 0x40 /* internal loopback enable */ 0215 #define IT87_FIFOCLR 0x80 /* FIFO clear bit */ 0216 0217 /* TCR2 bits */ 0218 #define IT87_TXMPW 0x07 /* transmitter modulation pulse width mask */ 0219 #define IT87_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 0220 #define IT87_CFQ 0xf8 /* carrier frequency mask */ 0221 #define IT87_CFQ_SHIFT 3 /* carrier frequency bit shift */ 0222 0223 /* TSR bits */ 0224 #define IT87_TXFBC 0x3f /* transmitter FIFO byte count mask */ 0225 0226 /* RSR bits */ 0227 #define IT87_RXFBC 0x3f /* receiver FIFO byte count mask */ 0228 #define IT87_RXFTO 0x80 /* receiver FIFO time-out */ 0229 0230 /* IIR bits */ 0231 #define IT87_IP 0x01 /* interrupt pending */ 0232 #define IT87_II 0x06 /* interrupt identification mask */ 0233 #define IT87_II_NOINT 0x00 /* no interrupt */ 0234 #define IT87_II_TXLDL 0x02 /* transmitter low data level */ 0235 #define IT87_II_RXDS 0x04 /* receiver data stored */ 0236 #define IT87_II_RXFO 0x06 /* receiver FIFO overrun */ 0237 0238 /* 0239 * IT8512E/F 0240 * 0241 * Hardware data obtained from: 0242 * 0243 * IT8512E/F 0244 * Embedded Controller 0245 * Preliminary Specification V0.4.1 0246 * 0247 * Note that the CIR registers are not directly available to the host, because 0248 * they only are accessible to the integrated microcontroller. Thus, in order 0249 * use it, some kind of bridging is required. As the bridging may depend on 0250 * the controller firmware in use, we are going to use the PNP ID in order to 0251 * determine the strategy and ports available. See after these generic 0252 * IT8512E/F register definitions for register definitions for those 0253 * strategies. 0254 */ 0255 0256 /* register offsets */ 0257 #define IT85_C0DR 0x00 /* data register */ 0258 #define IT85_C0MSTCR 0x01 /* master control register */ 0259 #define IT85_C0IER 0x02 /* interrupt enable register */ 0260 #define IT85_C0IIR 0x03 /* interrupt identification register */ 0261 #define IT85_C0CFR 0x04 /* carrier frequency register */ 0262 #define IT85_C0RCR 0x05 /* receiver control register */ 0263 #define IT85_C0TCR 0x06 /* transmitter control register */ 0264 #define IT85_C0SCK 0x07 /* slow clock control register */ 0265 #define IT85_C0BDLR 0x08 /* baud rate divisor low byte register */ 0266 #define IT85_C0BDHR 0x09 /* baud rate divisor high byte register */ 0267 #define IT85_C0TFSR 0x0a /* transmitter FIFO status register */ 0268 #define IT85_C0RFSR 0x0b /* receiver FIFO status register */ 0269 #define IT85_C0WCL 0x0d /* wakeup code length register */ 0270 #define IT85_C0WCR 0x0e /* wakeup code read/write register */ 0271 #define IT85_C0WPS 0x0f /* wakeup power control/status register */ 0272 0273 #define IT85_IOREG_LENGTH 0x10 /* length of register file */ 0274 0275 /* C0MSTCR bits */ 0276 #define IT85_RESET 0x01 /* reset */ 0277 #define IT85_FIFOCLR 0x02 /* FIFO clear bit */ 0278 #define IT85_FIFOTL 0x0c /* FIFO level threshold mask */ 0279 #define IT85_FIFOTL_DEFAULT 0x08 /* FIFO level threshold default 0280 * 0x00 -> 1, 0x04 -> 7, 0x08 -> 17, 0281 * 0x0c -> 25 */ 0282 #define IT85_ILE 0x10 /* internal loopback enable */ 0283 #define IT85_ILSEL 0x20 /* internal loopback select */ 0284 0285 /* C0IER bits */ 0286 #define IT85_TLDLIE 0x01 /* TX low data level interrupt enable */ 0287 #define IT85_RDAIE 0x02 /* RX data available interrupt enable */ 0288 #define IT85_RFOIE 0x04 /* RX FIFO overrun interrupt enable */ 0289 #define IT85_IEC 0x80 /* interrupt enable function control */ 0290 0291 /* C0IIR bits */ 0292 #define IT85_TLDLI 0x01 /* transmitter low data level interrupt */ 0293 #define IT85_RDAI 0x02 /* receiver data available interrupt */ 0294 #define IT85_RFOI 0x04 /* receiver FIFO overrun interrupt */ 0295 #define IT85_NIP 0x80 /* no interrupt pending */ 0296 0297 /* C0CFR bits */ 0298 #define IT85_CFQ 0x1f /* carrier frequency mask */ 0299 #define IT85_HCFS 0x20 /* high speed carrier frequency select */ 0300 0301 /* C0RCR bits */ 0302 #define IT85_RXDCR 0x07 /* receiver demodulation carrier range mask */ 0303 #define IT85_RXACT 0x08 /* receiver active */ 0304 #define IT85_RXEND 0x10 /* receiver demodulation enable */ 0305 #define IT85_RDWOS 0x20 /* receiver data without sync */ 0306 #define IT85_RXEN 0x80 /* receiver enable */ 0307 0308 /* C0TCR bits */ 0309 #define IT85_TXMPW 0x07 /* transmitter modulation pulse width mask */ 0310 #define IT85_TXMPW_DEFAULT 0x04 /* default modulation pulse width */ 0311 #define IT85_TXMPM 0x18 /* transmitter modulation pulse mode mask */ 0312 #define IT85_TXMPM_DEFAULT 0x00 /* modulation pulse mode default */ 0313 #define IT85_TXENDF 0x20 /* transmitter deferral */ 0314 #define IT85_TXRLE 0x40 /* transmitter run length enable */ 0315 0316 /* C0SCK bits */ 0317 #define IT85_SCKS 0x01 /* slow clock select */ 0318 #define IT85_TXDCKG 0x02 /* TXD clock gating */ 0319 #define IT85_DLL1P8E 0x04 /* DLL 1.8432M enable */ 0320 #define IT85_DLLTE 0x08 /* DLL test enable */ 0321 #define IT85_BRCM 0x70 /* baud rate count mode */ 0322 #define IT85_DLLOCK 0x80 /* DLL lock */ 0323 0324 /* C0TFSR bits */ 0325 #define IT85_TXFBC 0x3f /* transmitter FIFO count mask */ 0326 0327 /* C0RFSR bits */ 0328 #define IT85_RXFBC 0x3f /* receiver FIFO count mask */ 0329 #define IT85_RXFTO 0x80 /* receiver FIFO time-out */ 0330 0331 /* C0WCL bits */ 0332 #define IT85_WCL 0x3f /* wakeup code length mask */ 0333 0334 /* C0WPS bits */ 0335 #define IT85_CIRPOSIE 0x01 /* power on/off status interrupt enable */ 0336 #define IT85_CIRPOIS 0x02 /* power on/off interrupt status */ 0337 #define IT85_CIRPOII 0x04 /* power on/off interrupt identification */ 0338 #define IT85_RCRST 0x10 /* wakeup code reading counter reset bit */ 0339 #define IT85_WCRST 0x20 /* wakeup code writing counter reset bit */ 0340 0341 /* 0342 * ITE8708 0343 * 0344 * Hardware data obtained from hacked driver for IT8512 in this forum post: 0345 * 0346 * http://ubuntuforums.org/showthread.php?t=1028640 0347 * 0348 * Although there's no official documentation for that driver, analysis would 0349 * suggest that it maps the 16 registers of IT8512 onto two 8-register banks, 0350 * selectable by a single bank-select bit that's mapped onto both banks. The 0351 * IT8512 registers are mapped in a different order, so that the first bank 0352 * maps the ones that are used more often, and two registers that share a 0353 * reserved high-order bit are placed at the same offset in both banks in 0354 * order to reuse the reserved bit as the bank select bit. 0355 */ 0356 0357 /* register offsets */ 0358 0359 /* mapped onto both banks */ 0360 #define IT8708_BANKSEL 0x07 /* bank select register */ 0361 #define IT8708_HRAE 0x80 /* high registers access enable */ 0362 0363 /* mapped onto the low bank */ 0364 #define IT8708_C0DR 0x00 /* data register */ 0365 #define IT8708_C0MSTCR 0x01 /* master control register */ 0366 #define IT8708_C0IER 0x02 /* interrupt enable register */ 0367 #define IT8708_C0IIR 0x03 /* interrupt identification register */ 0368 #define IT8708_C0RFSR 0x04 /* receiver FIFO status register */ 0369 #define IT8708_C0RCR 0x05 /* receiver control register */ 0370 #define IT8708_C0TFSR 0x06 /* transmitter FIFO status register */ 0371 #define IT8708_C0TCR 0x07 /* transmitter control register */ 0372 0373 /* mapped onto the high bank */ 0374 #define IT8708_C0BDLR 0x01 /* baud rate divisor low byte register */ 0375 #define IT8708_C0BDHR 0x02 /* baud rate divisor high byte register */ 0376 #define IT8708_C0CFR 0x04 /* carrier frequency register */ 0377 0378 /* registers whose bank mapping we don't know, since they weren't being used 0379 * in the hacked driver... most probably they belong to the high bank too, 0380 * since they fit in the holes the other registers leave */ 0381 #define IT8708_C0SCK 0x03 /* slow clock control register */ 0382 #define IT8708_C0WCL 0x05 /* wakeup code length register */ 0383 #define IT8708_C0WCR 0x06 /* wakeup code read/write register */ 0384 #define IT8708_C0WPS 0x07 /* wakeup power control/status register */ 0385 0386 #define IT8708_IOREG_LENGTH 0x08 /* length of register file */ 0387 0388 /* two more registers that are defined in the hacked driver, but can't be 0389 * found in the data sheets; no idea what they are or how they are accessed, 0390 * since the hacked driver doesn't seem to use them */ 0391 #define IT8708_CSCRR 0x00 0392 #define IT8708_CGPINTR 0x01 0393 0394 /* CSCRR bits */ 0395 #define IT8708_CSCRR_SCRB 0x3f 0396 #define IT8708_CSCRR_PM 0x80 0397 0398 /* CGPINTR bits */ 0399 #define IT8708_CGPINT 0x01 0400 0401 /* 0402 * ITE8709 0403 * 0404 * Hardware interfacing data obtained from the original lirc_ite8709 driver. 0405 * Verbatim from its sources: 0406 * 0407 * The ITE8709 device seems to be the combination of IT8512 superIO chip and 0408 * a specific firmware running on the IT8512's embedded micro-controller. 0409 * In addition of the embedded micro-controller, the IT8512 chip contains a 0410 * CIR module and several other modules. A few modules are directly accessible 0411 * by the host CPU, but most of them are only accessible by the 0412 * micro-controller. The CIR module is only accessible by the 0413 * micro-controller. 0414 * 0415 * The battery-backed SRAM module is accessible by the host CPU and the 0416 * micro-controller. So one of the MC's firmware role is to act as a bridge 0417 * between the host CPU and the CIR module. The firmware implements a kind of 0418 * communication protocol using the SRAM module as a shared memory. The IT8512 0419 * specification is publicly available on ITE's web site, but the 0420 * communication protocol is not, so it was reverse-engineered. 0421 */ 0422 0423 /* register offsets */ 0424 #define IT8709_RAM_IDX 0x00 /* index into the SRAM module bytes */ 0425 #define IT8709_RAM_VAL 0x01 /* read/write data to the indexed byte */ 0426 0427 #define IT8709_IOREG_LENGTH 0x02 /* length of register file */ 0428 0429 /* register offsets inside the SRAM module */ 0430 #define IT8709_MODE 0x1a /* request/ack byte */ 0431 #define IT8709_REG_IDX 0x1b /* index of the CIR register to access */ 0432 #define IT8709_REG_VAL 0x1c /* value read/to be written */ 0433 #define IT8709_IIR 0x1e /* interrupt identification register */ 0434 #define IT8709_RFSR 0x1f /* receiver FIFO status register */ 0435 #define IT8709_FIFO 0x20 /* start of in RAM RX FIFO copy */ 0436 0437 /* MODE values */ 0438 #define IT8709_IDLE 0x00 0439 #define IT8709_WRITE 0x01 0440 #define IT8709_READ 0x02
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