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OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Driver for ITE Tech Inc. IT8712F/IT8512 CIR
0004  *
0005  * Copyright (C) 2010 Juan Jesús García de Soria <skandalfo@gmail.com>
0006  *
0007  * Inspired by the original lirc_it87 and lirc_ite8709 drivers, on top of the
0008  * skeleton provided by the nuvoton-cir driver.
0009  *
0010  * The lirc_it87 driver was originally written by Hans-Gunter Lutke Uphues
0011  * <hg_lu@web.de> in 2001, with enhancements by Christoph Bartelmus
0012  * <lirc@bartelmus.de>, Andrew Calkin <r_tay@hotmail.com> and James Edwards
0013  * <jimbo-lirc@edwardsclan.net>.
0014  *
0015  * The lirc_ite8709 driver was written by Grégory Lardière
0016  * <spmf2004-lirc@yahoo.fr> in 2008.
0017  */
0018 
0019 #include <linux/kernel.h>
0020 #include <linux/module.h>
0021 #include <linux/pnp.h>
0022 #include <linux/io.h>
0023 #include <linux/interrupt.h>
0024 #include <linux/sched.h>
0025 #include <linux/delay.h>
0026 #include <linux/slab.h>
0027 #include <linux/input.h>
0028 #include <linux/bitops.h>
0029 #include <media/rc-core.h>
0030 #include <linux/pci_ids.h>
0031 
0032 #include "ite-cir.h"
0033 
0034 /* module parameters */
0035 
0036 /* default sample period */
0037 static long sample_period = NSEC_PER_SEC / 115200;
0038 module_param(sample_period, long, S_IRUGO | S_IWUSR);
0039 MODULE_PARM_DESC(sample_period, "sample period");
0040 
0041 /* override detected model id */
0042 static int model_number = -1;
0043 module_param(model_number, int, S_IRUGO | S_IWUSR);
0044 MODULE_PARM_DESC(model_number, "Use this model number, don't autodetect");
0045 
0046 
0047 /* HW-independent code functions */
0048 
0049 /* check whether carrier frequency is high frequency */
0050 static inline bool ite_is_high_carrier_freq(unsigned int freq)
0051 {
0052     return freq >= ITE_HCF_MIN_CARRIER_FREQ;
0053 }
0054 
0055 /* get the bits required to program the carrier frequency in CFQ bits,
0056  * unshifted */
0057 static u8 ite_get_carrier_freq_bits(unsigned int freq)
0058 {
0059     if (ite_is_high_carrier_freq(freq)) {
0060         if (freq < 425000)
0061             return ITE_CFQ_400;
0062 
0063         else if (freq < 465000)
0064             return ITE_CFQ_450;
0065 
0066         else if (freq < 490000)
0067             return ITE_CFQ_480;
0068 
0069         else
0070             return ITE_CFQ_500;
0071     } else {
0072             /* trim to limits */
0073         if (freq < ITE_LCF_MIN_CARRIER_FREQ)
0074             freq = ITE_LCF_MIN_CARRIER_FREQ;
0075         if (freq > ITE_LCF_MAX_CARRIER_FREQ)
0076             freq = ITE_LCF_MAX_CARRIER_FREQ;
0077 
0078         /* convert to kHz and subtract the base freq */
0079         freq = DIV_ROUND_CLOSEST(freq - ITE_LCF_MIN_CARRIER_FREQ, 1000);
0080 
0081         return (u8) freq;
0082     }
0083 }
0084 
0085 /* get the bits required to program the pulse with in TXMPW */
0086 static u8 ite_get_pulse_width_bits(unsigned int freq, int duty_cycle)
0087 {
0088     unsigned long period_ns, on_ns;
0089 
0090     /* sanitize freq into range */
0091     if (freq < ITE_LCF_MIN_CARRIER_FREQ)
0092         freq = ITE_LCF_MIN_CARRIER_FREQ;
0093     if (freq > ITE_HCF_MAX_CARRIER_FREQ)
0094         freq = ITE_HCF_MAX_CARRIER_FREQ;
0095 
0096     period_ns = 1000000000UL / freq;
0097     on_ns = period_ns * duty_cycle / 100;
0098 
0099     if (ite_is_high_carrier_freq(freq)) {
0100         if (on_ns < 750)
0101             return ITE_TXMPW_A;
0102 
0103         else if (on_ns < 850)
0104             return ITE_TXMPW_B;
0105 
0106         else if (on_ns < 950)
0107             return ITE_TXMPW_C;
0108 
0109         else if (on_ns < 1080)
0110             return ITE_TXMPW_D;
0111 
0112         else
0113             return ITE_TXMPW_E;
0114     } else {
0115         if (on_ns < 6500)
0116             return ITE_TXMPW_A;
0117 
0118         else if (on_ns < 7850)
0119             return ITE_TXMPW_B;
0120 
0121         else if (on_ns < 9650)
0122             return ITE_TXMPW_C;
0123 
0124         else if (on_ns < 11950)
0125             return ITE_TXMPW_D;
0126 
0127         else
0128             return ITE_TXMPW_E;
0129     }
0130 }
0131 
0132 /* decode raw bytes as received by the hardware, and push them to the ir-core
0133  * layer */
0134 static void ite_decode_bytes(struct ite_dev *dev, const u8 * data, int
0135                  length)
0136 {
0137     unsigned long *ldata;
0138     unsigned int next_one, next_zero, size;
0139     struct ir_raw_event ev = {};
0140 
0141     if (length == 0)
0142         return;
0143 
0144     ldata = (unsigned long *)data;
0145     size = length << 3;
0146     next_one = find_next_bit_le(ldata, size, 0);
0147     if (next_one > 0) {
0148         ev.pulse = true;
0149         ev.duration = ITE_BITS_TO_US(next_one, sample_period);
0150         ir_raw_event_store_with_filter(dev->rdev, &ev);
0151     }
0152 
0153     while (next_one < size) {
0154         next_zero = find_next_zero_bit_le(ldata, size, next_one + 1);
0155         ev.pulse = false;
0156         ev.duration = ITE_BITS_TO_US(next_zero - next_one, sample_period);
0157         ir_raw_event_store_with_filter(dev->rdev, &ev);
0158 
0159         if (next_zero < size) {
0160             next_one = find_next_bit_le(ldata, size, next_zero + 1);
0161             ev.pulse = true;
0162             ev.duration = ITE_BITS_TO_US(next_one - next_zero,
0163                              sample_period);
0164             ir_raw_event_store_with_filter(dev->rdev, &ev);
0165         } else
0166             next_one = size;
0167     }
0168 
0169     ir_raw_event_handle(dev->rdev);
0170 
0171     dev_dbg(&dev->rdev->dev, "decoded %d bytes\n", length);
0172 }
0173 
0174 /* set all the rx/tx carrier parameters; this must be called with the device
0175  * spinlock held */
0176 static void ite_set_carrier_params(struct ite_dev *dev)
0177 {
0178     unsigned int freq, low_freq, high_freq;
0179     int allowance;
0180     bool use_demodulator;
0181     bool for_tx = dev->transmitting;
0182 
0183     if (for_tx) {
0184         /* we don't need no stinking calculations */
0185         freq = dev->tx_carrier_freq;
0186         allowance = ITE_RXDCR_DEFAULT;
0187         use_demodulator = false;
0188     } else {
0189         low_freq = dev->rx_low_carrier_freq;
0190         high_freq = dev->rx_high_carrier_freq;
0191 
0192         if (low_freq == 0) {
0193             /* don't demodulate */
0194             freq = ITE_DEFAULT_CARRIER_FREQ;
0195             allowance = ITE_RXDCR_DEFAULT;
0196             use_demodulator = false;
0197         } else {
0198             /* calculate the middle freq */
0199             freq = (low_freq + high_freq) / 2;
0200 
0201             /* calculate the allowance */
0202             allowance =
0203                 DIV_ROUND_CLOSEST(10000 * (high_freq - low_freq),
0204                           ITE_RXDCR_PER_10000_STEP
0205                           * (high_freq + low_freq));
0206 
0207             if (allowance < 1)
0208                 allowance = 1;
0209 
0210             if (allowance > ITE_RXDCR_MAX)
0211                 allowance = ITE_RXDCR_MAX;
0212 
0213             use_demodulator = true;
0214         }
0215     }
0216 
0217     /* set the carrier parameters in a device-dependent way */
0218     dev->params->set_carrier_params(dev, ite_is_high_carrier_freq(freq),
0219          use_demodulator, ite_get_carrier_freq_bits(freq), allowance,
0220          ite_get_pulse_width_bits(freq, dev->tx_duty_cycle));
0221 }
0222 
0223 /* interrupt service routine for incoming and outgoing CIR data */
0224 static irqreturn_t ite_cir_isr(int irq, void *data)
0225 {
0226     struct ite_dev *dev = data;
0227     irqreturn_t ret = IRQ_RETVAL(IRQ_NONE);
0228     u8 rx_buf[ITE_RX_FIFO_LEN];
0229     int rx_bytes;
0230     int iflags;
0231 
0232     /* grab the spinlock */
0233     spin_lock(&dev->lock);
0234 
0235     /* read the interrupt flags */
0236     iflags = dev->params->get_irq_causes(dev);
0237 
0238     /* Check for RX overflow */
0239     if (iflags & ITE_IRQ_RX_FIFO_OVERRUN) {
0240         dev_warn(&dev->rdev->dev, "receive overflow\n");
0241         ir_raw_event_overflow(dev->rdev);
0242     }
0243 
0244     /* check for the receive interrupt */
0245     if (iflags & (ITE_IRQ_RX_FIFO | ITE_IRQ_RX_FIFO_OVERRUN)) {
0246         /* read the FIFO bytes */
0247         rx_bytes = dev->params->get_rx_bytes(dev, rx_buf,
0248                             ITE_RX_FIFO_LEN);
0249 
0250         dev_dbg(&dev->rdev->dev, "interrupt %d RX bytes\n", rx_bytes);
0251 
0252         if (rx_bytes > 0) {
0253             /* drop the spinlock, since the ir-core layer
0254              * may call us back again through
0255              * ite_s_idle() */
0256             spin_unlock(&dev->lock);
0257 
0258             /* decode the data we've just received */
0259             ite_decode_bytes(dev, rx_buf, rx_bytes);
0260 
0261             /* reacquire the spinlock */
0262             spin_lock(&dev->lock);
0263 
0264             /* mark the interrupt as serviced */
0265             ret = IRQ_RETVAL(IRQ_HANDLED);
0266         }
0267     } else if (iflags & ITE_IRQ_TX_FIFO) {
0268         /* FIFO space available interrupt */
0269         dev_dbg(&dev->rdev->dev, "interrupt TX FIFO\n");
0270 
0271         /* wake any sleeping transmitter */
0272         wake_up_interruptible(&dev->tx_queue);
0273 
0274         /* mark the interrupt as serviced */
0275         ret = IRQ_RETVAL(IRQ_HANDLED);
0276     }
0277 
0278     /* drop the spinlock */
0279     spin_unlock(&dev->lock);
0280 
0281     return ret;
0282 }
0283 
0284 /* set the rx carrier freq range, guess it's in Hz... */
0285 static int ite_set_rx_carrier_range(struct rc_dev *rcdev, u32 carrier_low, u32
0286                     carrier_high)
0287 {
0288     unsigned long flags;
0289     struct ite_dev *dev = rcdev->priv;
0290 
0291     spin_lock_irqsave(&dev->lock, flags);
0292     dev->rx_low_carrier_freq = carrier_low;
0293     dev->rx_high_carrier_freq = carrier_high;
0294     ite_set_carrier_params(dev);
0295     spin_unlock_irqrestore(&dev->lock, flags);
0296 
0297     return 0;
0298 }
0299 
0300 /* set the tx carrier freq, guess it's in Hz... */
0301 static int ite_set_tx_carrier(struct rc_dev *rcdev, u32 carrier)
0302 {
0303     unsigned long flags;
0304     struct ite_dev *dev = rcdev->priv;
0305 
0306     spin_lock_irqsave(&dev->lock, flags);
0307     dev->tx_carrier_freq = carrier;
0308     ite_set_carrier_params(dev);
0309     spin_unlock_irqrestore(&dev->lock, flags);
0310 
0311     return 0;
0312 }
0313 
0314 /* set the tx duty cycle by controlling the pulse width */
0315 static int ite_set_tx_duty_cycle(struct rc_dev *rcdev, u32 duty_cycle)
0316 {
0317     unsigned long flags;
0318     struct ite_dev *dev = rcdev->priv;
0319 
0320     spin_lock_irqsave(&dev->lock, flags);
0321     dev->tx_duty_cycle = duty_cycle;
0322     ite_set_carrier_params(dev);
0323     spin_unlock_irqrestore(&dev->lock, flags);
0324 
0325     return 0;
0326 }
0327 
0328 /* transmit out IR pulses; what you get here is a batch of alternating
0329  * pulse/space/pulse/space lengths that we should write out completely through
0330  * the FIFO, blocking on a full FIFO */
0331 static int ite_tx_ir(struct rc_dev *rcdev, unsigned *txbuf, unsigned n)
0332 {
0333     unsigned long flags;
0334     struct ite_dev *dev = rcdev->priv;
0335     bool is_pulse = false;
0336     int remaining_us, fifo_avail, fifo_remaining, last_idx = 0;
0337     int max_rle_us, next_rle_us;
0338     int ret = n;
0339     u8 last_sent[ITE_TX_FIFO_LEN];
0340     u8 val;
0341 
0342     /* clear the array just in case */
0343     memset(last_sent, 0, sizeof(last_sent));
0344 
0345     spin_lock_irqsave(&dev->lock, flags);
0346 
0347     /* let everybody know we're now transmitting */
0348     dev->transmitting = true;
0349 
0350     /* and set the carrier values for transmission */
0351     ite_set_carrier_params(dev);
0352 
0353     /* calculate how much time we can send in one byte */
0354     max_rle_us =
0355         (ITE_BAUDRATE_DIVISOR * sample_period *
0356          ITE_TX_MAX_RLE) / 1000;
0357 
0358     /* disable the receiver */
0359     dev->params->disable_rx(dev);
0360 
0361     /* this is where we'll begin filling in the FIFO, until it's full.
0362      * then we'll just activate the interrupt, wait for it to wake us up
0363      * again, disable it, continue filling the FIFO... until everything
0364      * has been pushed out */
0365     fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);
0366 
0367     while (n > 0) {
0368         /* transmit the next sample */
0369         is_pulse = !is_pulse;
0370         remaining_us = *(txbuf++);
0371         n--;
0372 
0373         dev_dbg(&dev->rdev->dev, "%s: %d\n",
0374             is_pulse ? "pulse" : "space", remaining_us);
0375 
0376         /* repeat while the pulse is non-zero length */
0377         while (remaining_us > 0) {
0378             if (remaining_us > max_rle_us)
0379                 next_rle_us = max_rle_us;
0380 
0381             else
0382                 next_rle_us = remaining_us;
0383 
0384             remaining_us -= next_rle_us;
0385 
0386             /* check what's the length we have to pump out */
0387             val = (ITE_TX_MAX_RLE * next_rle_us) / max_rle_us;
0388 
0389             /* put it into the sent buffer */
0390             last_sent[last_idx++] = val;
0391             last_idx &= (ITE_TX_FIFO_LEN);
0392 
0393             /* encode it for 7 bits */
0394             val = (val - 1) & ITE_TX_RLE_MASK;
0395 
0396             /* take into account pulse/space prefix */
0397             if (is_pulse)
0398                 val |= ITE_TX_PULSE;
0399 
0400             else
0401                 val |= ITE_TX_SPACE;
0402 
0403             /*
0404              * if we get to 0 available, read again, just in case
0405              * some other slot got freed
0406              */
0407             if (fifo_avail <= 0)
0408                 fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev);
0409 
0410             /* if it's still full */
0411             if (fifo_avail <= 0) {
0412                 /* enable the tx interrupt */
0413                 dev->params->enable_tx_interrupt(dev);
0414 
0415                 /* drop the spinlock */
0416                 spin_unlock_irqrestore(&dev->lock, flags);
0417 
0418                 /* wait for the FIFO to empty enough */
0419                 wait_event_interruptible(dev->tx_queue,
0420                     (fifo_avail = ITE_TX_FIFO_LEN - dev->params->get_tx_used_slots(dev)) >= 8);
0421 
0422                 /* get the spinlock again */
0423                 spin_lock_irqsave(&dev->lock, flags);
0424 
0425                 /* disable the tx interrupt again. */
0426                 dev->params->disable_tx_interrupt(dev);
0427             }
0428 
0429             /* now send the byte through the FIFO */
0430             dev->params->put_tx_byte(dev, val);
0431             fifo_avail--;
0432         }
0433     }
0434 
0435     /* wait and don't return until the whole FIFO has been sent out;
0436      * otherwise we could configure the RX carrier params instead of the
0437      * TX ones while the transmission is still being performed! */
0438     fifo_remaining = dev->params->get_tx_used_slots(dev);
0439     remaining_us = 0;
0440     while (fifo_remaining > 0) {
0441         fifo_remaining--;
0442         last_idx--;
0443         last_idx &= (ITE_TX_FIFO_LEN - 1);
0444         remaining_us += last_sent[last_idx];
0445     }
0446     remaining_us = (remaining_us * max_rle_us) / (ITE_TX_MAX_RLE);
0447 
0448     /* drop the spinlock while we sleep */
0449     spin_unlock_irqrestore(&dev->lock, flags);
0450 
0451     /* sleep remaining_us microseconds */
0452     mdelay(DIV_ROUND_UP(remaining_us, 1000));
0453 
0454     /* reacquire the spinlock */
0455     spin_lock_irqsave(&dev->lock, flags);
0456 
0457     /* now we're not transmitting anymore */
0458     dev->transmitting = false;
0459 
0460     /* and set the carrier values for reception */
0461     ite_set_carrier_params(dev);
0462 
0463     /* re-enable the receiver */
0464     dev->params->enable_rx(dev);
0465 
0466     /* notify transmission end */
0467     wake_up_interruptible(&dev->tx_ended);
0468 
0469     spin_unlock_irqrestore(&dev->lock, flags);
0470 
0471     return ret;
0472 }
0473 
0474 /* idle the receiver if needed */
0475 static void ite_s_idle(struct rc_dev *rcdev, bool enable)
0476 {
0477     unsigned long flags;
0478     struct ite_dev *dev = rcdev->priv;
0479 
0480     if (enable) {
0481         spin_lock_irqsave(&dev->lock, flags);
0482         dev->params->idle_rx(dev);
0483         spin_unlock_irqrestore(&dev->lock, flags);
0484     }
0485 }
0486 
0487 
0488 /* IT8712F HW-specific functions */
0489 
0490 /* retrieve a bitmask of the current causes for a pending interrupt; this may
0491  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
0492  * */
0493 static int it87_get_irq_causes(struct ite_dev *dev)
0494 {
0495     u8 iflags;
0496     int ret = 0;
0497 
0498     /* read the interrupt flags */
0499     iflags = inb(dev->cir_addr + IT87_IIR) & IT87_II;
0500 
0501     switch (iflags) {
0502     case IT87_II_RXDS:
0503         ret = ITE_IRQ_RX_FIFO;
0504         break;
0505     case IT87_II_RXFO:
0506         ret = ITE_IRQ_RX_FIFO_OVERRUN;
0507         break;
0508     case IT87_II_TXLDL:
0509         ret = ITE_IRQ_TX_FIFO;
0510         break;
0511     }
0512 
0513     return ret;
0514 }
0515 
0516 /* set the carrier parameters; to be called with the spinlock held */
0517 static void it87_set_carrier_params(struct ite_dev *dev, bool high_freq,
0518                     bool use_demodulator,
0519                     u8 carrier_freq_bits, u8 allowance_bits,
0520                     u8 pulse_width_bits)
0521 {
0522     u8 val;
0523 
0524     /* program the RCR register */
0525     val = inb(dev->cir_addr + IT87_RCR)
0526         & ~(IT87_HCFS | IT87_RXEND | IT87_RXDCR);
0527 
0528     if (high_freq)
0529         val |= IT87_HCFS;
0530 
0531     if (use_demodulator)
0532         val |= IT87_RXEND;
0533 
0534     val |= allowance_bits;
0535 
0536     outb(val, dev->cir_addr + IT87_RCR);
0537 
0538     /* program the TCR2 register */
0539     outb((carrier_freq_bits << IT87_CFQ_SHIFT) | pulse_width_bits,
0540         dev->cir_addr + IT87_TCR2);
0541 }
0542 
0543 /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
0544  * held */
0545 static int it87_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
0546 {
0547     int fifo, read = 0;
0548 
0549     /* read how many bytes are still in the FIFO */
0550     fifo = inb(dev->cir_addr + IT87_RSR) & IT87_RXFBC;
0551 
0552     while (fifo > 0 && buf_size > 0) {
0553         *(buf++) = inb(dev->cir_addr + IT87_DR);
0554         fifo--;
0555         read++;
0556         buf_size--;
0557     }
0558 
0559     return read;
0560 }
0561 
0562 /* return how many bytes are still in the FIFO; this will be called
0563  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
0564  * empty; let's expect this won't be a problem */
0565 static int it87_get_tx_used_slots(struct ite_dev *dev)
0566 {
0567     return inb(dev->cir_addr + IT87_TSR) & IT87_TXFBC;
0568 }
0569 
0570 /* put a byte to the TX fifo; this should be called with the spinlock held */
0571 static void it87_put_tx_byte(struct ite_dev *dev, u8 value)
0572 {
0573     outb(value, dev->cir_addr + IT87_DR);
0574 }
0575 
0576 /* idle the receiver so that we won't receive samples until another
0577   pulse is detected; this must be called with the device spinlock held */
0578 static void it87_idle_rx(struct ite_dev *dev)
0579 {
0580     /* disable streaming by clearing RXACT writing it as 1 */
0581     outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXACT,
0582         dev->cir_addr + IT87_RCR);
0583 
0584     /* clear the FIFO */
0585     outb(inb(dev->cir_addr + IT87_TCR1) | IT87_FIFOCLR,
0586         dev->cir_addr + IT87_TCR1);
0587 }
0588 
0589 /* disable the receiver; this must be called with the device spinlock held */
0590 static void it87_disable_rx(struct ite_dev *dev)
0591 {
0592     /* disable the receiver interrupts */
0593     outb(inb(dev->cir_addr + IT87_IER) & ~(IT87_RDAIE | IT87_RFOIE),
0594         dev->cir_addr + IT87_IER);
0595 
0596     /* disable the receiver */
0597     outb(inb(dev->cir_addr + IT87_RCR) & ~IT87_RXEN,
0598         dev->cir_addr + IT87_RCR);
0599 
0600     /* clear the FIFO and RXACT (actually RXACT should have been cleared
0601     * in the previous outb() call) */
0602     it87_idle_rx(dev);
0603 }
0604 
0605 /* enable the receiver; this must be called with the device spinlock held */
0606 static void it87_enable_rx(struct ite_dev *dev)
0607 {
0608     /* enable the receiver by setting RXEN */
0609     outb(inb(dev->cir_addr + IT87_RCR) | IT87_RXEN,
0610         dev->cir_addr + IT87_RCR);
0611 
0612     /* just prepare it to idle for the next reception */
0613     it87_idle_rx(dev);
0614 
0615     /* enable the receiver interrupts and master enable flag */
0616     outb(inb(dev->cir_addr + IT87_IER) | IT87_RDAIE | IT87_RFOIE | IT87_IEC,
0617         dev->cir_addr + IT87_IER);
0618 }
0619 
0620 /* disable the transmitter interrupt; this must be called with the device
0621  * spinlock held */
0622 static void it87_disable_tx_interrupt(struct ite_dev *dev)
0623 {
0624     /* disable the transmitter interrupts */
0625     outb(inb(dev->cir_addr + IT87_IER) & ~IT87_TLDLIE,
0626         dev->cir_addr + IT87_IER);
0627 }
0628 
0629 /* enable the transmitter interrupt; this must be called with the device
0630  * spinlock held */
0631 static void it87_enable_tx_interrupt(struct ite_dev *dev)
0632 {
0633     /* enable the transmitter interrupts and master enable flag */
0634     outb(inb(dev->cir_addr + IT87_IER) | IT87_TLDLIE | IT87_IEC,
0635         dev->cir_addr + IT87_IER);
0636 }
0637 
0638 /* disable the device; this must be called with the device spinlock held */
0639 static void it87_disable(struct ite_dev *dev)
0640 {
0641     /* clear out all interrupt enable flags */
0642     outb(inb(dev->cir_addr + IT87_IER) &
0643         ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE),
0644         dev->cir_addr + IT87_IER);
0645 
0646     /* disable the receiver */
0647     it87_disable_rx(dev);
0648 
0649     /* erase the FIFO */
0650     outb(IT87_FIFOCLR | inb(dev->cir_addr + IT87_TCR1),
0651         dev->cir_addr + IT87_TCR1);
0652 }
0653 
0654 /* initialize the hardware */
0655 static void it87_init_hardware(struct ite_dev *dev)
0656 {
0657     /* enable just the baud rate divisor register,
0658     disabling all the interrupts at the same time */
0659     outb((inb(dev->cir_addr + IT87_IER) &
0660         ~(IT87_IEC | IT87_RFOIE | IT87_RDAIE | IT87_TLDLIE)) | IT87_BR,
0661         dev->cir_addr + IT87_IER);
0662 
0663     /* write out the baud rate divisor */
0664     outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT87_BDLR);
0665     outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff, dev->cir_addr + IT87_BDHR);
0666 
0667     /* disable the baud rate divisor register again */
0668     outb(inb(dev->cir_addr + IT87_IER) & ~IT87_BR,
0669         dev->cir_addr + IT87_IER);
0670 
0671     /* program the RCR register defaults */
0672     outb(ITE_RXDCR_DEFAULT, dev->cir_addr + IT87_RCR);
0673 
0674     /* program the TCR1 register */
0675     outb(IT87_TXMPM_DEFAULT | IT87_TXENDF | IT87_TXRLE
0676         | IT87_FIFOTL_DEFAULT | IT87_FIFOCLR,
0677         dev->cir_addr + IT87_TCR1);
0678 
0679     /* program the carrier parameters */
0680     ite_set_carrier_params(dev);
0681 }
0682 
0683 /* IT8512F on ITE8708 HW-specific functions */
0684 
0685 /* retrieve a bitmask of the current causes for a pending interrupt; this may
0686  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
0687  * */
0688 static int it8708_get_irq_causes(struct ite_dev *dev)
0689 {
0690     u8 iflags;
0691     int ret = 0;
0692 
0693     /* read the interrupt flags */
0694     iflags = inb(dev->cir_addr + IT8708_C0IIR);
0695 
0696     if (iflags & IT85_TLDLI)
0697         ret |= ITE_IRQ_TX_FIFO;
0698     if (iflags & IT85_RDAI)
0699         ret |= ITE_IRQ_RX_FIFO;
0700     if (iflags & IT85_RFOI)
0701         ret |= ITE_IRQ_RX_FIFO_OVERRUN;
0702 
0703     return ret;
0704 }
0705 
0706 /* set the carrier parameters; to be called with the spinlock held */
0707 static void it8708_set_carrier_params(struct ite_dev *dev, bool high_freq,
0708                       bool use_demodulator,
0709                       u8 carrier_freq_bits, u8 allowance_bits,
0710                       u8 pulse_width_bits)
0711 {
0712     u8 val;
0713 
0714     /* program the C0CFR register, with HRAE=1 */
0715     outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
0716         dev->cir_addr + IT8708_BANKSEL);
0717 
0718     val = (inb(dev->cir_addr + IT8708_C0CFR)
0719         & ~(IT85_HCFS | IT85_CFQ)) | carrier_freq_bits;
0720 
0721     if (high_freq)
0722         val |= IT85_HCFS;
0723 
0724     outb(val, dev->cir_addr + IT8708_C0CFR);
0725 
0726     outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
0727            dev->cir_addr + IT8708_BANKSEL);
0728 
0729     /* program the C0RCR register */
0730     val = inb(dev->cir_addr + IT8708_C0RCR)
0731         & ~(IT85_RXEND | IT85_RXDCR);
0732 
0733     if (use_demodulator)
0734         val |= IT85_RXEND;
0735 
0736     val |= allowance_bits;
0737 
0738     outb(val, dev->cir_addr + IT8708_C0RCR);
0739 
0740     /* program the C0TCR register */
0741     val = inb(dev->cir_addr + IT8708_C0TCR) & ~IT85_TXMPW;
0742     val |= pulse_width_bits;
0743     outb(val, dev->cir_addr + IT8708_C0TCR);
0744 }
0745 
0746 /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
0747  * held */
0748 static int it8708_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
0749 {
0750     int fifo, read = 0;
0751 
0752     /* read how many bytes are still in the FIFO */
0753     fifo = inb(dev->cir_addr + IT8708_C0RFSR) & IT85_RXFBC;
0754 
0755     while (fifo > 0 && buf_size > 0) {
0756         *(buf++) = inb(dev->cir_addr + IT8708_C0DR);
0757         fifo--;
0758         read++;
0759         buf_size--;
0760     }
0761 
0762     return read;
0763 }
0764 
0765 /* return how many bytes are still in the FIFO; this will be called
0766  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
0767  * empty; let's expect this won't be a problem */
0768 static int it8708_get_tx_used_slots(struct ite_dev *dev)
0769 {
0770     return inb(dev->cir_addr + IT8708_C0TFSR) & IT85_TXFBC;
0771 }
0772 
0773 /* put a byte to the TX fifo; this should be called with the spinlock held */
0774 static void it8708_put_tx_byte(struct ite_dev *dev, u8 value)
0775 {
0776     outb(value, dev->cir_addr + IT8708_C0DR);
0777 }
0778 
0779 /* idle the receiver so that we won't receive samples until another
0780   pulse is detected; this must be called with the device spinlock held */
0781 static void it8708_idle_rx(struct ite_dev *dev)
0782 {
0783     /* disable streaming by clearing RXACT writing it as 1 */
0784     outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXACT,
0785         dev->cir_addr + IT8708_C0RCR);
0786 
0787     /* clear the FIFO */
0788     outb(inb(dev->cir_addr + IT8708_C0MSTCR) | IT85_FIFOCLR,
0789         dev->cir_addr + IT8708_C0MSTCR);
0790 }
0791 
0792 /* disable the receiver; this must be called with the device spinlock held */
0793 static void it8708_disable_rx(struct ite_dev *dev)
0794 {
0795     /* disable the receiver interrupts */
0796     outb(inb(dev->cir_addr + IT8708_C0IER) &
0797         ~(IT85_RDAIE | IT85_RFOIE),
0798         dev->cir_addr + IT8708_C0IER);
0799 
0800     /* disable the receiver */
0801     outb(inb(dev->cir_addr + IT8708_C0RCR) & ~IT85_RXEN,
0802         dev->cir_addr + IT8708_C0RCR);
0803 
0804     /* clear the FIFO and RXACT (actually RXACT should have been cleared
0805      * in the previous outb() call) */
0806     it8708_idle_rx(dev);
0807 }
0808 
0809 /* enable the receiver; this must be called with the device spinlock held */
0810 static void it8708_enable_rx(struct ite_dev *dev)
0811 {
0812     /* enable the receiver by setting RXEN */
0813     outb(inb(dev->cir_addr + IT8708_C0RCR) | IT85_RXEN,
0814         dev->cir_addr + IT8708_C0RCR);
0815 
0816     /* just prepare it to idle for the next reception */
0817     it8708_idle_rx(dev);
0818 
0819     /* enable the receiver interrupts and master enable flag */
0820     outb(inb(dev->cir_addr + IT8708_C0IER)
0821         |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
0822         dev->cir_addr + IT8708_C0IER);
0823 }
0824 
0825 /* disable the transmitter interrupt; this must be called with the device
0826  * spinlock held */
0827 static void it8708_disable_tx_interrupt(struct ite_dev *dev)
0828 {
0829     /* disable the transmitter interrupts */
0830     outb(inb(dev->cir_addr + IT8708_C0IER) & ~IT85_TLDLIE,
0831         dev->cir_addr + IT8708_C0IER);
0832 }
0833 
0834 /* enable the transmitter interrupt; this must be called with the device
0835  * spinlock held */
0836 static void it8708_enable_tx_interrupt(struct ite_dev *dev)
0837 {
0838     /* enable the transmitter interrupts and master enable flag */
0839     outb(inb(dev->cir_addr + IT8708_C0IER)
0840         |IT85_TLDLIE | IT85_IEC,
0841         dev->cir_addr + IT8708_C0IER);
0842 }
0843 
0844 /* disable the device; this must be called with the device spinlock held */
0845 static void it8708_disable(struct ite_dev *dev)
0846 {
0847     /* clear out all interrupt enable flags */
0848     outb(inb(dev->cir_addr + IT8708_C0IER) &
0849         ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
0850         dev->cir_addr + IT8708_C0IER);
0851 
0852     /* disable the receiver */
0853     it8708_disable_rx(dev);
0854 
0855     /* erase the FIFO */
0856     outb(IT85_FIFOCLR | inb(dev->cir_addr + IT8708_C0MSTCR),
0857         dev->cir_addr + IT8708_C0MSTCR);
0858 }
0859 
0860 /* initialize the hardware */
0861 static void it8708_init_hardware(struct ite_dev *dev)
0862 {
0863     /* disable all the interrupts */
0864     outb(inb(dev->cir_addr + IT8708_C0IER) &
0865         ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
0866         dev->cir_addr + IT8708_C0IER);
0867 
0868     /* program the baud rate divisor */
0869     outb(inb(dev->cir_addr + IT8708_BANKSEL) | IT8708_HRAE,
0870         dev->cir_addr + IT8708_BANKSEL);
0871 
0872     outb(ITE_BAUDRATE_DIVISOR & 0xff, dev->cir_addr + IT8708_C0BDLR);
0873     outb((ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
0874            dev->cir_addr + IT8708_C0BDHR);
0875 
0876     outb(inb(dev->cir_addr + IT8708_BANKSEL) & ~IT8708_HRAE,
0877            dev->cir_addr + IT8708_BANKSEL);
0878 
0879     /* program the C0MSTCR register defaults */
0880     outb((inb(dev->cir_addr + IT8708_C0MSTCR) &
0881             ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL |
0882               IT85_FIFOCLR | IT85_RESET)) |
0883                IT85_FIFOTL_DEFAULT,
0884                dev->cir_addr + IT8708_C0MSTCR);
0885 
0886     /* program the C0RCR register defaults */
0887     outb((inb(dev->cir_addr + IT8708_C0RCR) &
0888             ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND |
0889               IT85_RXACT | IT85_RXDCR)) |
0890                ITE_RXDCR_DEFAULT,
0891                dev->cir_addr + IT8708_C0RCR);
0892 
0893     /* program the C0TCR register defaults */
0894     outb((inb(dev->cir_addr + IT8708_C0TCR) &
0895             ~(IT85_TXMPM | IT85_TXMPW))
0896                |IT85_TXRLE | IT85_TXENDF |
0897                IT85_TXMPM_DEFAULT | IT85_TXMPW_DEFAULT,
0898                dev->cir_addr + IT8708_C0TCR);
0899 
0900     /* program the carrier parameters */
0901     ite_set_carrier_params(dev);
0902 }
0903 
0904 /* IT8512F on ITE8709 HW-specific functions */
0905 
0906 /* read a byte from the SRAM module */
0907 static inline u8 it8709_rm(struct ite_dev *dev, int index)
0908 {
0909     outb(index, dev->cir_addr + IT8709_RAM_IDX);
0910     return inb(dev->cir_addr + IT8709_RAM_VAL);
0911 }
0912 
0913 /* write a byte to the SRAM module */
0914 static inline void it8709_wm(struct ite_dev *dev, u8 val, int index)
0915 {
0916     outb(index, dev->cir_addr + IT8709_RAM_IDX);
0917     outb(val, dev->cir_addr + IT8709_RAM_VAL);
0918 }
0919 
0920 static void it8709_wait(struct ite_dev *dev)
0921 {
0922     int i = 0;
0923     /*
0924      * loop until device tells it's ready to continue
0925      * iterations count is usually ~750 but can sometimes achieve 13000
0926      */
0927     for (i = 0; i < 15000; i++) {
0928         udelay(2);
0929         if (it8709_rm(dev, IT8709_MODE) == IT8709_IDLE)
0930             break;
0931     }
0932 }
0933 
0934 /* read the value of a CIR register */
0935 static u8 it8709_rr(struct ite_dev *dev, int index)
0936 {
0937     /* just wait in case the previous access was a write */
0938     it8709_wait(dev);
0939     it8709_wm(dev, index, IT8709_REG_IDX);
0940     it8709_wm(dev, IT8709_READ, IT8709_MODE);
0941 
0942     /* wait for the read data to be available */
0943     it8709_wait(dev);
0944 
0945     /* return the read value */
0946     return it8709_rm(dev, IT8709_REG_VAL);
0947 }
0948 
0949 /* write the value of a CIR register */
0950 static void it8709_wr(struct ite_dev *dev, u8 val, int index)
0951 {
0952     /* we wait before writing, and not afterwards, since this allows us to
0953      * pipeline the host CPU with the microcontroller */
0954     it8709_wait(dev);
0955     it8709_wm(dev, val, IT8709_REG_VAL);
0956     it8709_wm(dev, index, IT8709_REG_IDX);
0957     it8709_wm(dev, IT8709_WRITE, IT8709_MODE);
0958 }
0959 
0960 /* retrieve a bitmask of the current causes for a pending interrupt; this may
0961  * be composed of ITE_IRQ_TX_FIFO, ITE_IRQ_RX_FIFO and ITE_IRQ_RX_FIFO_OVERRUN
0962  * */
0963 static int it8709_get_irq_causes(struct ite_dev *dev)
0964 {
0965     u8 iflags;
0966     int ret = 0;
0967 
0968     /* read the interrupt flags */
0969     iflags = it8709_rm(dev, IT8709_IIR);
0970 
0971     if (iflags & IT85_TLDLI)
0972         ret |= ITE_IRQ_TX_FIFO;
0973     if (iflags & IT85_RDAI)
0974         ret |= ITE_IRQ_RX_FIFO;
0975     if (iflags & IT85_RFOI)
0976         ret |= ITE_IRQ_RX_FIFO_OVERRUN;
0977 
0978     return ret;
0979 }
0980 
0981 /* set the carrier parameters; to be called with the spinlock held */
0982 static void it8709_set_carrier_params(struct ite_dev *dev, bool high_freq,
0983                       bool use_demodulator,
0984                       u8 carrier_freq_bits, u8 allowance_bits,
0985                       u8 pulse_width_bits)
0986 {
0987     u8 val;
0988 
0989     val = (it8709_rr(dev, IT85_C0CFR)
0990              &~(IT85_HCFS | IT85_CFQ)) |
0991         carrier_freq_bits;
0992 
0993     if (high_freq)
0994         val |= IT85_HCFS;
0995 
0996     it8709_wr(dev, val, IT85_C0CFR);
0997 
0998     /* program the C0RCR register */
0999     val = it8709_rr(dev, IT85_C0RCR)
1000         & ~(IT85_RXEND | IT85_RXDCR);
1001 
1002     if (use_demodulator)
1003         val |= IT85_RXEND;
1004 
1005     val |= allowance_bits;
1006 
1007     it8709_wr(dev, val, IT85_C0RCR);
1008 
1009     /* program the C0TCR register */
1010     val = it8709_rr(dev, IT85_C0TCR) & ~IT85_TXMPW;
1011     val |= pulse_width_bits;
1012     it8709_wr(dev, val, IT85_C0TCR);
1013 }
1014 
1015 /* read up to buf_size bytes from the RX FIFO; to be called with the spinlock
1016  * held */
1017 static int it8709_get_rx_bytes(struct ite_dev *dev, u8 * buf, int buf_size)
1018 {
1019     int fifo, read = 0;
1020 
1021     /* read how many bytes are still in the FIFO */
1022     fifo = it8709_rm(dev, IT8709_RFSR) & IT85_RXFBC;
1023 
1024     while (fifo > 0 && buf_size > 0) {
1025         *(buf++) = it8709_rm(dev, IT8709_FIFO + read);
1026         fifo--;
1027         read++;
1028         buf_size--;
1029     }
1030 
1031     /* 'clear' the FIFO by setting the writing index to 0; this is
1032      * completely bound to be racy, but we can't help it, since it's a
1033      * limitation of the protocol */
1034     it8709_wm(dev, 0, IT8709_RFSR);
1035 
1036     return read;
1037 }
1038 
1039 /* return how many bytes are still in the FIFO; this will be called
1040  * with the device spinlock NOT HELD while waiting for the TX FIFO to get
1041  * empty; let's expect this won't be a problem */
1042 static int it8709_get_tx_used_slots(struct ite_dev *dev)
1043 {
1044     return it8709_rr(dev, IT85_C0TFSR) & IT85_TXFBC;
1045 }
1046 
1047 /* put a byte to the TX fifo; this should be called with the spinlock held */
1048 static void it8709_put_tx_byte(struct ite_dev *dev, u8 value)
1049 {
1050     it8709_wr(dev, value, IT85_C0DR);
1051 }
1052 
1053 /* idle the receiver so that we won't receive samples until another
1054   pulse is detected; this must be called with the device spinlock held */
1055 static void it8709_idle_rx(struct ite_dev *dev)
1056 {
1057     /* disable streaming by clearing RXACT writing it as 1 */
1058     it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXACT,
1059                 IT85_C0RCR);
1060 
1061     /* clear the FIFO */
1062     it8709_wr(dev, it8709_rr(dev, IT85_C0MSTCR) | IT85_FIFOCLR,
1063                 IT85_C0MSTCR);
1064 }
1065 
1066 /* disable the receiver; this must be called with the device spinlock held */
1067 static void it8709_disable_rx(struct ite_dev *dev)
1068 {
1069     /* disable the receiver interrupts */
1070     it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1071                 ~(IT85_RDAIE | IT85_RFOIE),
1072                 IT85_C0IER);
1073 
1074     /* disable the receiver */
1075     it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) & ~IT85_RXEN,
1076                 IT85_C0RCR);
1077 
1078     /* clear the FIFO and RXACT (actually RXACT should have been cleared
1079      * in the previous it8709_wr(dev, ) call) */
1080     it8709_idle_rx(dev);
1081 }
1082 
1083 /* enable the receiver; this must be called with the device spinlock held */
1084 static void it8709_enable_rx(struct ite_dev *dev)
1085 {
1086     /* enable the receiver by setting RXEN */
1087     it8709_wr(dev, it8709_rr(dev, IT85_C0RCR) | IT85_RXEN,
1088                 IT85_C0RCR);
1089 
1090     /* just prepare it to idle for the next reception */
1091     it8709_idle_rx(dev);
1092 
1093     /* enable the receiver interrupts and master enable flag */
1094     it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1095                 |IT85_RDAIE | IT85_RFOIE | IT85_IEC,
1096                 IT85_C0IER);
1097 }
1098 
1099 /* disable the transmitter interrupt; this must be called with the device
1100  * spinlock held */
1101 static void it8709_disable_tx_interrupt(struct ite_dev *dev)
1102 {
1103     /* disable the transmitter interrupts */
1104     it8709_wr(dev, it8709_rr(dev, IT85_C0IER) & ~IT85_TLDLIE,
1105                 IT85_C0IER);
1106 }
1107 
1108 /* enable the transmitter interrupt; this must be called with the device
1109  * spinlock held */
1110 static void it8709_enable_tx_interrupt(struct ite_dev *dev)
1111 {
1112     /* enable the transmitter interrupts and master enable flag */
1113     it8709_wr(dev, it8709_rr(dev, IT85_C0IER)
1114                 |IT85_TLDLIE | IT85_IEC,
1115                 IT85_C0IER);
1116 }
1117 
1118 /* disable the device; this must be called with the device spinlock held */
1119 static void it8709_disable(struct ite_dev *dev)
1120 {
1121     /* clear out all interrupt enable flags */
1122     it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1123             ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
1124           IT85_C0IER);
1125 
1126     /* disable the receiver */
1127     it8709_disable_rx(dev);
1128 
1129     /* erase the FIFO */
1130     it8709_wr(dev, IT85_FIFOCLR | it8709_rr(dev, IT85_C0MSTCR),
1131                 IT85_C0MSTCR);
1132 }
1133 
1134 /* initialize the hardware */
1135 static void it8709_init_hardware(struct ite_dev *dev)
1136 {
1137     /* disable all the interrupts */
1138     it8709_wr(dev, it8709_rr(dev, IT85_C0IER) &
1139             ~(IT85_IEC | IT85_RFOIE | IT85_RDAIE | IT85_TLDLIE),
1140           IT85_C0IER);
1141 
1142     /* program the baud rate divisor */
1143     it8709_wr(dev, ITE_BAUDRATE_DIVISOR & 0xff, IT85_C0BDLR);
1144     it8709_wr(dev, (ITE_BAUDRATE_DIVISOR >> 8) & 0xff,
1145             IT85_C0BDHR);
1146 
1147     /* program the C0MSTCR register defaults */
1148     it8709_wr(dev, (it8709_rr(dev, IT85_C0MSTCR) &
1149             ~(IT85_ILSEL | IT85_ILE | IT85_FIFOTL
1150               | IT85_FIFOCLR | IT85_RESET)) | IT85_FIFOTL_DEFAULT,
1151           IT85_C0MSTCR);
1152 
1153     /* program the C0RCR register defaults */
1154     it8709_wr(dev, (it8709_rr(dev, IT85_C0RCR) &
1155             ~(IT85_RXEN | IT85_RDWOS | IT85_RXEND | IT85_RXACT
1156               | IT85_RXDCR)) | ITE_RXDCR_DEFAULT,
1157           IT85_C0RCR);
1158 
1159     /* program the C0TCR register defaults */
1160     it8709_wr(dev, (it8709_rr(dev, IT85_C0TCR) & ~(IT85_TXMPM | IT85_TXMPW))
1161             | IT85_TXRLE | IT85_TXENDF | IT85_TXMPM_DEFAULT
1162             | IT85_TXMPW_DEFAULT,
1163           IT85_C0TCR);
1164 
1165     /* program the carrier parameters */
1166     ite_set_carrier_params(dev);
1167 }
1168 
1169 
1170 /* generic hardware setup/teardown code */
1171 
1172 /* activate the device for use */
1173 static int ite_open(struct rc_dev *rcdev)
1174 {
1175     struct ite_dev *dev = rcdev->priv;
1176     unsigned long flags;
1177 
1178     spin_lock_irqsave(&dev->lock, flags);
1179 
1180     /* enable the receiver */
1181     dev->params->enable_rx(dev);
1182 
1183     spin_unlock_irqrestore(&dev->lock, flags);
1184 
1185     return 0;
1186 }
1187 
1188 /* deactivate the device for use */
1189 static void ite_close(struct rc_dev *rcdev)
1190 {
1191     struct ite_dev *dev = rcdev->priv;
1192     unsigned long flags;
1193 
1194     spin_lock_irqsave(&dev->lock, flags);
1195 
1196     /* wait for any transmission to end */
1197     spin_unlock_irqrestore(&dev->lock, flags);
1198     wait_event_interruptible(dev->tx_ended, !dev->transmitting);
1199     spin_lock_irqsave(&dev->lock, flags);
1200 
1201     dev->params->disable(dev);
1202 
1203     spin_unlock_irqrestore(&dev->lock, flags);
1204 }
1205 
1206 /* supported models and their parameters */
1207 static const struct ite_dev_params ite_dev_descs[] = {
1208     {   /* 0: ITE8704 */
1209            .model = "ITE8704 CIR transceiver",
1210            .io_region_size = IT87_IOREG_LENGTH,
1211            .io_rsrc_no = 0,
1212 
1213         /* operations */
1214            .get_irq_causes = it87_get_irq_causes,
1215            .enable_rx = it87_enable_rx,
1216            .idle_rx = it87_idle_rx,
1217            .disable_rx = it87_idle_rx,
1218            .get_rx_bytes = it87_get_rx_bytes,
1219            .enable_tx_interrupt = it87_enable_tx_interrupt,
1220            .disable_tx_interrupt = it87_disable_tx_interrupt,
1221            .get_tx_used_slots = it87_get_tx_used_slots,
1222            .put_tx_byte = it87_put_tx_byte,
1223            .disable = it87_disable,
1224            .init_hardware = it87_init_hardware,
1225            .set_carrier_params = it87_set_carrier_params,
1226            },
1227     {   /* 1: ITE8713 */
1228            .model = "ITE8713 CIR transceiver",
1229            .io_region_size = IT87_IOREG_LENGTH,
1230            .io_rsrc_no = 0,
1231 
1232         /* operations */
1233            .get_irq_causes = it87_get_irq_causes,
1234            .enable_rx = it87_enable_rx,
1235            .idle_rx = it87_idle_rx,
1236            .disable_rx = it87_idle_rx,
1237            .get_rx_bytes = it87_get_rx_bytes,
1238            .enable_tx_interrupt = it87_enable_tx_interrupt,
1239            .disable_tx_interrupt = it87_disable_tx_interrupt,
1240            .get_tx_used_slots = it87_get_tx_used_slots,
1241            .put_tx_byte = it87_put_tx_byte,
1242            .disable = it87_disable,
1243            .init_hardware = it87_init_hardware,
1244            .set_carrier_params = it87_set_carrier_params,
1245            },
1246     {   /* 2: ITE8708 */
1247            .model = "ITE8708 CIR transceiver",
1248            .io_region_size = IT8708_IOREG_LENGTH,
1249            .io_rsrc_no = 0,
1250 
1251         /* operations */
1252            .get_irq_causes = it8708_get_irq_causes,
1253            .enable_rx = it8708_enable_rx,
1254            .idle_rx = it8708_idle_rx,
1255            .disable_rx = it8708_idle_rx,
1256            .get_rx_bytes = it8708_get_rx_bytes,
1257            .enable_tx_interrupt = it8708_enable_tx_interrupt,
1258            .disable_tx_interrupt =
1259            it8708_disable_tx_interrupt,
1260            .get_tx_used_slots = it8708_get_tx_used_slots,
1261            .put_tx_byte = it8708_put_tx_byte,
1262            .disable = it8708_disable,
1263            .init_hardware = it8708_init_hardware,
1264            .set_carrier_params = it8708_set_carrier_params,
1265            },
1266     {   /* 3: ITE8709 */
1267            .model = "ITE8709 CIR transceiver",
1268            .io_region_size = IT8709_IOREG_LENGTH,
1269            .io_rsrc_no = 2,
1270 
1271         /* operations */
1272            .get_irq_causes = it8709_get_irq_causes,
1273            .enable_rx = it8709_enable_rx,
1274            .idle_rx = it8709_idle_rx,
1275            .disable_rx = it8709_idle_rx,
1276            .get_rx_bytes = it8709_get_rx_bytes,
1277            .enable_tx_interrupt = it8709_enable_tx_interrupt,
1278            .disable_tx_interrupt =
1279            it8709_disable_tx_interrupt,
1280            .get_tx_used_slots = it8709_get_tx_used_slots,
1281            .put_tx_byte = it8709_put_tx_byte,
1282            .disable = it8709_disable,
1283            .init_hardware = it8709_init_hardware,
1284            .set_carrier_params = it8709_set_carrier_params,
1285            },
1286 };
1287 
1288 static const struct pnp_device_id ite_ids[] = {
1289     {"ITE8704", 0},     /* Default model */
1290     {"ITE8713", 1},     /* CIR found in EEEBox 1501U */
1291     {"ITE8708", 2},     /* Bridged IT8512 */
1292     {"ITE8709", 3},     /* SRAM-Bridged IT8512 */
1293     {"", 0},
1294 };
1295 
1296 /* allocate memory, probe hardware, and initialize everything */
1297 static int ite_probe(struct pnp_dev *pdev, const struct pnp_device_id
1298              *dev_id)
1299 {
1300     const struct ite_dev_params *dev_desc = NULL;
1301     struct ite_dev *itdev = NULL;
1302     struct rc_dev *rdev = NULL;
1303     int ret = -ENOMEM;
1304     int model_no;
1305     int io_rsrc_no;
1306 
1307     itdev = kzalloc(sizeof(struct ite_dev), GFP_KERNEL);
1308     if (!itdev)
1309         return ret;
1310 
1311     /* input device for IR remote (and tx) */
1312     rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
1313     if (!rdev)
1314         goto exit_free_dev_rdev;
1315     itdev->rdev = rdev;
1316 
1317     ret = -ENODEV;
1318 
1319     /* get the model number */
1320     model_no = (int)dev_id->driver_data;
1321     dev_dbg(&pdev->dev, "Auto-detected model: %s\n",
1322         ite_dev_descs[model_no].model);
1323 
1324     if (model_number >= 0 && model_number < ARRAY_SIZE(ite_dev_descs)) {
1325         model_no = model_number;
1326         dev_info(&pdev->dev, "model has been forced to: %s",
1327              ite_dev_descs[model_no].model);
1328     }
1329 
1330     /* get the description for the device */
1331     dev_desc = &ite_dev_descs[model_no];
1332     io_rsrc_no = dev_desc->io_rsrc_no;
1333 
1334     /* validate pnp resources */
1335     if (!pnp_port_valid(pdev, io_rsrc_no) ||
1336         pnp_port_len(pdev, io_rsrc_no) < dev_desc->io_region_size) {
1337         dev_err(&pdev->dev, "IR PNP Port not valid!\n");
1338         goto exit_free_dev_rdev;
1339     }
1340 
1341     if (!pnp_irq_valid(pdev, 0)) {
1342         dev_err(&pdev->dev, "PNP IRQ not valid!\n");
1343         goto exit_free_dev_rdev;
1344     }
1345 
1346     /* store resource values */
1347     itdev->cir_addr = pnp_port_start(pdev, io_rsrc_no);
1348     itdev->cir_irq = pnp_irq(pdev, 0);
1349 
1350     /* initialize spinlocks */
1351     spin_lock_init(&itdev->lock);
1352 
1353     /* set driver data into the pnp device */
1354     pnp_set_drvdata(pdev, itdev);
1355     itdev->pdev = pdev;
1356 
1357     /* initialize waitqueues for transmission */
1358     init_waitqueue_head(&itdev->tx_queue);
1359     init_waitqueue_head(&itdev->tx_ended);
1360 
1361     /* Set model-specific parameters */
1362     itdev->params = dev_desc;
1363 
1364     /* set up hardware initial state */
1365     itdev->tx_duty_cycle = 33;
1366     itdev->tx_carrier_freq = ITE_DEFAULT_CARRIER_FREQ;
1367     itdev->params->init_hardware(itdev);
1368 
1369     /* set up ir-core props */
1370     rdev->priv = itdev;
1371     rdev->dev.parent = &pdev->dev;
1372     rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
1373     rdev->open = ite_open;
1374     rdev->close = ite_close;
1375     rdev->s_idle = ite_s_idle;
1376     rdev->s_rx_carrier_range = ite_set_rx_carrier_range;
1377     /* FIFO threshold is 17 bytes, so 17 * 8 samples minimum */
1378     rdev->min_timeout = 17 * 8 * ITE_BAUDRATE_DIVISOR *
1379                 sample_period / 1000;
1380     rdev->timeout = IR_DEFAULT_TIMEOUT;
1381     rdev->max_timeout = 10 * IR_DEFAULT_TIMEOUT;
1382     rdev->rx_resolution = ITE_BAUDRATE_DIVISOR * sample_period / 1000;
1383     rdev->tx_resolution = ITE_BAUDRATE_DIVISOR * sample_period / 1000;
1384 
1385     /* set up transmitter related values */
1386     rdev->tx_ir = ite_tx_ir;
1387     rdev->s_tx_carrier = ite_set_tx_carrier;
1388     rdev->s_tx_duty_cycle = ite_set_tx_duty_cycle;
1389 
1390     rdev->device_name = dev_desc->model;
1391     rdev->input_id.bustype = BUS_HOST;
1392     rdev->input_id.vendor = PCI_VENDOR_ID_ITE;
1393     rdev->input_id.product = 0;
1394     rdev->input_id.version = 0;
1395     rdev->driver_name = ITE_DRIVER_NAME;
1396     rdev->map_name = RC_MAP_RC6_MCE;
1397 
1398     ret = rc_register_device(rdev);
1399     if (ret)
1400         goto exit_free_dev_rdev;
1401 
1402     ret = -EBUSY;
1403     /* now claim resources */
1404     if (!request_region(itdev->cir_addr,
1405                 dev_desc->io_region_size, ITE_DRIVER_NAME))
1406         goto exit_unregister_device;
1407 
1408     if (request_irq(itdev->cir_irq, ite_cir_isr, IRQF_SHARED,
1409             ITE_DRIVER_NAME, (void *)itdev))
1410         goto exit_release_cir_addr;
1411 
1412     return 0;
1413 
1414 exit_release_cir_addr:
1415     release_region(itdev->cir_addr, itdev->params->io_region_size);
1416 exit_unregister_device:
1417     rc_unregister_device(rdev);
1418     rdev = NULL;
1419 exit_free_dev_rdev:
1420     rc_free_device(rdev);
1421     kfree(itdev);
1422 
1423     return ret;
1424 }
1425 
1426 static void ite_remove(struct pnp_dev *pdev)
1427 {
1428     struct ite_dev *dev = pnp_get_drvdata(pdev);
1429     unsigned long flags;
1430 
1431     spin_lock_irqsave(&dev->lock, flags);
1432 
1433     /* disable hardware */
1434     dev->params->disable(dev);
1435 
1436     spin_unlock_irqrestore(&dev->lock, flags);
1437 
1438     /* free resources */
1439     free_irq(dev->cir_irq, dev);
1440     release_region(dev->cir_addr, dev->params->io_region_size);
1441 
1442     rc_unregister_device(dev->rdev);
1443 
1444     kfree(dev);
1445 }
1446 
1447 static int ite_suspend(struct pnp_dev *pdev, pm_message_t state)
1448 {
1449     struct ite_dev *dev = pnp_get_drvdata(pdev);
1450     unsigned long flags;
1451 
1452     /* wait for any transmission to end */
1453     wait_event_interruptible(dev->tx_ended, !dev->transmitting);
1454 
1455     spin_lock_irqsave(&dev->lock, flags);
1456 
1457     /* disable all interrupts */
1458     dev->params->disable(dev);
1459 
1460     spin_unlock_irqrestore(&dev->lock, flags);
1461 
1462     return 0;
1463 }
1464 
1465 static int ite_resume(struct pnp_dev *pdev)
1466 {
1467     struct ite_dev *dev = pnp_get_drvdata(pdev);
1468     unsigned long flags;
1469 
1470     spin_lock_irqsave(&dev->lock, flags);
1471 
1472     /* reinitialize hardware config registers */
1473     dev->params->init_hardware(dev);
1474     /* enable the receiver */
1475     dev->params->enable_rx(dev);
1476 
1477     spin_unlock_irqrestore(&dev->lock, flags);
1478 
1479     return 0;
1480 }
1481 
1482 static void ite_shutdown(struct pnp_dev *pdev)
1483 {
1484     struct ite_dev *dev = pnp_get_drvdata(pdev);
1485     unsigned long flags;
1486 
1487     spin_lock_irqsave(&dev->lock, flags);
1488 
1489     /* disable all interrupts */
1490     dev->params->disable(dev);
1491 
1492     spin_unlock_irqrestore(&dev->lock, flags);
1493 }
1494 
1495 static struct pnp_driver ite_driver = {
1496     .name       = ITE_DRIVER_NAME,
1497     .id_table   = ite_ids,
1498     .probe      = ite_probe,
1499     .remove     = ite_remove,
1500     .suspend    = ite_suspend,
1501     .resume     = ite_resume,
1502     .shutdown   = ite_shutdown,
1503 };
1504 
1505 MODULE_DEVICE_TABLE(pnp, ite_ids);
1506 MODULE_DESCRIPTION("ITE Tech Inc. IT8712F/ITE8512F CIR driver");
1507 
1508 MODULE_AUTHOR("Juan J. Garcia de Soria <skandalfo@gmail.com>");
1509 MODULE_LICENSE("GPL");
1510 
1511 module_pnp_driver(ite_driver);
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