media/rc/ir-hix5hd2.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (c) 2014 Linaro Ltd.
0004  * Copyright (c) 2014 HiSilicon Limited.
0005  */
0006
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/interrupt.h>
0010 #include <linux/mfd/syscon.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/regmap.h>
0014 #include <media/rc-core.h>
0015
0016 #define IR_ENABLE       0x00
0017 #define IR_CONFIG       0x04
0018 #define CNT_LEADS       0x08
0019 #define CNT_LEADE       0x0c
0020 #define CNT_SLEADE      0x10
0021 #define CNT0_B          0x14
0022 #define CNT1_B          0x18
0023 #define IR_BUSY         0x1c
0024 #define IR_DATAH        0x20
0025 #define IR_DATAL        0x24
0026 #define IR_INTM         0x28
0027 #define IR_INTS         0x2c
0028 #define IR_INTC         0x30
0029 #define IR_START        0x34
0030
0031 /* interrupt mask */
0032 #define INTMS_SYMBRCV       (BIT(24) | BIT(8))
0033 #define INTMS_TIMEOUT       (BIT(25) | BIT(9))
0034 #define INTMS_OVERFLOW      (BIT(26) | BIT(10))
0035 #define INT_CLR_OVERFLOW    BIT(18)
0036 #define INT_CLR_TIMEOUT     BIT(17)
0037 #define INT_CLR_RCV     BIT(16)
0038 #define INT_CLR_RCVTIMEOUT  (BIT(16) | BIT(17))
0039
0040 #define IR_CLK_ENABLE       BIT(4)
0041 #define IR_CLK_RESET        BIT(5)
0042
0043 /* IR_ENABLE register bits */
0044 #define IR_ENABLE_EN        BIT(0)
0045 #define IR_ENABLE_EN_EXTRA  BIT(8)
0046
0047 #define IR_CFG_WIDTH_MASK   0xffff
0048 #define IR_CFG_WIDTH_SHIFT  16
0049 #define IR_CFG_FORMAT_MASK  0x3
0050 #define IR_CFG_FORMAT_SHIFT 14
0051 #define IR_CFG_INT_LEVEL_MASK   0x3f
0052 #define IR_CFG_INT_LEVEL_SHIFT  8
0053 /* only support raw mode */
0054 #define IR_CFG_MODE_RAW     BIT(7)
0055 #define IR_CFG_FREQ_MASK    0x7f
0056 #define IR_CFG_FREQ_SHIFT   0
0057 #define IR_CFG_INT_THRESHOLD    1
0058 /* symbol start from low to high, symbol stream end at high*/
0059 #define IR_CFG_SYMBOL_FMT   0
0060 #define IR_CFG_SYMBOL_MAXWIDTH  0x3e80
0061
0062 #define IR_HIX5HD2_NAME     "hix5hd2-ir"
0063
0064 /* Need to set extra bit for enabling IR */
0065 #define HIX5HD2_FLAG_EXTRA_ENABLE   BIT(0)
0066
0067 struct hix5hd2_soc_data {
0068     u32 clk_reg;
0069     u32 flags;
0070 };
0071
0072 static const struct hix5hd2_soc_data hix5hd2_data = {
0073     .clk_reg = 0x48,
0074 };
0075
0076 static const struct hix5hd2_soc_data hi3796cv300_data = {
0077     .clk_reg = 0x60,
0078     .flags = HIX5HD2_FLAG_EXTRA_ENABLE,
0079 };
0080
0081 struct hix5hd2_ir_priv {
0082     int         irq;
0083     void __iomem        *base;
0084     struct device       *dev;
0085     struct rc_dev       *rdev;
0086     struct regmap       *regmap;
0087     struct clk      *clock;
0088     unsigned long       rate;
0089     const struct hix5hd2_soc_data *socdata;
0090 };
0091
0092 static int hix5hd2_ir_clk_enable(struct hix5hd2_ir_priv *dev, bool on)
0093 {
0094     u32 clk_reg = dev->socdata->clk_reg;
0095     u32 val;
0096     int ret = 0;
0097
0098     if (dev->regmap) {
0099         regmap_read(dev->regmap, clk_reg, &val);
0100         if (on) {
0101             val &= ~IR_CLK_RESET;
0102             val |= IR_CLK_ENABLE;
0103         } else {
0104             val &= ~IR_CLK_ENABLE;
0105             val |= IR_CLK_RESET;
0106         }
0107         regmap_write(dev->regmap, clk_reg, val);
0108     } else {
0109         if (on)
0110             ret = clk_prepare_enable(dev->clock);
0111         else
0112             clk_disable_unprepare(dev->clock);
0113     }
0114     return ret;
0115 }
0116
0117 static inline void hix5hd2_ir_enable(struct hix5hd2_ir_priv *priv)
0118 {
0119     u32 val = IR_ENABLE_EN;
0120
0121     if (priv->socdata->flags & HIX5HD2_FLAG_EXTRA_ENABLE)
0122         val |= IR_ENABLE_EN_EXTRA;
0123
0124     writel_relaxed(val, priv->base + IR_ENABLE);
0125 }
0126
0127 static int hix5hd2_ir_config(struct hix5hd2_ir_priv *priv)
0128 {
0129     int timeout = 10000;
0130     u32 val, rate;
0131
0132     hix5hd2_ir_enable(priv);
0133
0134     while (readl_relaxed(priv->base + IR_BUSY)) {
0135         if (timeout--) {
0136             udelay(1);
0137         } else {
0138             dev_err(priv->dev, "IR_BUSY timeout\n");
0139             return -ETIMEDOUT;
0140         }
0141     }
0142
0143     /* Now only support raw mode, with symbol start from low to high */
0144     rate = DIV_ROUND_CLOSEST(priv->rate, 1000000);
0145     val = IR_CFG_SYMBOL_MAXWIDTH & IR_CFG_WIDTH_MASK << IR_CFG_WIDTH_SHIFT;
0146     val |= IR_CFG_SYMBOL_FMT & IR_CFG_FORMAT_MASK << IR_CFG_FORMAT_SHIFT;
0147     val |= (IR_CFG_INT_THRESHOLD - 1) & IR_CFG_INT_LEVEL_MASK
0148            << IR_CFG_INT_LEVEL_SHIFT;
0149     val |= IR_CFG_MODE_RAW;
0150     val |= (rate - 1) & IR_CFG_FREQ_MASK << IR_CFG_FREQ_SHIFT;
0151     writel_relaxed(val, priv->base + IR_CONFIG);
0152
0153     writel_relaxed(0x00, priv->base + IR_INTM);
0154     /* write arbitrary value to start  */
0155     writel_relaxed(0x01, priv->base + IR_START);
0156     return 0;
0157 }
0158
0159 static int hix5hd2_ir_open(struct rc_dev *rdev)
0160 {
0161     struct hix5hd2_ir_priv *priv = rdev->priv;
0162     int ret;
0163
0164     ret = hix5hd2_ir_clk_enable(priv, true);
0165     if (ret)
0166         return ret;
0167
0168     ret = hix5hd2_ir_config(priv);
0169     if (ret) {
0170         hix5hd2_ir_clk_enable(priv, false);
0171         return ret;
0172     }
0173     return 0;
0174 }
0175
0176 static void hix5hd2_ir_close(struct rc_dev *rdev)
0177 {
0178     struct hix5hd2_ir_priv *priv = rdev->priv;
0179
0180     hix5hd2_ir_clk_enable(priv, false);
0181 }
0182
0183 static irqreturn_t hix5hd2_ir_rx_interrupt(int irq, void *data)
0184 {
0185     u32 symb_num, symb_val, symb_time;
0186     u32 data_l, data_h;
0187     u32 irq_sr, i;
0188     struct hix5hd2_ir_priv *priv = data;
0189
0190     irq_sr = readl_relaxed(priv->base + IR_INTS);
0191     if (irq_sr & INTMS_OVERFLOW) {
0192         /*
0193          * we must read IR_DATAL first, then we can clean up
0194          * IR_INTS availably since logic would not clear
0195          * fifo when overflow, drv do the job
0196          */
0197         ir_raw_event_overflow(priv->rdev);
0198         symb_num = readl_relaxed(priv->base + IR_DATAH);
0199         for (i = 0; i < symb_num; i++)
0200             readl_relaxed(priv->base + IR_DATAL);
0201
0202         writel_relaxed(INT_CLR_OVERFLOW, priv->base + IR_INTC);
0203         dev_info(priv->dev, "overflow, level=%d\n",
0204              IR_CFG_INT_THRESHOLD);
0205     }
0206
0207     if ((irq_sr & INTMS_SYMBRCV) || (irq_sr & INTMS_TIMEOUT)) {
0208         struct ir_raw_event ev = {};
0209
0210         symb_num = readl_relaxed(priv->base + IR_DATAH);
0211         for (i = 0; i < symb_num; i++) {
0212             symb_val = readl_relaxed(priv->base + IR_DATAL);
0213             data_l = ((symb_val & 0xffff) * 10);
0214             data_h =  ((symb_val >> 16) & 0xffff) * 10;
0215             symb_time = (data_l + data_h) / 10;
0216
0217             ev.duration = data_l;
0218             ev.pulse = true;
0219             ir_raw_event_store(priv->rdev, &ev);
0220
0221             if (symb_time < IR_CFG_SYMBOL_MAXWIDTH) {
0222                 ev.duration = data_h;
0223                 ev.pulse = false;
0224                 ir_raw_event_store(priv->rdev, &ev);
0225             } else {
0226                 ir_raw_event_set_idle(priv->rdev, true);
0227             }
0228         }
0229
0230         if (irq_sr & INTMS_SYMBRCV)
0231             writel_relaxed(INT_CLR_RCV, priv->base + IR_INTC);
0232         if (irq_sr & INTMS_TIMEOUT)
0233             writel_relaxed(INT_CLR_TIMEOUT, priv->base + IR_INTC);
0234     }
0235
0236     /* Empty software fifo */
0237     ir_raw_event_handle(priv->rdev);
0238     return IRQ_HANDLED;
0239 }
0240
0241 static const struct of_device_id hix5hd2_ir_table[] = {
0242     { .compatible = "hisilicon,hix5hd2-ir", &hix5hd2_data, },
0243     { .compatible = "hisilicon,hi3796cv300-ir", &hi3796cv300_data, },
0244     {},
0245 };
0246 MODULE_DEVICE_TABLE(of, hix5hd2_ir_table);
0247
0248 static int hix5hd2_ir_probe(struct platform_device *pdev)
0249 {
0250     struct rc_dev *rdev;
0251     struct device *dev = &pdev->dev;
0252     struct hix5hd2_ir_priv *priv;
0253     struct device_node *node = pdev->dev.of_node;
0254     const struct of_device_id *of_id;
0255     const char *map_name;
0256     int ret;
0257
0258     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0259     if (!priv)
0260         return -ENOMEM;
0261
0262     of_id = of_match_device(hix5hd2_ir_table, dev);
0263     if (!of_id) {
0264         dev_err(dev, "Unable to initialize IR data\n");
0265         return -ENODEV;
0266     }
0267     priv->socdata = of_id->data;
0268
0269     priv->regmap = syscon_regmap_lookup_by_phandle(node,
0270                                "hisilicon,power-syscon");
0271     if (IS_ERR(priv->regmap)) {
0272         dev_info(dev, "no power-reg\n");
0273         priv->regmap = NULL;
0274     }
0275
0276     priv->base = devm_platform_ioremap_resource(pdev, 0);
0277     if (IS_ERR(priv->base))
0278         return PTR_ERR(priv->base);
0279
0280     priv->irq = platform_get_irq(pdev, 0);
0281     if (priv->irq < 0)
0282         return priv->irq;
0283
0284     rdev = rc_allocate_device(RC_DRIVER_IR_RAW);
0285     if (!rdev)
0286         return -ENOMEM;
0287
0288     priv->clock = devm_clk_get(dev, NULL);
0289     if (IS_ERR(priv->clock)) {
0290         dev_err(dev, "clock not found\n");
0291         ret = PTR_ERR(priv->clock);
0292         goto err;
0293     }
0294     ret = clk_prepare_enable(priv->clock);
0295     if (ret)
0296         goto err;
0297     priv->rate = clk_get_rate(priv->clock);
0298
0299     rdev->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER;
0300     rdev->priv = priv;
0301     rdev->open = hix5hd2_ir_open;
0302     rdev->close = hix5hd2_ir_close;
0303     rdev->driver_name = IR_HIX5HD2_NAME;
0304     map_name = of_get_property(node, "linux,rc-map-name", NULL);
0305     rdev->map_name = map_name ?: RC_MAP_EMPTY;
0306     rdev->device_name = IR_HIX5HD2_NAME;
0307     rdev->input_phys = IR_HIX5HD2_NAME "/input0";
0308     rdev->input_id.bustype = BUS_HOST;
0309     rdev->input_id.vendor = 0x0001;
0310     rdev->input_id.product = 0x0001;
0311     rdev->input_id.version = 0x0100;
0312     rdev->rx_resolution = 10;
0313     rdev->timeout = IR_CFG_SYMBOL_MAXWIDTH * 10;
0314
0315     ret = rc_register_device(rdev);
0316     if (ret < 0)
0317         goto clkerr;
0318
0319     if (devm_request_irq(dev, priv->irq, hix5hd2_ir_rx_interrupt,
0320                  0, pdev->name, priv) < 0) {
0321         dev_err(dev, "IRQ %d register failed\n", priv->irq);
0322         ret = -EINVAL;
0323         goto regerr;
0324     }
0325
0326     priv->rdev = rdev;
0327     priv->dev = dev;
0328     platform_set_drvdata(pdev, priv);
0329
0330     return ret;
0331
0332 regerr:
0333     rc_unregister_device(rdev);
0334     rdev = NULL;
0335 clkerr:
0336     clk_disable_unprepare(priv->clock);
0337 err:
0338     rc_free_device(rdev);
0339     dev_err(dev, "Unable to register device (%d)\n", ret);
0340     return ret;
0341 }
0342
0343 static int hix5hd2_ir_remove(struct platform_device *pdev)
0344 {
0345     struct hix5hd2_ir_priv *priv = platform_get_drvdata(pdev);
0346
0347     clk_disable_unprepare(priv->clock);
0348     rc_unregister_device(priv->rdev);
0349     return 0;
0350 }
0351
0352 #ifdef CONFIG_PM_SLEEP
0353 static int hix5hd2_ir_suspend(struct device *dev)
0354 {
0355     struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
0356
0357     clk_disable_unprepare(priv->clock);
0358     hix5hd2_ir_clk_enable(priv, false);
0359
0360     return 0;
0361 }
0362
0363 static int hix5hd2_ir_resume(struct device *dev)
0364 {
0365     struct hix5hd2_ir_priv *priv = dev_get_drvdata(dev);
0366     int ret;
0367
0368     ret = hix5hd2_ir_clk_enable(priv, true);
0369     if (ret)
0370         return ret;
0371
0372     ret = clk_prepare_enable(priv->clock);
0373     if (ret) {
0374         hix5hd2_ir_clk_enable(priv, false);
0375         return ret;
0376     }
0377
0378     hix5hd2_ir_enable(priv);
0379
0380     writel_relaxed(0x00, priv->base + IR_INTM);
0381     writel_relaxed(0xff, priv->base + IR_INTC);
0382     writel_relaxed(0x01, priv->base + IR_START);
0383
0384     return 0;
0385 }
0386 #endif
0387
0388 static SIMPLE_DEV_PM_OPS(hix5hd2_ir_pm_ops, hix5hd2_ir_suspend,
0389              hix5hd2_ir_resume);
0390
0391 static struct platform_driver hix5hd2_ir_driver = {
0392     .driver = {
0393         .name = IR_HIX5HD2_NAME,
0394         .of_match_table = hix5hd2_ir_table,
0395         .pm     = &hix5hd2_ir_pm_ops,
0396     },
0397     .probe = hix5hd2_ir_probe,
0398     .remove = hix5hd2_ir_remove,
0399 };
0400
0401 module_platform_driver(hix5hd2_ir_driver);
0402
0403 MODULE_DESCRIPTION("IR controller driver for hix5hd2 platforms");
0404 MODULE_AUTHOR("Guoxiong Yan <yanguoxiong@huawei.com>");
0405 MODULE_LICENSE("GPL v2");
0406 MODULE_ALIAS("platform:hix5hd2-ir");