rc/img-ir/img-ir.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * ImgTec IR Decoder found in PowerDown Controller.
0004  *
0005  * Copyright 2010-2014 Imagination Technologies Ltd.
0006  */
0007
0008 #ifndef _IMG_IR_H_
0009 #define _IMG_IR_H_
0010
0011 #include <linux/io.h>
0012 #include <linux/spinlock.h>
0013
0014 #include "img-ir-raw.h"
0015 #include "img-ir-hw.h"
0016
0017 /* registers */
0018
0019 /* relative to the start of the IR block of registers */
0020 #define IMG_IR_CONTROL      0x00
0021 #define IMG_IR_STATUS       0x04
0022 #define IMG_IR_DATA_LW      0x08
0023 #define IMG_IR_DATA_UP      0x0c
0024 #define IMG_IR_LEAD_SYMB_TIMING 0x10
0025 #define IMG_IR_S00_SYMB_TIMING  0x14
0026 #define IMG_IR_S01_SYMB_TIMING  0x18
0027 #define IMG_IR_S10_SYMB_TIMING  0x1c
0028 #define IMG_IR_S11_SYMB_TIMING  0x20
0029 #define IMG_IR_FREE_SYMB_TIMING 0x24
0030 #define IMG_IR_POW_MOD_PARAMS   0x28
0031 #define IMG_IR_POW_MOD_ENABLE   0x2c
0032 #define IMG_IR_IRQ_MSG_DATA_LW  0x30
0033 #define IMG_IR_IRQ_MSG_DATA_UP  0x34
0034 #define IMG_IR_IRQ_MSG_MASK_LW  0x38
0035 #define IMG_IR_IRQ_MSG_MASK_UP  0x3c
0036 #define IMG_IR_IRQ_ENABLE   0x40
0037 #define IMG_IR_IRQ_STATUS   0x44
0038 #define IMG_IR_IRQ_CLEAR    0x48
0039 #define IMG_IR_IRCORE_ID    0xf0
0040 #define IMG_IR_CORE_REV     0xf4
0041 #define IMG_IR_CORE_DES1    0xf8
0042 #define IMG_IR_CORE_DES2    0xfc
0043
0044
0045 /* field masks */
0046
0047 /* IMG_IR_CONTROL */
0048 #define IMG_IR_DECODEN      0x40000000
0049 #define IMG_IR_CODETYPE     0x30000000
0050 #define IMG_IR_CODETYPE_SHIFT       28
0051 #define IMG_IR_HDRTOG       0x08000000
0052 #define IMG_IR_LDRDEC       0x04000000
0053 #define IMG_IR_DECODINPOL   0x02000000  /* active high */
0054 #define IMG_IR_BITORIEN     0x01000000  /* MSB first */
0055 #define IMG_IR_D1VALIDSEL   0x00008000
0056 #define IMG_IR_BITINV       0x00000040  /* don't invert */
0057 #define IMG_IR_DECODEND2    0x00000010
0058 #define IMG_IR_BITORIEND2   0x00000002  /* MSB first */
0059 #define IMG_IR_BITINVD2     0x00000001  /* don't invert */
0060
0061 /* IMG_IR_STATUS */
0062 #define IMG_IR_RXDVALD2     0x00001000
0063 #define IMG_IR_IRRXD        0x00000400
0064 #define IMG_IR_TOGSTATE     0x00000200
0065 #define IMG_IR_RXDVAL       0x00000040
0066 #define IMG_IR_RXDLEN       0x0000003f
0067 #define IMG_IR_RXDLEN_SHIFT     0
0068
0069 /* IMG_IR_LEAD_SYMB_TIMING, IMG_IR_Sxx_SYMB_TIMING */
0070 #define IMG_IR_PD_MAX       0xff000000
0071 #define IMG_IR_PD_MAX_SHIFT     24
0072 #define IMG_IR_PD_MIN       0x00ff0000
0073 #define IMG_IR_PD_MIN_SHIFT     16
0074 #define IMG_IR_W_MAX        0x0000ff00
0075 #define IMG_IR_W_MAX_SHIFT      8
0076 #define IMG_IR_W_MIN        0x000000ff
0077 #define IMG_IR_W_MIN_SHIFT      0
0078
0079 /* IMG_IR_FREE_SYMB_TIMING */
0080 #define IMG_IR_MAXLEN       0x0007e000
0081 #define IMG_IR_MAXLEN_SHIFT     13
0082 #define IMG_IR_MINLEN       0x00001f00
0083 #define IMG_IR_MINLEN_SHIFT     8
0084 #define IMG_IR_FT_MIN       0x000000ff
0085 #define IMG_IR_FT_MIN_SHIFT     0
0086
0087 /* IMG_IR_POW_MOD_PARAMS */
0088 #define IMG_IR_PERIOD_LEN   0x3f000000
0089 #define IMG_IR_PERIOD_LEN_SHIFT     24
0090 #define IMG_IR_PERIOD_DUTY  0x003f0000
0091 #define IMG_IR_PERIOD_DUTY_SHIFT    16
0092 #define IMG_IR_STABLE_STOP  0x00003f00
0093 #define IMG_IR_STABLE_STOP_SHIFT    8
0094 #define IMG_IR_STABLE_START 0x0000003f
0095 #define IMG_IR_STABLE_START_SHIFT   0
0096
0097 /* IMG_IR_POW_MOD_ENABLE */
0098 #define IMG_IR_POWER_OUT_EN 0x00000002
0099 #define IMG_IR_POWER_MOD_EN 0x00000001
0100
0101 /* IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_STATUS, IMG_IR_IRQ_CLEAR */
0102 #define IMG_IR_IRQ_DEC2_ERR 0x00000080
0103 #define IMG_IR_IRQ_DEC_ERR  0x00000040
0104 #define IMG_IR_IRQ_ACT_LEVEL    0x00000020
0105 #define IMG_IR_IRQ_FALL_EDGE    0x00000010
0106 #define IMG_IR_IRQ_RISE_EDGE    0x00000008
0107 #define IMG_IR_IRQ_DATA_MATCH   0x00000004
0108 #define IMG_IR_IRQ_DATA2_VALID  0x00000002
0109 #define IMG_IR_IRQ_DATA_VALID   0x00000001
0110 #define IMG_IR_IRQ_ALL      0x000000ff
0111 #define IMG_IR_IRQ_EDGE     (IMG_IR_IRQ_FALL_EDGE | IMG_IR_IRQ_RISE_EDGE)
0112
0113 /* IMG_IR_CORE_ID */
0114 #define IMG_IR_CORE_ID      0x00ff0000
0115 #define IMG_IR_CORE_ID_SHIFT        16
0116 #define IMG_IR_CORE_CONFIG  0x0000ffff
0117 #define IMG_IR_CORE_CONFIG_SHIFT    0
0118
0119 /* IMG_IR_CORE_REV */
0120 #define IMG_IR_DESIGNER     0xff000000
0121 #define IMG_IR_DESIGNER_SHIFT       24
0122 #define IMG_IR_MAJOR_REV    0x00ff0000
0123 #define IMG_IR_MAJOR_REV_SHIFT      16
0124 #define IMG_IR_MINOR_REV    0x0000ff00
0125 #define IMG_IR_MINOR_REV_SHIFT      8
0126 #define IMG_IR_MAINT_REV    0x000000ff
0127 #define IMG_IR_MAINT_REV_SHIFT      0
0128
0129 struct device;
0130 struct clk;
0131
0132 /**
0133  * struct img_ir_priv - Private driver data.
0134  * @dev:        Platform device.
0135  * @irq:        IRQ number.
0136  * @clk:        Input clock.
0137  * @sys_clk:        System clock.
0138  * @reg_base:       Iomem base address of IR register block.
0139  * @lock:       Protects IR registers and variables in this struct.
0140  * @raw:        Driver data for raw decoder.
0141  * @hw:         Driver data for hardware decoder.
0142  */
0143 struct img_ir_priv {
0144     struct device       *dev;
0145     int         irq;
0146     struct clk      *clk;
0147     struct clk      *sys_clk;
0148     void __iomem        *reg_base;
0149     spinlock_t      lock;
0150
0151     struct img_ir_priv_raw  raw;
0152     struct img_ir_priv_hw   hw;
0153 };
0154
0155 /* Hardware access */
0156
0157 static inline void img_ir_write(struct img_ir_priv *priv,
0158                 unsigned int reg_offs, unsigned int data)
0159 {
0160     iowrite32(data, priv->reg_base + reg_offs);
0161 }
0162
0163 static inline unsigned int img_ir_read(struct img_ir_priv *priv,
0164                        unsigned int reg_offs)
0165 {
0166     return ioread32(priv->reg_base + reg_offs);
0167 }
0168
0169 #endif /* _IMG_IR_H_ */