Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ImgTec IR Hardware Decoder found in PowerDown Controller.
0004  *
0005  * Copyright 2010-2014 Imagination Technologies Ltd.
0006  *
0007  * This ties into the input subsystem using the RC-core. Protocol support is
0008  * provided in separate modules which provide the parameters and scancode
0009  * translation functions to set up the hardware decoder and interpret the
0010  * resulting input.
0011  */
0012 
0013 #include <linux/bitops.h>
0014 #include <linux/clk.h>
0015 #include <linux/interrupt.h>
0016 #include <linux/spinlock.h>
0017 #include <linux/timer.h>
0018 #include <media/rc-core.h>
0019 #include "img-ir.h"
0020 
0021 /* Decoders lock (only modified to preprocess them) */
0022 static DEFINE_SPINLOCK(img_ir_decoders_lock);
0023 
0024 static bool img_ir_decoders_preprocessed;
0025 static struct img_ir_decoder *img_ir_decoders[] = {
0026 #ifdef CONFIG_IR_IMG_NEC
0027     &img_ir_nec,
0028 #endif
0029 #ifdef CONFIG_IR_IMG_JVC
0030     &img_ir_jvc,
0031 #endif
0032 #ifdef CONFIG_IR_IMG_SONY
0033     &img_ir_sony,
0034 #endif
0035 #ifdef CONFIG_IR_IMG_SHARP
0036     &img_ir_sharp,
0037 #endif
0038 #ifdef CONFIG_IR_IMG_SANYO
0039     &img_ir_sanyo,
0040 #endif
0041 #ifdef CONFIG_IR_IMG_RC5
0042     &img_ir_rc5,
0043 #endif
0044 #ifdef CONFIG_IR_IMG_RC6
0045     &img_ir_rc6,
0046 #endif
0047     NULL
0048 };
0049 
0050 #define IMG_IR_F_FILTER     BIT(RC_FILTER_NORMAL)   /* enable filtering */
0051 #define IMG_IR_F_WAKE       BIT(RC_FILTER_WAKEUP)   /* enable waking */
0052 
0053 /* code type quirks */
0054 
0055 #define IMG_IR_QUIRK_CODE_BROKEN    0x1 /* Decode is broken */
0056 #define IMG_IR_QUIRK_CODE_LEN_INCR  0x2 /* Bit length needs increment */
0057 /*
0058  * The decoder generates rapid interrupts without actually having
0059  * received any new data after an incomplete IR code is decoded.
0060  */
0061 #define IMG_IR_QUIRK_CODE_IRQ       0x4
0062 
0063 /* functions for preprocessing timings, ensuring max is set */
0064 
0065 static void img_ir_timing_preprocess(struct img_ir_timing_range *range,
0066                      unsigned int unit)
0067 {
0068     if (range->max < range->min)
0069         range->max = range->min;
0070     if (unit) {
0071         /* multiply by unit and convert to microseconds */
0072         range->min = (range->min*unit)/1000;
0073         range->max = (range->max*unit + 999)/1000; /* round up */
0074     }
0075 }
0076 
0077 static void img_ir_symbol_timing_preprocess(struct img_ir_symbol_timing *timing,
0078                         unsigned int unit)
0079 {
0080     img_ir_timing_preprocess(&timing->pulse, unit);
0081     img_ir_timing_preprocess(&timing->space, unit);
0082 }
0083 
0084 static void img_ir_timings_preprocess(struct img_ir_timings *timings,
0085                       unsigned int unit)
0086 {
0087     img_ir_symbol_timing_preprocess(&timings->ldr, unit);
0088     img_ir_symbol_timing_preprocess(&timings->s00, unit);
0089     img_ir_symbol_timing_preprocess(&timings->s01, unit);
0090     img_ir_symbol_timing_preprocess(&timings->s10, unit);
0091     img_ir_symbol_timing_preprocess(&timings->s11, unit);
0092     /* default s10 and s11 to s00 and s01 if no leader */
0093     if (unit)
0094         /* multiply by unit and convert to microseconds (round up) */
0095         timings->ft.ft_min = (timings->ft.ft_min*unit + 999)/1000;
0096 }
0097 
0098 /* functions for filling empty fields with defaults */
0099 
0100 static void img_ir_timing_defaults(struct img_ir_timing_range *range,
0101                    struct img_ir_timing_range *defaults)
0102 {
0103     if (!range->min)
0104         range->min = defaults->min;
0105     if (!range->max)
0106         range->max = defaults->max;
0107 }
0108 
0109 static void img_ir_symbol_timing_defaults(struct img_ir_symbol_timing *timing,
0110                       struct img_ir_symbol_timing *defaults)
0111 {
0112     img_ir_timing_defaults(&timing->pulse, &defaults->pulse);
0113     img_ir_timing_defaults(&timing->space, &defaults->space);
0114 }
0115 
0116 static void img_ir_timings_defaults(struct img_ir_timings *timings,
0117                     struct img_ir_timings *defaults)
0118 {
0119     img_ir_symbol_timing_defaults(&timings->ldr, &defaults->ldr);
0120     img_ir_symbol_timing_defaults(&timings->s00, &defaults->s00);
0121     img_ir_symbol_timing_defaults(&timings->s01, &defaults->s01);
0122     img_ir_symbol_timing_defaults(&timings->s10, &defaults->s10);
0123     img_ir_symbol_timing_defaults(&timings->s11, &defaults->s11);
0124     if (!timings->ft.ft_min)
0125         timings->ft.ft_min = defaults->ft.ft_min;
0126 }
0127 
0128 /* functions for converting timings to register values */
0129 
0130 /**
0131  * img_ir_control() - Convert control struct to control register value.
0132  * @control:    Control data
0133  *
0134  * Returns: The control register value equivalent of @control.
0135  */
0136 static u32 img_ir_control(const struct img_ir_control *control)
0137 {
0138     u32 ctrl = control->code_type << IMG_IR_CODETYPE_SHIFT;
0139     if (control->decoden)
0140         ctrl |= IMG_IR_DECODEN;
0141     if (control->hdrtog)
0142         ctrl |= IMG_IR_HDRTOG;
0143     if (control->ldrdec)
0144         ctrl |= IMG_IR_LDRDEC;
0145     if (control->decodinpol)
0146         ctrl |= IMG_IR_DECODINPOL;
0147     if (control->bitorien)
0148         ctrl |= IMG_IR_BITORIEN;
0149     if (control->d1validsel)
0150         ctrl |= IMG_IR_D1VALIDSEL;
0151     if (control->bitinv)
0152         ctrl |= IMG_IR_BITINV;
0153     if (control->decodend2)
0154         ctrl |= IMG_IR_DECODEND2;
0155     if (control->bitoriend2)
0156         ctrl |= IMG_IR_BITORIEND2;
0157     if (control->bitinvd2)
0158         ctrl |= IMG_IR_BITINVD2;
0159     return ctrl;
0160 }
0161 
0162 /**
0163  * img_ir_timing_range_convert() - Convert microsecond range.
0164  * @out:    Output timing range in clock cycles with a shift.
0165  * @in:     Input timing range in microseconds.
0166  * @tolerance:  Tolerance as a fraction of 128 (roughly percent).
0167  * @clock_hz:   IR clock rate in Hz.
0168  * @shift:  Shift of output units.
0169  *
0170  * Converts min and max from microseconds to IR clock cycles, applies a
0171  * tolerance, and shifts for the register, rounding in the right direction.
0172  * Note that in and out can safely be the same object.
0173  */
0174 static void img_ir_timing_range_convert(struct img_ir_timing_range *out,
0175                     const struct img_ir_timing_range *in,
0176                     unsigned int tolerance,
0177                     unsigned long clock_hz,
0178                     unsigned int shift)
0179 {
0180     unsigned int min = in->min;
0181     unsigned int max = in->max;
0182     /* add a tolerance */
0183     min = min - (min*tolerance >> 7);
0184     max = max + (max*tolerance >> 7);
0185     /* convert from microseconds into clock cycles */
0186     min = min*clock_hz / 1000000;
0187     max = (max*clock_hz + 999999) / 1000000; /* round up */
0188     /* apply shift and copy to output */
0189     out->min = min >> shift;
0190     out->max = (max + ((1 << shift) - 1)) >> shift; /* round up */
0191 }
0192 
0193 /**
0194  * img_ir_symbol_timing() - Convert symbol timing struct to register value.
0195  * @timing: Symbol timing data
0196  * @tolerance:  Timing tolerance where 0-128 represents 0-100%
0197  * @clock_hz:   Frequency of source clock in Hz
0198  * @pd_shift:   Shift to apply to symbol period
0199  * @w_shift:    Shift to apply to symbol width
0200  *
0201  * Returns: Symbol timing register value based on arguments.
0202  */
0203 static u32 img_ir_symbol_timing(const struct img_ir_symbol_timing *timing,
0204                 unsigned int tolerance,
0205                 unsigned long clock_hz,
0206                 unsigned int pd_shift,
0207                 unsigned int w_shift)
0208 {
0209     struct img_ir_timing_range hw_pulse, hw_period;
0210     /* we calculate period in hw_period, then convert in place */
0211     hw_period.min = timing->pulse.min + timing->space.min;
0212     hw_period.max = timing->pulse.max + timing->space.max;
0213     img_ir_timing_range_convert(&hw_period, &hw_period,
0214             tolerance, clock_hz, pd_shift);
0215     img_ir_timing_range_convert(&hw_pulse, &timing->pulse,
0216             tolerance, clock_hz, w_shift);
0217     /* construct register value */
0218     return  (hw_period.max  << IMG_IR_PD_MAX_SHIFT) |
0219         (hw_period.min  << IMG_IR_PD_MIN_SHIFT) |
0220         (hw_pulse.max   << IMG_IR_W_MAX_SHIFT)  |
0221         (hw_pulse.min   << IMG_IR_W_MIN_SHIFT);
0222 }
0223 
0224 /**
0225  * img_ir_free_timing() - Convert free time timing struct to register value.
0226  * @timing: Free symbol timing data
0227  * @clock_hz:   Source clock frequency in Hz
0228  *
0229  * Returns: Free symbol timing register value.
0230  */
0231 static u32 img_ir_free_timing(const struct img_ir_free_timing *timing,
0232                   unsigned long clock_hz)
0233 {
0234     unsigned int minlen, maxlen, ft_min;
0235     /* minlen is only 5 bits, and round minlen to multiple of 2 */
0236     if (timing->minlen < 30)
0237         minlen = timing->minlen & -2;
0238     else
0239         minlen = 30;
0240     /* maxlen has maximum value of 48, and round maxlen to multiple of 2 */
0241     if (timing->maxlen < 48)
0242         maxlen = (timing->maxlen + 1) & -2;
0243     else
0244         maxlen = 48;
0245     /* convert and shift ft_min, rounding upwards */
0246     ft_min = (timing->ft_min*clock_hz + 999999) / 1000000;
0247     ft_min = (ft_min + 7) >> 3;
0248     /* construct register value */
0249     return  (maxlen << IMG_IR_MAXLEN_SHIFT) |
0250         (minlen << IMG_IR_MINLEN_SHIFT) |
0251         (ft_min << IMG_IR_FT_MIN_SHIFT);
0252 }
0253 
0254 /**
0255  * img_ir_free_timing_dynamic() - Update free time register value.
0256  * @st_ft:  Static free time register value from img_ir_free_timing.
0257  * @filter: Current filter which may additionally restrict min/max len.
0258  *
0259  * Returns: Updated free time register value based on the current filter.
0260  */
0261 static u32 img_ir_free_timing_dynamic(u32 st_ft, struct img_ir_filter *filter)
0262 {
0263     unsigned int minlen, maxlen, newminlen, newmaxlen;
0264 
0265     /* round minlen, maxlen to multiple of 2 */
0266     newminlen = filter->minlen & -2;
0267     newmaxlen = (filter->maxlen + 1) & -2;
0268     /* extract min/max len from register */
0269     minlen = (st_ft & IMG_IR_MINLEN) >> IMG_IR_MINLEN_SHIFT;
0270     maxlen = (st_ft & IMG_IR_MAXLEN) >> IMG_IR_MAXLEN_SHIFT;
0271     /* if the new values are more restrictive, update the register value */
0272     if (newminlen > minlen) {
0273         st_ft &= ~IMG_IR_MINLEN;
0274         st_ft |= newminlen << IMG_IR_MINLEN_SHIFT;
0275     }
0276     if (newmaxlen < maxlen) {
0277         st_ft &= ~IMG_IR_MAXLEN;
0278         st_ft |= newmaxlen << IMG_IR_MAXLEN_SHIFT;
0279     }
0280     return st_ft;
0281 }
0282 
0283 /**
0284  * img_ir_timings_convert() - Convert timings to register values
0285  * @regs:   Output timing register values
0286  * @timings:    Input timing data
0287  * @tolerance:  Timing tolerance where 0-128 represents 0-100%
0288  * @clock_hz:   Source clock frequency in Hz
0289  */
0290 static void img_ir_timings_convert(struct img_ir_timing_regvals *regs,
0291                    const struct img_ir_timings *timings,
0292                    unsigned int tolerance,
0293                    unsigned int clock_hz)
0294 {
0295     /* leader symbol timings are divided by 16 */
0296     regs->ldr = img_ir_symbol_timing(&timings->ldr, tolerance, clock_hz,
0297             4, 4);
0298     /* other symbol timings, pd fields only are divided by 2 */
0299     regs->s00 = img_ir_symbol_timing(&timings->s00, tolerance, clock_hz,
0300             1, 0);
0301     regs->s01 = img_ir_symbol_timing(&timings->s01, tolerance, clock_hz,
0302             1, 0);
0303     regs->s10 = img_ir_symbol_timing(&timings->s10, tolerance, clock_hz,
0304             1, 0);
0305     regs->s11 = img_ir_symbol_timing(&timings->s11, tolerance, clock_hz,
0306             1, 0);
0307     regs->ft = img_ir_free_timing(&timings->ft, clock_hz);
0308 }
0309 
0310 /**
0311  * img_ir_decoder_preprocess() - Preprocess timings in decoder.
0312  * @decoder:    Decoder to be preprocessed.
0313  *
0314  * Ensures that the symbol timing ranges are valid with respect to ordering, and
0315  * does some fixed conversion on them.
0316  */
0317 static void img_ir_decoder_preprocess(struct img_ir_decoder *decoder)
0318 {
0319     /* default tolerance */
0320     if (!decoder->tolerance)
0321         decoder->tolerance = 10; /* percent */
0322     /* and convert tolerance to fraction out of 128 */
0323     decoder->tolerance = decoder->tolerance * 128 / 100;
0324 
0325     /* fill in implicit fields */
0326     img_ir_timings_preprocess(&decoder->timings, decoder->unit);
0327 
0328     /* do the same for repeat timings if applicable */
0329     if (decoder->repeat) {
0330         img_ir_timings_preprocess(&decoder->rtimings, decoder->unit);
0331         img_ir_timings_defaults(&decoder->rtimings, &decoder->timings);
0332     }
0333 }
0334 
0335 /**
0336  * img_ir_decoder_convert() - Generate internal timings in decoder.
0337  * @decoder:    Decoder to be converted to internal timings.
0338  * @reg_timings: Timing register values.
0339  * @clock_hz:   IR clock rate in Hz.
0340  *
0341  * Fills out the repeat timings and timing register values for a specific clock
0342  * rate.
0343  */
0344 static void img_ir_decoder_convert(const struct img_ir_decoder *decoder,
0345                    struct img_ir_reg_timings *reg_timings,
0346                    unsigned int clock_hz)
0347 {
0348     /* calculate control value */
0349     reg_timings->ctrl = img_ir_control(&decoder->control);
0350 
0351     /* fill in implicit fields and calculate register values */
0352     img_ir_timings_convert(&reg_timings->timings, &decoder->timings,
0353                    decoder->tolerance, clock_hz);
0354 
0355     /* do the same for repeat timings if applicable */
0356     if (decoder->repeat)
0357         img_ir_timings_convert(&reg_timings->rtimings,
0358                        &decoder->rtimings, decoder->tolerance,
0359                        clock_hz);
0360 }
0361 
0362 /**
0363  * img_ir_write_timings() - Write timings to the hardware now
0364  * @priv:   IR private data
0365  * @regs:   Timing register values to write
0366  * @type:   RC filter type (RC_FILTER_*)
0367  *
0368  * Write timing register values @regs to the hardware, taking into account the
0369  * current filter which may impose restrictions on the length of the expected
0370  * data.
0371  */
0372 static void img_ir_write_timings(struct img_ir_priv *priv,
0373                  struct img_ir_timing_regvals *regs,
0374                  enum rc_filter_type type)
0375 {
0376     struct img_ir_priv_hw *hw = &priv->hw;
0377 
0378     /* filter may be more restrictive to minlen, maxlen */
0379     u32 ft = regs->ft;
0380     if (hw->flags & BIT(type))
0381         ft = img_ir_free_timing_dynamic(regs->ft, &hw->filters[type]);
0382     /* write to registers */
0383     img_ir_write(priv, IMG_IR_LEAD_SYMB_TIMING, regs->ldr);
0384     img_ir_write(priv, IMG_IR_S00_SYMB_TIMING, regs->s00);
0385     img_ir_write(priv, IMG_IR_S01_SYMB_TIMING, regs->s01);
0386     img_ir_write(priv, IMG_IR_S10_SYMB_TIMING, regs->s10);
0387     img_ir_write(priv, IMG_IR_S11_SYMB_TIMING, regs->s11);
0388     img_ir_write(priv, IMG_IR_FREE_SYMB_TIMING, ft);
0389     dev_dbg(priv->dev, "timings: ldr=%#x, s=[%#x, %#x, %#x, %#x], ft=%#x\n",
0390         regs->ldr, regs->s00, regs->s01, regs->s10, regs->s11, ft);
0391 }
0392 
0393 static void img_ir_write_filter(struct img_ir_priv *priv,
0394                 struct img_ir_filter *filter)
0395 {
0396     if (filter) {
0397         dev_dbg(priv->dev, "IR filter=%016llx & %016llx\n",
0398             (unsigned long long)filter->data,
0399             (unsigned long long)filter->mask);
0400         img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_LW, (u32)filter->data);
0401         img_ir_write(priv, IMG_IR_IRQ_MSG_DATA_UP, (u32)(filter->data
0402                                     >> 32));
0403         img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, (u32)filter->mask);
0404         img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, (u32)(filter->mask
0405                                     >> 32));
0406     } else {
0407         dev_dbg(priv->dev, "IR clearing filter\n");
0408         img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_LW, 0);
0409         img_ir_write(priv, IMG_IR_IRQ_MSG_MASK_UP, 0);
0410     }
0411 }
0412 
0413 /* caller must have lock */
0414 static void _img_ir_set_filter(struct img_ir_priv *priv,
0415                    struct img_ir_filter *filter)
0416 {
0417     struct img_ir_priv_hw *hw = &priv->hw;
0418     u32 irq_en, irq_on;
0419 
0420     irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
0421     if (filter) {
0422         /* Only use the match interrupt */
0423         hw->filters[RC_FILTER_NORMAL] = *filter;
0424         hw->flags |= IMG_IR_F_FILTER;
0425         irq_on = IMG_IR_IRQ_DATA_MATCH;
0426         irq_en &= ~(IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID);
0427     } else {
0428         /* Only use the valid interrupt */
0429         hw->flags &= ~IMG_IR_F_FILTER;
0430         irq_en &= ~IMG_IR_IRQ_DATA_MATCH;
0431         irq_on = IMG_IR_IRQ_DATA_VALID | IMG_IR_IRQ_DATA2_VALID;
0432     }
0433     irq_en |= irq_on;
0434 
0435     img_ir_write_filter(priv, filter);
0436     /* clear any interrupts we're enabling so we don't handle old ones */
0437     img_ir_write(priv, IMG_IR_IRQ_CLEAR, irq_on);
0438     img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en);
0439 }
0440 
0441 /* caller must have lock */
0442 static void _img_ir_set_wake_filter(struct img_ir_priv *priv,
0443                     struct img_ir_filter *filter)
0444 {
0445     struct img_ir_priv_hw *hw = &priv->hw;
0446     if (filter) {
0447         /* Enable wake, and copy filter for later */
0448         hw->filters[RC_FILTER_WAKEUP] = *filter;
0449         hw->flags |= IMG_IR_F_WAKE;
0450     } else {
0451         /* Disable wake */
0452         hw->flags &= ~IMG_IR_F_WAKE;
0453     }
0454 }
0455 
0456 /* Callback for setting scancode filter */
0457 static int img_ir_set_filter(struct rc_dev *dev, enum rc_filter_type type,
0458                  struct rc_scancode_filter *sc_filter)
0459 {
0460     struct img_ir_priv *priv = dev->priv;
0461     struct img_ir_priv_hw *hw = &priv->hw;
0462     struct img_ir_filter filter, *filter_ptr = &filter;
0463     int ret = 0;
0464 
0465     dev_dbg(priv->dev, "IR scancode %sfilter=%08x & %08x\n",
0466         type == RC_FILTER_WAKEUP ? "wake " : "",
0467         sc_filter->data,
0468         sc_filter->mask);
0469 
0470     spin_lock_irq(&priv->lock);
0471 
0472     /* filtering can always be disabled */
0473     if (!sc_filter->mask) {
0474         filter_ptr = NULL;
0475         goto set_unlock;
0476     }
0477 
0478     /* current decoder must support scancode filtering */
0479     if (!hw->decoder || !hw->decoder->filter) {
0480         ret = -EINVAL;
0481         goto unlock;
0482     }
0483 
0484     /* convert scancode filter to raw filter */
0485     filter.minlen = 0;
0486     filter.maxlen = ~0;
0487     if (type == RC_FILTER_NORMAL) {
0488         /* guess scancode from protocol */
0489         ret = hw->decoder->filter(sc_filter, &filter,
0490                       dev->enabled_protocols);
0491     } else {
0492         /* for wakeup user provided exact protocol variant */
0493         ret = hw->decoder->filter(sc_filter, &filter,
0494                       1ULL << dev->wakeup_protocol);
0495     }
0496     if (ret)
0497         goto unlock;
0498     dev_dbg(priv->dev, "IR raw %sfilter=%016llx & %016llx\n",
0499         type == RC_FILTER_WAKEUP ? "wake " : "",
0500         (unsigned long long)filter.data,
0501         (unsigned long long)filter.mask);
0502 
0503 set_unlock:
0504     /* apply raw filters */
0505     switch (type) {
0506     case RC_FILTER_NORMAL:
0507         _img_ir_set_filter(priv, filter_ptr);
0508         break;
0509     case RC_FILTER_WAKEUP:
0510         _img_ir_set_wake_filter(priv, filter_ptr);
0511         break;
0512     default:
0513         ret = -EINVAL;
0514     }
0515 
0516 unlock:
0517     spin_unlock_irq(&priv->lock);
0518     return ret;
0519 }
0520 
0521 static int img_ir_set_normal_filter(struct rc_dev *dev,
0522                     struct rc_scancode_filter *sc_filter)
0523 {
0524     return img_ir_set_filter(dev, RC_FILTER_NORMAL, sc_filter);
0525 }
0526 
0527 static int img_ir_set_wakeup_filter(struct rc_dev *dev,
0528                     struct rc_scancode_filter *sc_filter)
0529 {
0530     return img_ir_set_filter(dev, RC_FILTER_WAKEUP, sc_filter);
0531 }
0532 
0533 /**
0534  * img_ir_set_decoder() - Set the current decoder.
0535  * @priv:   IR private data.
0536  * @decoder:    Decoder to use with immediate effect.
0537  * @proto:  Protocol bitmap (or 0 to use decoder->type).
0538  */
0539 static void img_ir_set_decoder(struct img_ir_priv *priv,
0540                    const struct img_ir_decoder *decoder,
0541                    u64 proto)
0542 {
0543     struct img_ir_priv_hw *hw = &priv->hw;
0544     struct rc_dev *rdev = hw->rdev;
0545     u32 ir_status, irq_en;
0546     spin_lock_irq(&priv->lock);
0547 
0548     /*
0549      * First record that the protocol is being stopped so that the end timer
0550      * isn't restarted while we're trying to stop it.
0551      */
0552     hw->stopping = true;
0553 
0554     /*
0555      * Release the lock to stop the end timer, since the end timer handler
0556      * acquires the lock and we don't want to deadlock waiting for it.
0557      */
0558     spin_unlock_irq(&priv->lock);
0559     del_timer_sync(&hw->end_timer);
0560     del_timer_sync(&hw->suspend_timer);
0561     spin_lock_irq(&priv->lock);
0562 
0563     hw->stopping = false;
0564 
0565     /* switch off and disable interrupts */
0566     img_ir_write(priv, IMG_IR_CONTROL, 0);
0567     irq_en = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
0568     img_ir_write(priv, IMG_IR_IRQ_ENABLE, irq_en & IMG_IR_IRQ_EDGE);
0569     img_ir_write(priv, IMG_IR_IRQ_CLEAR, IMG_IR_IRQ_ALL & ~IMG_IR_IRQ_EDGE);
0570 
0571     /* ack any data already detected */
0572     ir_status = img_ir_read(priv, IMG_IR_STATUS);
0573     if (ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2)) {
0574         ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2);
0575         img_ir_write(priv, IMG_IR_STATUS, ir_status);
0576     }
0577 
0578     /* always read data to clear buffer if IR wakes the device */
0579     img_ir_read(priv, IMG_IR_DATA_LW);
0580     img_ir_read(priv, IMG_IR_DATA_UP);
0581 
0582     /* switch back to normal mode */
0583     hw->mode = IMG_IR_M_NORMAL;
0584 
0585     /* clear the wakeup scancode filter */
0586     rdev->scancode_wakeup_filter.data = 0;
0587     rdev->scancode_wakeup_filter.mask = 0;
0588     rdev->wakeup_protocol = RC_PROTO_UNKNOWN;
0589 
0590     /* clear raw filters */
0591     _img_ir_set_filter(priv, NULL);
0592     _img_ir_set_wake_filter(priv, NULL);
0593 
0594     /* clear the enabled protocols */
0595     hw->enabled_protocols = 0;
0596 
0597     /* switch decoder */
0598     hw->decoder = decoder;
0599     if (!decoder)
0600         goto unlock;
0601 
0602     /* set the enabled protocols */
0603     if (!proto)
0604         proto = decoder->type;
0605     hw->enabled_protocols = proto;
0606 
0607     /* write the new timings */
0608     img_ir_decoder_convert(decoder, &hw->reg_timings, hw->clk_hz);
0609     img_ir_write_timings(priv, &hw->reg_timings.timings, RC_FILTER_NORMAL);
0610 
0611     /* set up and enable */
0612     img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
0613 
0614 
0615 unlock:
0616     spin_unlock_irq(&priv->lock);
0617 }
0618 
0619 /**
0620  * img_ir_decoder_compatible() - Find whether a decoder will work with a device.
0621  * @priv:   IR private data.
0622  * @dec:    Decoder to check.
0623  *
0624  * Returns: true if @dec is compatible with the device @priv refers to.
0625  */
0626 static bool img_ir_decoder_compatible(struct img_ir_priv *priv,
0627                       const struct img_ir_decoder *dec)
0628 {
0629     unsigned int ct;
0630 
0631     /* don't accept decoders using code types which aren't supported */
0632     ct = dec->control.code_type;
0633     if (priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_BROKEN)
0634         return false;
0635 
0636     return true;
0637 }
0638 
0639 /**
0640  * img_ir_allowed_protos() - Get allowed protocols from global decoder list.
0641  * @priv:   IR private data.
0642  *
0643  * Returns: Mask of protocols supported by the device @priv refers to.
0644  */
0645 static u64 img_ir_allowed_protos(struct img_ir_priv *priv)
0646 {
0647     u64 protos = 0;
0648     struct img_ir_decoder **decp;
0649 
0650     for (decp = img_ir_decoders; *decp; ++decp) {
0651         const struct img_ir_decoder *dec = *decp;
0652         if (img_ir_decoder_compatible(priv, dec))
0653             protos |= dec->type;
0654     }
0655     return protos;
0656 }
0657 
0658 /* Callback for changing protocol using sysfs */
0659 static int img_ir_change_protocol(struct rc_dev *dev, u64 *ir_type)
0660 {
0661     struct img_ir_priv *priv = dev->priv;
0662     struct img_ir_priv_hw *hw = &priv->hw;
0663     struct rc_dev *rdev = hw->rdev;
0664     struct img_ir_decoder **decp;
0665     u64 wakeup_protocols;
0666 
0667     if (!*ir_type) {
0668         /* disable all protocols */
0669         img_ir_set_decoder(priv, NULL, 0);
0670         goto success;
0671     }
0672     for (decp = img_ir_decoders; *decp; ++decp) {
0673         const struct img_ir_decoder *dec = *decp;
0674         if (!img_ir_decoder_compatible(priv, dec))
0675             continue;
0676         if (*ir_type & dec->type) {
0677             *ir_type &= dec->type;
0678             img_ir_set_decoder(priv, dec, *ir_type);
0679             goto success;
0680         }
0681     }
0682     return -EINVAL;
0683 
0684 success:
0685     /*
0686      * Only allow matching wakeup protocols for now, and only if filtering
0687      * is supported.
0688      */
0689     wakeup_protocols = *ir_type;
0690     if (!hw->decoder || !hw->decoder->filter)
0691         wakeup_protocols = 0;
0692     rdev->allowed_wakeup_protocols = wakeup_protocols;
0693     return 0;
0694 }
0695 
0696 /* Changes ir-core protocol device attribute */
0697 static void img_ir_set_protocol(struct img_ir_priv *priv, u64 proto)
0698 {
0699     struct rc_dev *rdev = priv->hw.rdev;
0700 
0701     mutex_lock(&rdev->lock);
0702     rdev->enabled_protocols = proto;
0703     rdev->allowed_wakeup_protocols = proto;
0704     mutex_unlock(&rdev->lock);
0705 }
0706 
0707 /* Set up IR decoders */
0708 static void img_ir_init_decoders(void)
0709 {
0710     struct img_ir_decoder **decp;
0711 
0712     spin_lock(&img_ir_decoders_lock);
0713     if (!img_ir_decoders_preprocessed) {
0714         for (decp = img_ir_decoders; *decp; ++decp)
0715             img_ir_decoder_preprocess(*decp);
0716         img_ir_decoders_preprocessed = true;
0717     }
0718     spin_unlock(&img_ir_decoders_lock);
0719 }
0720 
0721 #ifdef CONFIG_PM_SLEEP
0722 /**
0723  * img_ir_enable_wake() - Switch to wake mode.
0724  * @priv:   IR private data.
0725  *
0726  * Returns: non-zero if the IR can wake the system.
0727  */
0728 static int img_ir_enable_wake(struct img_ir_priv *priv)
0729 {
0730     struct img_ir_priv_hw *hw = &priv->hw;
0731     int ret = 0;
0732 
0733     spin_lock_irq(&priv->lock);
0734     if (hw->flags & IMG_IR_F_WAKE) {
0735         /* interrupt only on a match */
0736         hw->suspend_irqen = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
0737         img_ir_write(priv, IMG_IR_IRQ_ENABLE, IMG_IR_IRQ_DATA_MATCH);
0738         img_ir_write_filter(priv, &hw->filters[RC_FILTER_WAKEUP]);
0739         img_ir_write_timings(priv, &hw->reg_timings.timings,
0740                      RC_FILTER_WAKEUP);
0741         hw->mode = IMG_IR_M_WAKE;
0742         ret = 1;
0743     }
0744     spin_unlock_irq(&priv->lock);
0745     return ret;
0746 }
0747 
0748 /**
0749  * img_ir_disable_wake() - Switch out of wake mode.
0750  * @priv:   IR private data
0751  *
0752  * Returns: 1 if the hardware should be allowed to wake from a sleep state.
0753  *      0 otherwise.
0754  */
0755 static int img_ir_disable_wake(struct img_ir_priv *priv)
0756 {
0757     struct img_ir_priv_hw *hw = &priv->hw;
0758     int ret = 0;
0759 
0760     spin_lock_irq(&priv->lock);
0761     if (hw->flags & IMG_IR_F_WAKE) {
0762         /* restore normal filtering */
0763         if (hw->flags & IMG_IR_F_FILTER) {
0764             img_ir_write(priv, IMG_IR_IRQ_ENABLE,
0765                      (hw->suspend_irqen & IMG_IR_IRQ_EDGE) |
0766                      IMG_IR_IRQ_DATA_MATCH);
0767             img_ir_write_filter(priv,
0768                         &hw->filters[RC_FILTER_NORMAL]);
0769         } else {
0770             img_ir_write(priv, IMG_IR_IRQ_ENABLE,
0771                      (hw->suspend_irqen & IMG_IR_IRQ_EDGE) |
0772                      IMG_IR_IRQ_DATA_VALID |
0773                      IMG_IR_IRQ_DATA2_VALID);
0774             img_ir_write_filter(priv, NULL);
0775         }
0776         img_ir_write_timings(priv, &hw->reg_timings.timings,
0777                      RC_FILTER_NORMAL);
0778         hw->mode = IMG_IR_M_NORMAL;
0779         ret = 1;
0780     }
0781     spin_unlock_irq(&priv->lock);
0782     return ret;
0783 }
0784 #endif /* CONFIG_PM_SLEEP */
0785 
0786 /* lock must be held */
0787 static void img_ir_begin_repeat(struct img_ir_priv *priv)
0788 {
0789     struct img_ir_priv_hw *hw = &priv->hw;
0790     if (hw->mode == IMG_IR_M_NORMAL) {
0791         /* switch to repeat timings */
0792         img_ir_write(priv, IMG_IR_CONTROL, 0);
0793         hw->mode = IMG_IR_M_REPEATING;
0794         img_ir_write_timings(priv, &hw->reg_timings.rtimings,
0795                      RC_FILTER_NORMAL);
0796         img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
0797     }
0798 }
0799 
0800 /* lock must be held */
0801 static void img_ir_end_repeat(struct img_ir_priv *priv)
0802 {
0803     struct img_ir_priv_hw *hw = &priv->hw;
0804     if (hw->mode == IMG_IR_M_REPEATING) {
0805         /* switch to normal timings */
0806         img_ir_write(priv, IMG_IR_CONTROL, 0);
0807         hw->mode = IMG_IR_M_NORMAL;
0808         img_ir_write_timings(priv, &hw->reg_timings.timings,
0809                      RC_FILTER_NORMAL);
0810         img_ir_write(priv, IMG_IR_CONTROL, hw->reg_timings.ctrl);
0811     }
0812 }
0813 
0814 /* lock must be held */
0815 static void img_ir_handle_data(struct img_ir_priv *priv, u32 len, u64 raw)
0816 {
0817     struct img_ir_priv_hw *hw = &priv->hw;
0818     const struct img_ir_decoder *dec = hw->decoder;
0819     int ret = IMG_IR_SCANCODE;
0820     struct img_ir_scancode_req request;
0821 
0822     request.protocol = RC_PROTO_UNKNOWN;
0823     request.toggle   = 0;
0824 
0825     if (dec->scancode)
0826         ret = dec->scancode(len, raw, hw->enabled_protocols, &request);
0827     else if (len >= 32)
0828         request.scancode = (u32)raw;
0829     else if (len < 32)
0830         request.scancode = (u32)raw & ((1 << len)-1);
0831     dev_dbg(priv->dev, "data (%u bits) = %#llx\n",
0832         len, (unsigned long long)raw);
0833     if (ret == IMG_IR_SCANCODE) {
0834         dev_dbg(priv->dev, "decoded scan code %#x, toggle %u\n",
0835             request.scancode, request.toggle);
0836         rc_keydown(hw->rdev, request.protocol, request.scancode,
0837                request.toggle);
0838         img_ir_end_repeat(priv);
0839     } else if (ret == IMG_IR_REPEATCODE) {
0840         if (hw->mode == IMG_IR_M_REPEATING) {
0841             dev_dbg(priv->dev, "decoded repeat code\n");
0842             rc_repeat(hw->rdev);
0843         } else {
0844             dev_dbg(priv->dev, "decoded unexpected repeat code, ignoring\n");
0845         }
0846     } else {
0847         dev_dbg(priv->dev, "decode failed (%d)\n", ret);
0848         return;
0849     }
0850 
0851 
0852     /* we mustn't update the end timer while trying to stop it */
0853     if (dec->repeat && !hw->stopping) {
0854         unsigned long interval;
0855 
0856         img_ir_begin_repeat(priv);
0857 
0858         /* update timer, but allowing for 1/8th tolerance */
0859         interval = dec->repeat + (dec->repeat >> 3);
0860         mod_timer(&hw->end_timer,
0861               jiffies + msecs_to_jiffies(interval));
0862     }
0863 }
0864 
0865 /* timer function to end waiting for repeat. */
0866 static void img_ir_end_timer(struct timer_list *t)
0867 {
0868     struct img_ir_priv *priv = from_timer(priv, t, hw.end_timer);
0869 
0870     spin_lock_irq(&priv->lock);
0871     img_ir_end_repeat(priv);
0872     spin_unlock_irq(&priv->lock);
0873 }
0874 
0875 /*
0876  * Timer function to re-enable the current protocol after it had been
0877  * cleared when invalid interrupts were generated due to a quirk in the
0878  * img-ir decoder.
0879  */
0880 static void img_ir_suspend_timer(struct timer_list *t)
0881 {
0882     struct img_ir_priv *priv = from_timer(priv, t, hw.suspend_timer);
0883 
0884     spin_lock_irq(&priv->lock);
0885     /*
0886      * Don't overwrite enabled valid/match IRQs if they have already been
0887      * changed by e.g. a filter change.
0888      */
0889     if ((priv->hw.quirk_suspend_irq & IMG_IR_IRQ_EDGE) ==
0890                 img_ir_read(priv, IMG_IR_IRQ_ENABLE))
0891         img_ir_write(priv, IMG_IR_IRQ_ENABLE,
0892                     priv->hw.quirk_suspend_irq);
0893     /* enable */
0894     img_ir_write(priv, IMG_IR_CONTROL, priv->hw.reg_timings.ctrl);
0895     spin_unlock_irq(&priv->lock);
0896 }
0897 
0898 #ifdef CONFIG_COMMON_CLK
0899 static void img_ir_change_frequency(struct img_ir_priv *priv,
0900                     struct clk_notifier_data *change)
0901 {
0902     struct img_ir_priv_hw *hw = &priv->hw;
0903 
0904     dev_dbg(priv->dev, "clk changed %lu HZ -> %lu HZ\n",
0905         change->old_rate, change->new_rate);
0906 
0907     spin_lock_irq(&priv->lock);
0908     if (hw->clk_hz == change->new_rate)
0909         goto unlock;
0910     hw->clk_hz = change->new_rate;
0911     /* refresh current timings */
0912     if (hw->decoder) {
0913         img_ir_decoder_convert(hw->decoder, &hw->reg_timings,
0914                        hw->clk_hz);
0915         switch (hw->mode) {
0916         case IMG_IR_M_NORMAL:
0917             img_ir_write_timings(priv, &hw->reg_timings.timings,
0918                          RC_FILTER_NORMAL);
0919             break;
0920         case IMG_IR_M_REPEATING:
0921             img_ir_write_timings(priv, &hw->reg_timings.rtimings,
0922                          RC_FILTER_NORMAL);
0923             break;
0924 #ifdef CONFIG_PM_SLEEP
0925         case IMG_IR_M_WAKE:
0926             img_ir_write_timings(priv, &hw->reg_timings.timings,
0927                          RC_FILTER_WAKEUP);
0928             break;
0929 #endif
0930         }
0931     }
0932 unlock:
0933     spin_unlock_irq(&priv->lock);
0934 }
0935 
0936 static int img_ir_clk_notify(struct notifier_block *self, unsigned long action,
0937                  void *data)
0938 {
0939     struct img_ir_priv *priv = container_of(self, struct img_ir_priv,
0940                         hw.clk_nb);
0941     switch (action) {
0942     case POST_RATE_CHANGE:
0943         img_ir_change_frequency(priv, data);
0944         break;
0945     default:
0946         break;
0947     }
0948     return NOTIFY_OK;
0949 }
0950 #endif /* CONFIG_COMMON_CLK */
0951 
0952 /* called with priv->lock held */
0953 void img_ir_isr_hw(struct img_ir_priv *priv, u32 irq_status)
0954 {
0955     struct img_ir_priv_hw *hw = &priv->hw;
0956     u32 ir_status, len, lw, up;
0957     unsigned int ct;
0958 
0959     /* use the current decoder */
0960     if (!hw->decoder)
0961         return;
0962 
0963     ct = hw->decoder->control.code_type;
0964 
0965     ir_status = img_ir_read(priv, IMG_IR_STATUS);
0966     if (!(ir_status & (IMG_IR_RXDVAL | IMG_IR_RXDVALD2))) {
0967         if (!(priv->hw.ct_quirks[ct] & IMG_IR_QUIRK_CODE_IRQ) ||
0968                 hw->stopping)
0969             return;
0970         /*
0971          * The below functionality is added as a work around to stop
0972          * multiple Interrupts generated when an incomplete IR code is
0973          * received by the decoder.
0974          * The decoder generates rapid interrupts without actually
0975          * having received any new data. After a single interrupt it's
0976          * expected to clear up, but instead multiple interrupts are
0977          * rapidly generated. only way to get out of this loop is to
0978          * reset the control register after a short delay.
0979          */
0980         img_ir_write(priv, IMG_IR_CONTROL, 0);
0981         hw->quirk_suspend_irq = img_ir_read(priv, IMG_IR_IRQ_ENABLE);
0982         img_ir_write(priv, IMG_IR_IRQ_ENABLE,
0983                  hw->quirk_suspend_irq & IMG_IR_IRQ_EDGE);
0984 
0985         /* Timer activated to re-enable the protocol. */
0986         mod_timer(&hw->suspend_timer,
0987               jiffies + msecs_to_jiffies(5));
0988         return;
0989     }
0990     ir_status &= ~(IMG_IR_RXDVAL | IMG_IR_RXDVALD2);
0991     img_ir_write(priv, IMG_IR_STATUS, ir_status);
0992 
0993     len = (ir_status & IMG_IR_RXDLEN) >> IMG_IR_RXDLEN_SHIFT;
0994     /* some versions report wrong length for certain code types */
0995     if (hw->ct_quirks[ct] & IMG_IR_QUIRK_CODE_LEN_INCR)
0996         ++len;
0997 
0998     lw = img_ir_read(priv, IMG_IR_DATA_LW);
0999     up = img_ir_read(priv, IMG_IR_DATA_UP);
1000     img_ir_handle_data(priv, len, (u64)up << 32 | lw);
1001 }
1002 
1003 void img_ir_setup_hw(struct img_ir_priv *priv)
1004 {
1005     struct img_ir_decoder **decp;
1006 
1007     if (!priv->hw.rdev)
1008         return;
1009 
1010     /* Use the first available decoder (or disable stuff if NULL) */
1011     for (decp = img_ir_decoders; *decp; ++decp) {
1012         const struct img_ir_decoder *dec = *decp;
1013         if (img_ir_decoder_compatible(priv, dec)) {
1014             img_ir_set_protocol(priv, dec->type);
1015             img_ir_set_decoder(priv, dec, 0);
1016             return;
1017         }
1018     }
1019     img_ir_set_decoder(priv, NULL, 0);
1020 }
1021 
1022 /**
1023  * img_ir_probe_hw_caps() - Probe capabilities of the hardware.
1024  * @priv:   IR private data.
1025  */
1026 static void img_ir_probe_hw_caps(struct img_ir_priv *priv)
1027 {
1028     struct img_ir_priv_hw *hw = &priv->hw;
1029     /*
1030      * When a version of the block becomes available without these quirks,
1031      * they'll have to depend on the core revision.
1032      */
1033     hw->ct_quirks[IMG_IR_CODETYPE_PULSELEN]
1034         |= IMG_IR_QUIRK_CODE_LEN_INCR;
1035     hw->ct_quirks[IMG_IR_CODETYPE_BIPHASE]
1036         |= IMG_IR_QUIRK_CODE_IRQ;
1037     hw->ct_quirks[IMG_IR_CODETYPE_2BITPULSEPOS]
1038         |= IMG_IR_QUIRK_CODE_BROKEN;
1039 }
1040 
1041 int img_ir_probe_hw(struct img_ir_priv *priv)
1042 {
1043     struct img_ir_priv_hw *hw = &priv->hw;
1044     struct rc_dev *rdev;
1045     int error;
1046 
1047     /* Ensure hardware decoders have been preprocessed */
1048     img_ir_init_decoders();
1049 
1050     /* Probe hardware capabilities */
1051     img_ir_probe_hw_caps(priv);
1052 
1053     /* Set up the end timer */
1054     timer_setup(&hw->end_timer, img_ir_end_timer, 0);
1055     timer_setup(&hw->suspend_timer, img_ir_suspend_timer, 0);
1056 
1057     /* Register a clock notifier */
1058     if (!IS_ERR(priv->clk)) {
1059         hw->clk_hz = clk_get_rate(priv->clk);
1060 #ifdef CONFIG_COMMON_CLK
1061         hw->clk_nb.notifier_call = img_ir_clk_notify;
1062         error = clk_notifier_register(priv->clk, &hw->clk_nb);
1063         if (error)
1064             dev_warn(priv->dev,
1065                  "failed to register clock notifier\n");
1066 #endif
1067     } else {
1068         hw->clk_hz = 32768;
1069     }
1070 
1071     /* Allocate hardware decoder */
1072     hw->rdev = rdev = rc_allocate_device(RC_DRIVER_SCANCODE);
1073     if (!rdev) {
1074         dev_err(priv->dev, "cannot allocate input device\n");
1075         error = -ENOMEM;
1076         goto err_alloc_rc;
1077     }
1078     rdev->priv = priv;
1079     rdev->map_name = RC_MAP_EMPTY;
1080     rdev->allowed_protocols = img_ir_allowed_protos(priv);
1081     rdev->device_name = "IMG Infrared Decoder";
1082     rdev->s_filter = img_ir_set_normal_filter;
1083     rdev->s_wakeup_filter = img_ir_set_wakeup_filter;
1084 
1085     /* Register hardware decoder */
1086     error = rc_register_device(rdev);
1087     if (error) {
1088         dev_err(priv->dev, "failed to register IR input device\n");
1089         goto err_register_rc;
1090     }
1091 
1092     /*
1093      * Set this after rc_register_device as no protocols have been
1094      * registered yet.
1095      */
1096     rdev->change_protocol = img_ir_change_protocol;
1097 
1098     device_init_wakeup(priv->dev, 1);
1099 
1100     return 0;
1101 
1102 err_register_rc:
1103     img_ir_set_decoder(priv, NULL, 0);
1104     hw->rdev = NULL;
1105     rc_free_device(rdev);
1106 err_alloc_rc:
1107 #ifdef CONFIG_COMMON_CLK
1108     if (!IS_ERR(priv->clk))
1109         clk_notifier_unregister(priv->clk, &hw->clk_nb);
1110 #endif
1111     return error;
1112 }
1113 
1114 void img_ir_remove_hw(struct img_ir_priv *priv)
1115 {
1116     struct img_ir_priv_hw *hw = &priv->hw;
1117     struct rc_dev *rdev = hw->rdev;
1118     if (!rdev)
1119         return;
1120     img_ir_set_decoder(priv, NULL, 0);
1121     hw->rdev = NULL;
1122     rc_unregister_device(rdev);
1123 #ifdef CONFIG_COMMON_CLK
1124     if (!IS_ERR(priv->clk))
1125         clk_notifier_unregister(priv->clk, &hw->clk_nb);
1126 #endif
1127 }
1128 
1129 #ifdef CONFIG_PM_SLEEP
1130 int img_ir_suspend(struct device *dev)
1131 {
1132     struct img_ir_priv *priv = dev_get_drvdata(dev);
1133 
1134     if (device_may_wakeup(dev) && img_ir_enable_wake(priv))
1135         enable_irq_wake(priv->irq);
1136     return 0;
1137 }
1138 
1139 int img_ir_resume(struct device *dev)
1140 {
1141     struct img_ir_priv *priv = dev_get_drvdata(dev);
1142 
1143     if (device_may_wakeup(dev) && img_ir_disable_wake(priv))
1144         disable_irq_wake(priv->irq);
1145     return 0;
1146 }
1147 #endif  /* CONFIG_PM_SLEEP */
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!