media/rc/fintek-cir.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Driver for Feature Integration Technology Inc. (aka Fintek) LPC CIR
0004  *
0005  * Copyright (C) 2011 Jarod Wilson <jarod@redhat.com>
0006  *
0007  * Special thanks to Fintek for providing hardware and spec sheets.
0008  * This driver is based upon the nuvoton, ite and ene drivers for
0009  * similar hardware.
0010  */
0011
0012 #include <linux/spinlock.h>
0013 #include <linux/ioctl.h>
0014
0015 /* platform driver name to register */
0016 #define FINTEK_DRIVER_NAME  "fintek-cir"
0017 #define FINTEK_DESCRIPTION  "Fintek LPC SuperIO Consumer IR Transceiver"
0018 #define VENDOR_ID_FINTEK    0x1934
0019
0020
0021 /* debugging module parameter */
0022 static int debug;
0023
0024 #define fit_pr(level, text, ...) \
0025     printk(level KBUILD_MODNAME ": " text, ## __VA_ARGS__)
0026
0027 #define fit_dbg(text, ...) \
0028     if (debug) \
0029         printk(KERN_DEBUG \
0030             KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
0031
0032 #define fit_dbg_verbose(text, ...) \
0033     if (debug > 1) \
0034         printk(KERN_DEBUG \
0035             KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
0036
0037 #define fit_dbg_wake(text, ...) \
0038     if (debug > 2) \
0039         printk(KERN_DEBUG \
0040             KBUILD_MODNAME ": " text "\n" , ## __VA_ARGS__)
0041
0042
0043 #define TX_BUF_LEN 256
0044 #define RX_BUF_LEN 32
0045
0046 struct fintek_dev {
0047     struct pnp_dev *pdev;
0048     struct rc_dev *rdev;
0049
0050     spinlock_t fintek_lock;
0051
0052     /* for rx */
0053     u8 buf[RX_BUF_LEN];
0054     unsigned int pkts;
0055
0056     struct {
0057         spinlock_t lock;
0058         u8 buf[TX_BUF_LEN];
0059         unsigned int buf_count;
0060         unsigned int cur_buf_num;
0061         wait_queue_head_t queue;
0062     } tx;
0063
0064     /* Config register index/data port pair */
0065     u32 cr_ip;
0066     u32 cr_dp;
0067
0068     /* hardware I/O settings */
0069     unsigned long cir_addr;
0070     int cir_irq;
0071     int cir_port_len;
0072
0073     /* hardware id */
0074     u8 chip_major;
0075     u8 chip_minor;
0076     u16 chip_vendor;
0077     u8 logical_dev_cir;
0078
0079     /* hardware features */
0080     bool hw_learning_capable;
0081     bool hw_tx_capable;
0082
0083     /* rx settings */
0084     bool learning_enabled;
0085     bool carrier_detect_enabled;
0086
0087     enum {
0088         CMD_HEADER = 0,
0089         SUBCMD,
0090         CMD_DATA,
0091         PARSE_IRDATA,
0092     } parser_state;
0093
0094     u8 cmd, rem;
0095
0096     /* carrier period = 1 / frequency */
0097     u32 carrier;
0098 };
0099
0100 /* buffer packet constants, largely identical to mceusb.c */
0101 #define BUF_PULSE_BIT       0x80
0102 #define BUF_LEN_MASK        0x1f
0103 #define BUF_SAMPLE_MASK     0x7f
0104
0105 #define BUF_COMMAND_HEADER  0x9f
0106 #define BUF_COMMAND_MASK    0xe0
0107 #define BUF_COMMAND_NULL    0x00
0108 #define BUF_HW_CMD_HEADER   0xff
0109 #define BUF_CMD_G_REVISION  0x0b
0110 #define BUF_CMD_S_CARRIER   0x06
0111 #define BUF_CMD_S_TIMEOUT   0x0c
0112 #define BUF_CMD_SIG_END     0x01
0113 #define BUF_CMD_S_TXMASK    0x08
0114 #define BUF_CMD_S_RXSENSOR  0x14
0115 #define BUF_RSP_PULSE_COUNT 0x15
0116
0117 #define CIR_SAMPLE_PERIOD   50
0118
0119 /*
0120  * Configuration Register:
0121  *  Index Port
0122  *  Data Port
0123  */
0124 #define CR_INDEX_PORT       0x2e
0125 #define CR_DATA_PORT        0x2f
0126
0127 /* Possible alternate values, depends on how the chip is wired */
0128 #define CR_INDEX_PORT2      0x4e
0129 #define CR_DATA_PORT2       0x4f
0130
0131 /*
0132  * GCR_CONFIG_PORT_SEL bit 4 specifies which Index Port value is
0133  * active. 1 = 0x4e, 0 = 0x2e
0134  */
0135 #define PORT_SEL_PORT_4E_EN 0x10
0136
0137 /* Extended Function Mode enable/disable magic values */
0138 #define CONFIG_REG_ENABLE   0x87
0139 #define CONFIG_REG_DISABLE  0xaa
0140
0141 /* Chip IDs found in CR_CHIP_ID_{HI,LO} */
0142 #define CHIP_ID_HIGH_F71809U    0x04
0143 #define CHIP_ID_LOW_F71809U 0x08
0144
0145 /*
0146  * Global control regs we need to care about:
0147  *      Global Control                  def.
0148  *      Register name           addr    val. */
0149 #define GCR_SOFTWARE_RESET  0x02 /* 0x00 */
0150 #define GCR_LOGICAL_DEV_NO  0x07 /* 0x00 */
0151 #define GCR_CHIP_ID_HI      0x20 /* 0x04 */
0152 #define GCR_CHIP_ID_LO      0x21 /* 0x08 */
0153 #define GCR_VENDOR_ID_HI    0x23 /* 0x19 */
0154 #define GCR_VENDOR_ID_LO    0x24 /* 0x34 */
0155 #define GCR_CONFIG_PORT_SEL 0x25 /* 0x01 */
0156 #define GCR_KBMOUSE_WAKEUP  0x27
0157
0158 #define LOGICAL_DEV_DISABLE 0x00
0159 #define LOGICAL_DEV_ENABLE  0x01
0160
0161 /* Logical device number of the CIR function */
0162 #define LOGICAL_DEV_CIR_REV1    0x05
0163 #define LOGICAL_DEV_CIR_REV2    0x08
0164
0165 /* CIR Logical Device (LDN 0x08) config registers */
0166 #define CIR_CR_COMMAND_INDEX    0x04
0167 #define CIR_CR_IRCS     0x05 /* Before host writes command to IR, host
0168                     must set to 1. When host finshes write
0169                     command to IR, host must clear to 0. */
0170 #define CIR_CR_COMMAND_DATA 0x06 /* Host read or write command data */
0171 #define CIR_CR_CLASS        0x07 /* 0xff = rx-only, 0x66 = rx + 2 tx,
0172                     0x33 = rx + 1 tx */
0173 #define CIR_CR_DEV_EN       0x30 /* bit0 = 1 enables CIR */
0174 #define CIR_CR_BASE_ADDR_HI 0x60 /* MSB of CIR IO base addr */
0175 #define CIR_CR_BASE_ADDR_LO 0x61 /* LSB of CIR IO base addr */
0176 #define CIR_CR_IRQ_SEL      0x70 /* bits3-0 store CIR IRQ */
0177 #define CIR_CR_PSOUT_STATUS 0xf1
0178 #define CIR_CR_WAKE_KEY3_ADDR   0xf8
0179 #define CIR_CR_WAKE_KEY3_CODE   0xf9
0180 #define CIR_CR_WAKE_KEY3_DC 0xfa
0181 #define CIR_CR_WAKE_CONTROL 0xfb
0182 #define CIR_CR_WAKE_KEY12_ADDR  0xfc
0183 #define CIR_CR_WAKE_KEY4_ADDR   0xfd
0184 #define CIR_CR_WAKE_KEY5_ADDR   0xfe
0185
0186 #define CLASS_RX_ONLY       0xff
0187 #define CLASS_RX_2TX        0x66
0188 #define CLASS_RX_1TX        0x33
0189
0190 /* CIR device registers */
0191 #define CIR_STATUS      0x00
0192 #define CIR_RX_DATA     0x01
0193 #define CIR_TX_CONTROL      0x02
0194 #define CIR_TX_DATA     0x03
0195 #define CIR_CONTROL     0x04
0196
0197 /* Bits to enable CIR wake */
0198 #define LOGICAL_DEV_ACPI    0x01
0199 #define LDEV_ACPI_WAKE_EN_REG   0xe8
0200 #define ACPI_WAKE_EN_CIR_BIT    0x04
0201
0202 #define LDEV_ACPI_PME_EN_REG    0xf0
0203 #define LDEV_ACPI_PME_CLR_REG   0xf1
0204 #define ACPI_PME_CIR_BIT    0x02
0205
0206 #define LDEV_ACPI_STATE_REG 0xf4
0207 #define ACPI_STATE_CIR_BIT  0x20
0208
0209 /*
0210  * CIR status register (0x00):
0211  *   7 - CIR_IRQ_EN (1 = enable CIR IRQ, 0 = disable)
0212  *   3 - TX_FINISH (1 when TX finished, write 1 to clear)
0213  *   2 - TX_UNDERRUN (1 on TX underrun, write 1 to clear)
0214  *   1 - RX_TIMEOUT (1 on RX timeout, write 1 to clear)
0215  *   0 - RX_RECEIVE (1 on RX receive, write 1 to clear)
0216  */
0217 #define CIR_STATUS_IRQ_EN   0x80
0218 #define CIR_STATUS_TX_FINISH    0x08
0219 #define CIR_STATUS_TX_UNDERRUN  0x04
0220 #define CIR_STATUS_RX_TIMEOUT   0x02
0221 #define CIR_STATUS_RX_RECEIVE   0x01
0222 #define CIR_STATUS_IRQ_MASK 0x0f
0223
0224 /*
0225  * CIR TX control register (0x02):
0226  *   7 - TX_START (1 to indicate TX start, auto-cleared when done)
0227  *   6 - TX_END (1 to indicate TX data written to TX fifo)
0228  */
0229 #define CIR_TX_CONTROL_TX_START 0x80
0230 #define CIR_TX_CONTROL_TX_END   0x40
0231