media/rc/ene_ir.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * driver for ENE KB3926 B/C/D/E/F CIR (also known as ENE0XXX)
0004  *
0005  * Copyright (C) 2010 Maxim Levitsky <maximlevitsky@gmail.com>
0006  */
0007 #include <linux/spinlock.h>
0008
0009
0010 /* hardware address */
0011 #define ENE_STATUS      0   /* hardware status - unused */
0012 #define ENE_ADDR_HI     1   /* hi byte of register address */
0013 #define ENE_ADDR_LO     2   /* low byte of register address */
0014 #define ENE_IO          3   /* read/write window */
0015 #define ENE_IO_SIZE     4
0016
0017 /* 8 bytes of samples, divided in 2 packets*/
0018 #define ENE_FW_SAMPLE_BUFFER    0xF8F0  /* sample buffer */
0019 #define ENE_FW_SAMPLE_SPACE 0x80    /* sample is space */
0020 #define ENE_FW_PACKET_SIZE  4
0021
0022 /* first firmware flag register */
0023 #define ENE_FW1         0xF8F8  /* flagr */
0024 #define ENE_FW1_ENABLE      0x01    /* enable fw processing */
0025 #define ENE_FW1_TXIRQ       0x02    /* TX interrupt pending */
0026 #define ENE_FW1_HAS_EXTRA_BUF   0x04    /* fw uses extra buffer*/
0027 #define ENE_FW1_EXTRA_BUF_HND   0x08    /* extra buffer handshake bit*/
0028 #define ENE_FW1_LED_ON      0x10    /* turn on a led */
0029
0030 #define ENE_FW1_WPATTERN    0x20    /* enable wake pattern */
0031 #define ENE_FW1_WAKE        0x40    /* enable wake from S3 */
0032 #define ENE_FW1_IRQ     0x80    /* enable interrupt */
0033
0034 /* second firmware flag register */
0035 #define ENE_FW2         0xF8F9  /* flagw */
0036 #define ENE_FW2_BUF_WPTR    0x01    /* which half of the buffer to read */
0037 #define ENE_FW2_RXIRQ       0x04    /* RX IRQ pending*/
0038 #define ENE_FW2_GP0A        0x08    /* Use GPIO0A for demodulated input */
0039 #define ENE_FW2_EMMITER1_CONN   0x10    /* TX emmiter 1 connected */
0040 #define ENE_FW2_EMMITER2_CONN   0x20    /* TX emmiter 2 connected */
0041
0042 #define ENE_FW2_FAN_INPUT   0x40    /* fan input used for demodulated data*/
0043 #define ENE_FW2_LEARNING    0x80    /* hardware supports learning and TX */
0044
0045 /* firmware RX pointer for new style buffer */
0046 #define ENE_FW_RX_POINTER   0xF8FA
0047
0048 /* high parts of samples for fan input (8 samples)*/
0049 #define ENE_FW_SMPL_BUF_FAN 0xF8FB
0050 #define ENE_FW_SMPL_BUF_FAN_PLS 0x8000  /* combined sample is pulse */
0051 #define ENE_FW_SMPL_BUF_FAN_MSK 0x0FFF  /* combined sample maximum value */
0052 #define ENE_FW_SAMPLE_PERIOD_FAN 61 /* fan input has fixed sample period */
0053
0054 /* transmitter ports */
0055 #define ENE_GPIOFS1     0xFC01
0056 #define ENE_GPIOFS1_GPIO0D  0x20    /* enable tx output on GPIO0D */
0057 #define ENE_GPIOFS8     0xFC08
0058 #define ENE_GPIOFS8_GPIO41  0x02    /* enable tx output on GPIO40 */
0059
0060 /* IRQ registers block (for revision B) */
0061 #define ENEB_IRQ        0xFD09  /* IRQ number */
0062 #define ENEB_IRQ_UNK1       0xFD17  /* unknown setting = 1 */
0063 #define ENEB_IRQ_STATUS     0xFD80  /* irq status */
0064 #define ENEB_IRQ_STATUS_IR  0x20    /* IR irq */
0065
0066 /* fan as input settings */
0067 #define ENE_FAN_AS_IN1      0xFE30  /* fan init reg 1 */
0068 #define ENE_FAN_AS_IN1_EN   0xCD
0069 #define ENE_FAN_AS_IN2      0xFE31  /* fan init reg 2 */
0070 #define ENE_FAN_AS_IN2_EN   0x03
0071
0072 /* IRQ registers block (for revision C,D) */
0073 #define ENE_IRQ         0xFE9B  /* new irq settings register */
0074 #define ENE_IRQ_MASK        0x0F    /* irq number mask */
0075 #define ENE_IRQ_UNK_EN      0x10    /* always enabled */
0076 #define ENE_IRQ_STATUS      0x20    /* irq status and ACK */
0077
0078 /* CIR Config register #1 */
0079 #define ENE_CIRCFG      0xFEC0
0080 #define ENE_CIRCFG_RX_EN    0x01    /* RX enable */
0081 #define ENE_CIRCFG_RX_IRQ   0x02    /* Enable hardware interrupt */
0082 #define ENE_CIRCFG_REV_POL  0x04    /* Input polarity reversed */
0083 #define ENE_CIRCFG_CARR_DEMOD   0x08    /* Enable carrier demodulator */
0084
0085 #define ENE_CIRCFG_TX_EN    0x10    /* TX enable */
0086 #define ENE_CIRCFG_TX_IRQ   0x20    /* Send interrupt on TX done */
0087 #define ENE_CIRCFG_TX_POL_REV   0x40    /* TX polarity reversed */
0088 #define ENE_CIRCFG_TX_CARR  0x80    /* send TX carrier or not */
0089
0090 /* CIR config register #2 */
0091 #define ENE_CIRCFG2     0xFEC1
0092 #define ENE_CIRCFG2_RLC     0x00
0093 #define ENE_CIRCFG2_RC5     0x01
0094 #define ENE_CIRCFG2_RC6     0x02
0095 #define ENE_CIRCFG2_NEC     0x03
0096 #define ENE_CIRCFG2_CARR_DETECT 0x10    /* Enable carrier detection */
0097 #define ENE_CIRCFG2_GPIO0A  0x20    /* Use GPIO0A instead of GPIO40 for input */
0098 #define ENE_CIRCFG2_FAST_SAMPL1 0x40    /* Fast leading pulse detection for RC6 */
0099 #define ENE_CIRCFG2_FAST_SAMPL2 0x80    /* Fast data detection for RC6 */
0100
0101 /* Knobs for protocol decoding - will document when/if will use them */
0102 #define ENE_CIRPF       0xFEC2
0103 #define ENE_CIRHIGH     0xFEC3
0104 #define ENE_CIRBIT      0xFEC4
0105 #define ENE_CIRSTART        0xFEC5
0106 #define ENE_CIRSTART2       0xFEC6
0107
0108 /* Actual register which contains RLC RX data - read by firmware */
0109 #define ENE_CIRDAT_IN       0xFEC7
0110
0111
0112 /* RLC configuration - sample period (1us resolution) + idle mode */
0113 #define ENE_CIRRLC_CFG      0xFEC8
0114 #define ENE_CIRRLC_CFG_OVERFLOW 0x80    /* interrupt on overflows if set */
0115 #define ENE_DEFAULT_SAMPLE_PERIOD 50
0116
0117 /* Two byte RLC TX buffer */
0118 #define ENE_CIRRLC_OUT0     0xFEC9
0119 #define ENE_CIRRLC_OUT1     0xFECA
0120 #define ENE_CIRRLC_OUT_PULSE    0x80    /* Transmitted sample is pulse */
0121 #define ENE_CIRRLC_OUT_MASK 0x7F
0122
0123
0124 /* Carrier detect setting
0125  * Low nibble  - number of carrier pulses to average
0126  * High nibble - number of initial carrier pulses to discard
0127  */
0128 #define ENE_CIRCAR_PULS     0xFECB
0129
0130 /* detected RX carrier period (resolution: 500 ns) */
0131 #define ENE_CIRCAR_PRD      0xFECC
0132 #define ENE_CIRCAR_PRD_VALID    0x80    /* data valid content valid */
0133
0134 /* detected RX carrier pulse width (resolution: 500 ns) */
0135 #define ENE_CIRCAR_HPRD     0xFECD
0136
0137 /* TX period (resolution: 500 ns, minimum 2)*/
0138 #define ENE_CIRMOD_PRD      0xFECE
0139 #define ENE_CIRMOD_PRD_POL  0x80    /* TX carrier polarity*/
0140
0141 #define ENE_CIRMOD_PRD_MAX  0x7F    /* 15.87 kHz */
0142 #define ENE_CIRMOD_PRD_MIN  0x02    /* 1 Mhz */
0143
0144 /* TX pulse width (resolution: 500 ns)*/
0145 #define ENE_CIRMOD_HPRD     0xFECF
0146
0147 /* Hardware versions */
0148 #define ENE_ECHV        0xFF00  /* hardware revision */
0149 #define ENE_PLLFRH      0xFF16
0150 #define ENE_PLLFRL      0xFF17
0151 #define ENE_DEFAULT_PLL_FREQ    1000
0152
0153 #define ENE_ECSTS       0xFF1D
0154 #define ENE_ECSTS_RSRVD     0x04
0155
0156 #define ENE_ECVER_MAJOR     0xFF1E  /* chip version */
0157 #define ENE_ECVER_MINOR     0xFF1F
0158 #define ENE_HW_VER_OLD      0xFD00
0159
0160 /******************************************************************************/
0161
0162 #define ENE_DRIVER_NAME     "ene_ir"
0163
0164 #define ENE_IRQ_RX      1
0165 #define ENE_IRQ_TX      2
0166
0167 #define  ENE_HW_B       1   /* 3926B */
0168 #define  ENE_HW_C       2   /* 3926C */
0169 #define  ENE_HW_D       3   /* 3926D or later */
0170
0171 #define __dbg(level, format, ...)               \
0172 do {                                \
0173     if (debug >= level)                 \
0174         pr_info(format "\n", ## __VA_ARGS__);       \
0175 } while (0)
0176
0177 #define dbg(format, ...)        __dbg(1, format, ## __VA_ARGS__)
0178 #define dbg_verbose(format, ...)    __dbg(2, format, ## __VA_ARGS__)
0179 #define dbg_regs(format, ...)       __dbg(3, format, ## __VA_ARGS__)
0180
0181 struct ene_device {
0182     struct pnp_dev *pnp_dev;
0183     struct rc_dev *rdev;
0184
0185     /* hw IO settings */
0186     long hw_io;
0187     int irq;
0188     spinlock_t hw_lock;
0189
0190     /* HW features */
0191     int hw_revision;            /* hardware revision */
0192     bool hw_use_gpio_0a;            /* gpio0a is demodulated input*/
0193     bool hw_extra_buffer;           /* hardware has 'extra buffer' */
0194     bool hw_fan_input;          /* fan input is IR data source */
0195     bool hw_learning_and_tx_capable;    /* learning & tx capable */
0196     int  pll_freq;
0197     int buffer_len;
0198
0199     /* Extra RX buffer location */
0200     int extra_buf1_address;
0201     int extra_buf1_len;
0202     int extra_buf2_address;
0203     int extra_buf2_len;
0204
0205     /* HW state*/
0206     int r_pointer;              /* pointer to next sample to read */
0207     int w_pointer;              /* pointer to next sample hw will write */
0208     bool rx_fan_input_inuse;        /* is fan input in use for rx*/
0209     int tx_reg;             /* current reg used for TX */
0210     u8  saved_conf1;            /* saved FEC0 reg */
0211     unsigned int tx_sample;         /* current sample for TX */
0212     bool tx_sample_pulse;           /* current sample is pulse */
0213
0214     /* TX buffer */
0215     unsigned *tx_buffer;            /* input samples buffer*/
0216     int tx_pos;             /* position in that buffer */
0217     int tx_len;             /* current len of tx buffer */
0218     int tx_done;                /* done transmitting */
0219                         /* one more sample pending*/
0220     struct completion tx_complete;      /* TX completion */
0221     struct timer_list tx_sim_timer;
0222
0223     /* TX settings */
0224     int tx_period;
0225     int tx_duty_cycle;
0226     int transmitter_mask;
0227
0228     /* RX settings */
0229     bool learning_mode_enabled;     /* learning input enabled */
0230     bool carrier_detect_enabled;        /* carrier detect enabled */
0231     int rx_period_adjust;
0232     bool rx_enabled;
0233 };
0234
0235 static int ene_irq_status(struct ene_device *dev);
0236 static void ene_rx_read_hw_pointer(struct ene_device *dev);