stm32/dma2d/dma2d.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * ST stm32 DMA2D - 2D Graphics Accelerator Driver
0004  *
0005  * Copyright (c) 2021 Dillon Min
0006  * Dillon Min, <dillon.minfei@gmail.com>
0007  *
0008  * based on s5p-g2d
0009  *
0010  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0011  * Kamil Debski, <k.debski@samsung.com>
0012  */
0013
0014 #ifndef __DMA2D_H__
0015 #define __DMA2D_H__
0016
0017 #include <linux/platform_device.h>
0018 #include <media/v4l2-device.h>
0019 #include <media/v4l2-ctrls.h>
0020
0021 #define DMA2D_NAME "stm-dma2d"
0022 #define BUS_INFO "platform:stm-dma2d"
0023 enum dma2d_op_mode {
0024     DMA2D_MODE_M2M,
0025     DMA2D_MODE_M2M_FPC,
0026     DMA2D_MODE_M2M_BLEND,
0027     DMA2D_MODE_R2M
0028 };
0029
0030 enum dma2d_cmode {
0031     /* output pfc cmode from ARGB888 to ARGB4444 */
0032     DMA2D_CMODE_ARGB8888,
0033     DMA2D_CMODE_RGB888,
0034     DMA2D_CMODE_RGB565,
0035     DMA2D_CMODE_ARGB1555,
0036     DMA2D_CMODE_ARGB4444,
0037     /* bg or fg pfc cmode from L8 to A4 */
0038     DMA2D_CMODE_L8,
0039     DMA2D_CMODE_AL44,
0040     DMA2D_CMODE_AL88,
0041     DMA2D_CMODE_L4,
0042     DMA2D_CMODE_A8,
0043     DMA2D_CMODE_A4
0044 };
0045
0046 enum dma2d_alpha_mode {
0047     DMA2D_ALPHA_MODE_NO_MODIF,
0048     DMA2D_ALPHA_MODE_REPLACE,
0049     DMA2D_ALPHA_MODE_COMBINE
0050 };
0051
0052 struct dma2d_fmt {
0053     u32 fourcc;
0054     int depth;
0055     enum dma2d_cmode cmode;
0056 };
0057
0058 struct dma2d_frame {
0059     /* Original dimensions */
0060     u32 width;
0061     u32 height;
0062     /* Crop size */
0063     u32 c_width;
0064     u32 c_height;
0065     /* Offset */
0066     u32 o_width;
0067     u32 o_height;
0068     u32 bottom;
0069     u32 right;
0070     u16 line_offset;
0071     /* Image format */
0072     struct dma2d_fmt *fmt;
0073     /* [0]: blue
0074      * [1]: green
0075      * [2]: red
0076      * [3]: alpha
0077      */
0078     u8  a_rgb[4];
0079     /*
0080      * AM[1:0] of DMA2D_FGPFCCR
0081      */
0082     enum dma2d_alpha_mode a_mode;
0083     u32 size;
0084     unsigned int    sequence;
0085 };
0086
0087 struct dma2d_ctx {
0088     struct v4l2_fh fh;
0089     struct dma2d_dev    *dev;
0090     struct dma2d_frame  cap;
0091     struct dma2d_frame  out;
0092     struct dma2d_frame  bg;
0093     /* fb_buf always point to bg address */
0094     struct v4l2_framebuffer fb_buf;
0095     /*
0096      * MODE[17:16] of DMA2D_CR
0097      */
0098     enum dma2d_op_mode  op_mode;
0099     struct v4l2_ctrl_handler ctrl_handler;
0100     enum v4l2_colorspace    colorspace;
0101     enum v4l2_ycbcr_encoding ycbcr_enc;
0102     enum v4l2_xfer_func xfer_func;
0103     enum v4l2_quantization  quant;
0104 };
0105
0106 struct dma2d_dev {
0107     struct v4l2_device  v4l2_dev;
0108     struct v4l2_m2m_dev *m2m_dev;
0109     struct video_device *vfd;
0110     /* for device open/close etc */
0111     struct mutex        mutex;
0112     /* to avoid the conflict with device running and user setting
0113      * at the same time
0114      */
0115     spinlock_t      ctrl_lock;
0116     atomic_t        num_inst;
0117     void __iomem        *regs;
0118     struct clk      *gate;
0119     struct dma2d_ctx    *curr;
0120     int irq;
0121 };
0122
0123 void dma2d_start(struct dma2d_dev *d);
0124 u32 dma2d_get_int(struct dma2d_dev *d);
0125 void dma2d_clear_int(struct dma2d_dev *d);
0126 void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm,
0127               dma_addr_t o_addr);
0128 void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm,
0129              dma_addr_t f_addr);
0130 void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm,
0131              dma_addr_t b_addr);
0132 void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode,
0133              u16 width, u16 height);
0134
0135 #endif /* __DMA2D_H__ */