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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * STM32 DMA2D - 2D Graphics Accelerator Driver
0004  *
0005  * Copyright (c) 2021 Dillon Min
0006  * Dillon Min, <dillon.minfei@gmail.com>
0007  *
0008  * based on s5p-g2d
0009  *
0010  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0011  * Kamil Debski, <k.debski@samsung.com>
0012  */
0013 
0014 #include <linux/module.h>
0015 #include <linux/fs.h>
0016 #include <linux/timer.h>
0017 #include <linux/sched.h>
0018 #include <linux/slab.h>
0019 #include <linux/clk.h>
0020 #include <linux/interrupt.h>
0021 #include <linux/of.h>
0022 
0023 #include <linux/platform_device.h>
0024 #include <media/v4l2-mem2mem.h>
0025 #include <media/v4l2-device.h>
0026 #include <media/v4l2-ioctl.h>
0027 #include <media/v4l2-event.h>
0028 #include <media/videobuf2-v4l2.h>
0029 #include <media/videobuf2-dma-contig.h>
0030 
0031 #include "dma2d.h"
0032 #include "dma2d-regs.h"
0033 
0034 /*
0035  * This V4L2 subdev m2m driver enables Chrom-Art Accelerator unit
0036  * of STMicroelectronics STM32 SoC series.
0037  *
0038  * Currently support r2m, m2m, m2m_pfc.
0039  *
0040  * - r2m, Filling a part or the whole of a destination image with a specific
0041  *   color.
0042  * - m2m, Copying a part or the whole of a source image into a part or the
0043  *   whole of a destination.
0044  * - m2m_pfc, Copying a part or the whole of a source image into a part or the
0045  *   whole of a destination image with a pixel format conversion.
0046  */
0047 
0048 #define fh2ctx(__fh) container_of(__fh, struct dma2d_ctx, fh)
0049 
0050 static const struct dma2d_fmt formats[] = {
0051     {
0052         .fourcc = V4L2_PIX_FMT_ARGB32,
0053         .cmode = DMA2D_CMODE_ARGB8888,
0054         .depth = 32,
0055     },
0056     {
0057         .fourcc = V4L2_PIX_FMT_RGB24,
0058         .cmode = DMA2D_CMODE_RGB888,
0059         .depth = 24,
0060     },
0061     {
0062         .fourcc = V4L2_PIX_FMT_RGB565,
0063         .cmode = DMA2D_CMODE_RGB565,
0064         .depth = 16,
0065     },
0066     {
0067         .fourcc = V4L2_PIX_FMT_ARGB555,
0068         .cmode = DMA2D_CMODE_ARGB1555,
0069         .depth = 16,
0070     },
0071     {
0072         .fourcc = V4L2_PIX_FMT_ARGB444,
0073         .cmode = DMA2D_CMODE_ARGB4444,
0074         .depth = 16,
0075     },
0076 };
0077 
0078 #define NUM_FORMATS ARRAY_SIZE(formats)
0079 
0080 static const struct dma2d_frame def_frame = {
0081     .width      = DEFAULT_WIDTH,
0082     .height     = DEFAULT_HEIGHT,
0083     .line_offset    = 0,
0084     .a_rgb      = {0x00, 0x00, 0x00, 0xff},
0085     .a_mode     = DMA2D_ALPHA_MODE_NO_MODIF,
0086     .fmt        = (struct dma2d_fmt *)&formats[0],
0087     .size       = DEFAULT_SIZE,
0088 };
0089 
0090 static struct dma2d_fmt *find_fmt(int pixelformat)
0091 {
0092     unsigned int i;
0093 
0094     for (i = 0; i < NUM_FORMATS; i++) {
0095         if (formats[i].fourcc == pixelformat)
0096             return (struct dma2d_fmt *)&formats[i];
0097     }
0098 
0099     return NULL;
0100 }
0101 
0102 static struct dma2d_frame *get_frame(struct dma2d_ctx *ctx,
0103                      enum v4l2_buf_type type)
0104 {
0105     return V4L2_TYPE_IS_OUTPUT(type) ? &ctx->cap : &ctx->out;
0106 }
0107 
0108 static int dma2d_queue_setup(struct vb2_queue *vq,
0109                  unsigned int *nbuffers, unsigned int *nplanes,
0110                  unsigned int sizes[], struct device *alloc_devs[])
0111 {
0112     struct dma2d_ctx *ctx = vb2_get_drv_priv(vq);
0113     struct dma2d_frame *f = get_frame(ctx, vq->type);
0114 
0115     if (*nplanes)
0116         return sizes[0] < f->size ? -EINVAL : 0;
0117 
0118     sizes[0] = f->size;
0119     *nplanes = 1;
0120 
0121     return 0;
0122 }
0123 
0124 static int dma2d_buf_out_validate(struct vb2_buffer *vb)
0125 {
0126     struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0127 
0128     if (vbuf->field == V4L2_FIELD_ANY)
0129         vbuf->field = V4L2_FIELD_NONE;
0130     if (vbuf->field != V4L2_FIELD_NONE)
0131         return -EINVAL;
0132 
0133     return 0;
0134 }
0135 
0136 static int dma2d_buf_prepare(struct vb2_buffer *vb)
0137 {
0138     struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
0139     struct dma2d_frame *f = get_frame(ctx, vb->vb2_queue->type);
0140 
0141     if (vb2_plane_size(vb, 0) < f->size)
0142         return -EINVAL;
0143 
0144     vb2_set_plane_payload(vb, 0, f->size);
0145 
0146     return 0;
0147 }
0148 
0149 static void dma2d_buf_queue(struct vb2_buffer *vb)
0150 {
0151     struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0152     struct dma2d_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
0153 
0154     v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
0155 }
0156 
0157 static int dma2d_start_streaming(struct vb2_queue *q, unsigned int count)
0158 {
0159     struct dma2d_ctx *ctx = vb2_get_drv_priv(q);
0160     struct dma2d_frame *f = get_frame(ctx, q->type);
0161 
0162     f->sequence = 0;
0163     return 0;
0164 }
0165 
0166 static void dma2d_stop_streaming(struct vb2_queue *q)
0167 {
0168     struct dma2d_ctx *ctx = vb2_get_drv_priv(q);
0169     struct vb2_v4l2_buffer *vbuf;
0170 
0171     for (;;) {
0172         if (V4L2_TYPE_IS_OUTPUT(q->type))
0173             vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
0174         else
0175             vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
0176         if (!vbuf)
0177             return;
0178         v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
0179     }
0180 }
0181 
0182 static const struct vb2_ops dma2d_qops = {
0183     .queue_setup    = dma2d_queue_setup,
0184     .buf_out_validate    = dma2d_buf_out_validate,
0185     .buf_prepare    = dma2d_buf_prepare,
0186     .buf_queue  = dma2d_buf_queue,
0187     .start_streaming = dma2d_start_streaming,
0188     .stop_streaming  = dma2d_stop_streaming,
0189     .wait_prepare   = vb2_ops_wait_prepare,
0190     .wait_finish    = vb2_ops_wait_finish,
0191 };
0192 
0193 static int queue_init(void *priv, struct vb2_queue *src_vq,
0194               struct vb2_queue *dst_vq)
0195 {
0196     struct dma2d_ctx *ctx = priv;
0197     int ret;
0198 
0199     src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
0200     src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
0201     src_vq->drv_priv = ctx;
0202     src_vq->ops = &dma2d_qops;
0203     src_vq->mem_ops = &vb2_dma_contig_memops;
0204     src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
0205     src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
0206     src_vq->lock = &ctx->dev->mutex;
0207     src_vq->dev = ctx->dev->v4l2_dev.dev;
0208 
0209     ret = vb2_queue_init(src_vq);
0210     if (ret)
0211         return ret;
0212 
0213     dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
0214     dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
0215     dst_vq->drv_priv = ctx;
0216     dst_vq->ops = &dma2d_qops;
0217     dst_vq->mem_ops = &vb2_dma_contig_memops;
0218     dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
0219     dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
0220     dst_vq->lock = &ctx->dev->mutex;
0221     dst_vq->dev = ctx->dev->v4l2_dev.dev;
0222 
0223     return vb2_queue_init(dst_vq);
0224 }
0225 
0226 static int dma2d_s_ctrl(struct v4l2_ctrl *ctrl)
0227 {
0228     struct dma2d_frame *frm;
0229     struct dma2d_ctx *ctx = container_of(ctrl->handler, struct dma2d_ctx,
0230                                 ctrl_handler);
0231     unsigned long flags;
0232 
0233     spin_lock_irqsave(&ctx->dev->ctrl_lock, flags);
0234     switch (ctrl->id) {
0235     case V4L2_CID_COLORFX:
0236         if (ctrl->val == V4L2_COLORFX_SET_RGB)
0237             ctx->op_mode = DMA2D_MODE_R2M;
0238         else if (ctrl->val == V4L2_COLORFX_NONE)
0239             ctx->op_mode = DMA2D_MODE_M2M;
0240         break;
0241     case V4L2_CID_COLORFX_RGB:
0242         frm = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
0243         frm->a_rgb[2] = (ctrl->val >> 16) & 0xff;
0244         frm->a_rgb[1] = (ctrl->val >> 8) & 0xff;
0245         frm->a_rgb[0] = (ctrl->val >> 0) & 0xff;
0246         break;
0247     default:
0248         spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags);
0249         return -EINVAL;
0250     }
0251     spin_unlock_irqrestore(&ctx->dev->ctrl_lock, flags);
0252 
0253     return 0;
0254 }
0255 
0256 static const struct v4l2_ctrl_ops dma2d_ctrl_ops = {
0257     .s_ctrl = dma2d_s_ctrl,
0258 };
0259 
0260 static int dma2d_setup_ctrls(struct dma2d_ctx *ctx)
0261 {
0262     struct v4l2_ctrl_handler *handler = &ctx->ctrl_handler;
0263 
0264     v4l2_ctrl_handler_init(handler, 2);
0265 
0266     v4l2_ctrl_new_std_menu(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX,
0267                    V4L2_COLORFX_SET_RGB, ~0x10001,
0268                    V4L2_COLORFX_NONE);
0269 
0270     v4l2_ctrl_new_std(handler, &dma2d_ctrl_ops, V4L2_CID_COLORFX_RGB, 0,
0271               0xffffff, 1, 0);
0272 
0273     return 0;
0274 }
0275 
0276 static int dma2d_open(struct file *file)
0277 {
0278     struct dma2d_dev *dev = video_drvdata(file);
0279     struct dma2d_ctx *ctx = NULL;
0280     int ret = 0;
0281 
0282     ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
0283     if (!ctx)
0284         return -ENOMEM;
0285     ctx->dev = dev;
0286     /* Set default formats */
0287     ctx->cap        = def_frame;
0288     ctx->bg     = def_frame;
0289     ctx->out    = def_frame;
0290     ctx->op_mode    = DMA2D_MODE_M2M_FPC;
0291     ctx->colorspace = V4L2_COLORSPACE_REC709;
0292     if (mutex_lock_interruptible(&dev->mutex)) {
0293         kfree(ctx);
0294         return -ERESTARTSYS;
0295     }
0296 
0297     ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(dev->m2m_dev, ctx, &queue_init);
0298     if (IS_ERR(ctx->fh.m2m_ctx)) {
0299         ret = PTR_ERR(ctx->fh.m2m_ctx);
0300         mutex_unlock(&dev->mutex);
0301         kfree(ctx);
0302         return ret;
0303     }
0304 
0305     v4l2_fh_init(&ctx->fh, video_devdata(file));
0306     file->private_data = &ctx->fh;
0307     v4l2_fh_add(&ctx->fh);
0308 
0309     dma2d_setup_ctrls(ctx);
0310 
0311     /* Write the default values to the ctx struct */
0312     v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
0313 
0314     ctx->fh.ctrl_handler = &ctx->ctrl_handler;
0315     mutex_unlock(&dev->mutex);
0316 
0317     return 0;
0318 }
0319 
0320 static int dma2d_release(struct file *file)
0321 {
0322     struct dma2d_dev *dev = video_drvdata(file);
0323     struct dma2d_ctx *ctx = fh2ctx(file->private_data);
0324 
0325     mutex_lock(&dev->mutex);
0326     v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
0327     mutex_unlock(&dev->mutex);
0328     v4l2_ctrl_handler_free(&ctx->ctrl_handler);
0329     v4l2_fh_del(&ctx->fh);
0330     v4l2_fh_exit(&ctx->fh);
0331     kfree(ctx);
0332 
0333     return 0;
0334 }
0335 
0336 static int vidioc_querycap(struct file *file, void *priv,
0337                struct v4l2_capability *cap)
0338 {
0339     strscpy(cap->driver, DMA2D_NAME, sizeof(cap->driver));
0340     strscpy(cap->card, DMA2D_NAME, sizeof(cap->card));
0341     strscpy(cap->bus_info, BUS_INFO, sizeof(cap->bus_info));
0342 
0343     return 0;
0344 }
0345 
0346 static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
0347 {
0348     if (f->index >= NUM_FORMATS)
0349         return -EINVAL;
0350 
0351     f->pixelformat = formats[f->index].fourcc;
0352     return 0;
0353 }
0354 
0355 static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
0356 {
0357     struct dma2d_ctx *ctx = prv;
0358     struct vb2_queue *vq;
0359     struct dma2d_frame *frm;
0360 
0361     vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
0362     if (!vq)
0363         return -EINVAL;
0364 
0365     frm = get_frame(ctx, f->type);
0366     f->fmt.pix.width        = frm->width;
0367     f->fmt.pix.height       = frm->height;
0368     f->fmt.pix.field        = V4L2_FIELD_NONE;
0369     f->fmt.pix.pixelformat      = frm->fmt->fourcc;
0370     f->fmt.pix.bytesperline     = (frm->width * frm->fmt->depth) >> 3;
0371     f->fmt.pix.sizeimage        = frm->size;
0372     f->fmt.pix.colorspace       = ctx->colorspace;
0373     f->fmt.pix.xfer_func        = ctx->xfer_func;
0374     f->fmt.pix.ycbcr_enc        = ctx->ycbcr_enc;
0375     f->fmt.pix.quantization     = ctx->quant;
0376 
0377     return 0;
0378 }
0379 
0380 static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
0381 {
0382     struct dma2d_ctx *ctx = prv;
0383     struct dma2d_fmt *fmt;
0384     enum v4l2_field *field;
0385     u32 fourcc = f->fmt.pix.pixelformat;
0386 
0387     fmt = find_fmt(fourcc);
0388     if (!fmt) {
0389         f->fmt.pix.pixelformat = formats[0].fourcc;
0390         fmt = find_fmt(f->fmt.pix.pixelformat);
0391     }
0392 
0393     field = &f->fmt.pix.field;
0394     if (*field == V4L2_FIELD_ANY)
0395         *field = V4L2_FIELD_NONE;
0396     else if (*field != V4L2_FIELD_NONE)
0397         return -EINVAL;
0398 
0399     if (f->fmt.pix.width > MAX_WIDTH)
0400         f->fmt.pix.width = MAX_WIDTH;
0401     if (f->fmt.pix.height > MAX_HEIGHT)
0402         f->fmt.pix.height = MAX_HEIGHT;
0403 
0404     if (f->fmt.pix.width < 1)
0405         f->fmt.pix.width = 1;
0406     if (f->fmt.pix.height < 1)
0407         f->fmt.pix.height = 1;
0408 
0409     if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT && !f->fmt.pix.colorspace) {
0410         f->fmt.pix.colorspace = V4L2_COLORSPACE_REC709;
0411     } else if (f->type == V4L2_BUF_TYPE_VIDEO_CAPTURE) {
0412         f->fmt.pix.colorspace   = ctx->colorspace;
0413         f->fmt.pix.xfer_func = ctx->xfer_func;
0414         f->fmt.pix.ycbcr_enc = ctx->ycbcr_enc;
0415         f->fmt.pix.quantization = ctx->quant;
0416     }
0417     f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
0418     f->fmt.pix.sizeimage = f->fmt.pix.height * f->fmt.pix.bytesperline;
0419 
0420     return 0;
0421 }
0422 
0423 static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
0424 {
0425     struct dma2d_ctx *ctx = prv;
0426     struct vb2_queue *vq;
0427     struct dma2d_frame *frm;
0428     struct dma2d_fmt *fmt;
0429     int ret = 0;
0430 
0431     /* Adjust all values accordingly to the hardware capabilities
0432      * and chosen format.
0433      */
0434     ret = vidioc_try_fmt(file, prv, f);
0435     if (ret)
0436         return ret;
0437 
0438     vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
0439     if (vb2_is_busy(vq))
0440         return -EBUSY;
0441 
0442     fmt = find_fmt(f->fmt.pix.pixelformat);
0443     if (!fmt)
0444         return -EINVAL;
0445 
0446     if (f->type == V4L2_BUF_TYPE_VIDEO_OUTPUT) {
0447         ctx->colorspace = f->fmt.pix.colorspace;
0448         ctx->xfer_func = f->fmt.pix.xfer_func;
0449         ctx->ycbcr_enc = f->fmt.pix.ycbcr_enc;
0450         ctx->quant = f->fmt.pix.quantization;
0451     }
0452 
0453     frm = get_frame(ctx, f->type);
0454     frm->width = f->fmt.pix.width;
0455     frm->height = f->fmt.pix.height;
0456     frm->size = f->fmt.pix.sizeimage;
0457     /* Reset crop settings */
0458     frm->o_width = 0;
0459     frm->o_height = 0;
0460     frm->c_width = frm->width;
0461     frm->c_height = frm->height;
0462     frm->right = frm->width;
0463     frm->bottom = frm->height;
0464     frm->fmt = fmt;
0465     frm->line_offset = 0;
0466 
0467     return 0;
0468 }
0469 
0470 static void device_run(void *prv)
0471 {
0472     struct dma2d_ctx *ctx = prv;
0473     struct dma2d_dev *dev = ctx->dev;
0474     struct dma2d_frame *frm_out, *frm_cap;
0475     struct vb2_v4l2_buffer *src, *dst;
0476     unsigned long flags;
0477 
0478     spin_lock_irqsave(&dev->ctrl_lock, flags);
0479     dev->curr = ctx;
0480 
0481     src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
0482     dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
0483     if (!dst || !src)
0484         goto end;
0485 
0486     frm_cap = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
0487     frm_out = get_frame(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
0488     if (!frm_cap || !frm_out)
0489         goto end;
0490 
0491     src->sequence = frm_out->sequence++;
0492     dst->sequence = frm_cap->sequence++;
0493     v4l2_m2m_buf_copy_metadata(src, dst, true);
0494 
0495     clk_enable(dev->gate);
0496 
0497     dma2d_config_fg(dev, frm_out,
0498             vb2_dma_contig_plane_dma_addr(&src->vb2_buf, 0));
0499 
0500     /* TODO: add M2M_BLEND handler here */
0501 
0502     if (ctx->op_mode != DMA2D_MODE_R2M) {
0503         if (frm_out->fmt->fourcc == frm_cap->fmt->fourcc)
0504             ctx->op_mode = DMA2D_MODE_M2M;
0505         else
0506             ctx->op_mode = DMA2D_MODE_M2M_FPC;
0507     }
0508 
0509     dma2d_config_out(dev, frm_cap,
0510              vb2_dma_contig_plane_dma_addr(&dst->vb2_buf, 0));
0511     dma2d_config_common(dev, ctx->op_mode, frm_cap->width, frm_cap->height);
0512 
0513     dma2d_start(dev);
0514 end:
0515     spin_unlock_irqrestore(&dev->ctrl_lock, flags);
0516 }
0517 
0518 static irqreturn_t dma2d_isr(int irq, void *prv)
0519 {
0520     struct dma2d_dev *dev = prv;
0521     struct dma2d_ctx *ctx = dev->curr;
0522     struct vb2_v4l2_buffer *src, *dst;
0523     u32 s = dma2d_get_int(dev);
0524 
0525     dma2d_clear_int(dev);
0526     if (s & ISR_TCIF || s == 0) {
0527         clk_disable(dev->gate);
0528 
0529         WARN_ON(!ctx);
0530 
0531         src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
0532         dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
0533 
0534         WARN_ON(!dst);
0535         WARN_ON(!src);
0536 
0537         v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
0538         v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
0539         v4l2_m2m_job_finish(dev->m2m_dev, ctx->fh.m2m_ctx);
0540 
0541         dev->curr = NULL;
0542     }
0543 
0544     return IRQ_HANDLED;
0545 }
0546 
0547 static const struct v4l2_file_operations dma2d_fops = {
0548     .owner      = THIS_MODULE,
0549     .open       = dma2d_open,
0550     .release    = dma2d_release,
0551     .poll       = v4l2_m2m_fop_poll,
0552     .unlocked_ioctl = video_ioctl2,
0553     .mmap       = v4l2_m2m_fop_mmap,
0554 #ifndef CONFIG_MMU
0555     .get_unmapped_area = v4l2_m2m_get_unmapped_area,
0556 #endif
0557 };
0558 
0559 static const struct v4l2_ioctl_ops dma2d_ioctl_ops = {
0560     .vidioc_querycap    = vidioc_querycap,
0561 
0562     .vidioc_enum_fmt_vid_cap    = vidioc_enum_fmt,
0563     .vidioc_g_fmt_vid_cap       = vidioc_g_fmt,
0564     .vidioc_try_fmt_vid_cap     = vidioc_try_fmt,
0565     .vidioc_s_fmt_vid_cap       = vidioc_s_fmt,
0566 
0567     .vidioc_enum_fmt_vid_out    = vidioc_enum_fmt,
0568     .vidioc_g_fmt_vid_out       = vidioc_g_fmt,
0569     .vidioc_try_fmt_vid_out     = vidioc_try_fmt,
0570     .vidioc_s_fmt_vid_out       = vidioc_s_fmt,
0571 
0572     .vidioc_reqbufs         = v4l2_m2m_ioctl_reqbufs,
0573     .vidioc_querybuf        = v4l2_m2m_ioctl_querybuf,
0574     .vidioc_qbuf            = v4l2_m2m_ioctl_qbuf,
0575     .vidioc_dqbuf           = v4l2_m2m_ioctl_dqbuf,
0576     .vidioc_prepare_buf     = v4l2_m2m_ioctl_prepare_buf,
0577     .vidioc_create_bufs     = v4l2_m2m_ioctl_create_bufs,
0578     .vidioc_expbuf          = v4l2_m2m_ioctl_expbuf,
0579 
0580     .vidioc_streamon        = v4l2_m2m_ioctl_streamon,
0581     .vidioc_streamoff       = v4l2_m2m_ioctl_streamoff,
0582 
0583     .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
0584     .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
0585 };
0586 
0587 static const struct video_device dma2d_videodev = {
0588     .name       = DMA2D_NAME,
0589     .fops       = &dma2d_fops,
0590     .ioctl_ops  = &dma2d_ioctl_ops,
0591     .minor      = -1,
0592     .release    = video_device_release,
0593     .vfl_dir    = VFL_DIR_M2M,
0594 };
0595 
0596 static const struct v4l2_m2m_ops dma2d_m2m_ops = {
0597     .device_run = device_run,
0598 };
0599 
0600 static const struct of_device_id stm32_dma2d_match[];
0601 
0602 static int dma2d_probe(struct platform_device *pdev)
0603 {
0604     struct dma2d_dev *dev;
0605     struct video_device *vfd;
0606     struct resource *res;
0607     int ret = 0;
0608 
0609     dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
0610     if (!dev)
0611         return -ENOMEM;
0612 
0613     spin_lock_init(&dev->ctrl_lock);
0614     mutex_init(&dev->mutex);
0615     atomic_set(&dev->num_inst, 0);
0616 
0617     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0618 
0619     dev->regs = devm_ioremap_resource(&pdev->dev, res);
0620     if (IS_ERR(dev->regs))
0621         return PTR_ERR(dev->regs);
0622 
0623     dev->gate = clk_get(&pdev->dev, "dma2d");
0624     if (IS_ERR(dev->gate)) {
0625         dev_err(&pdev->dev, "failed to get dma2d clock gate\n");
0626         ret = -ENXIO;
0627         return ret;
0628     }
0629 
0630     ret = clk_prepare(dev->gate);
0631     if (ret) {
0632         dev_err(&pdev->dev, "failed to prepare dma2d clock gate\n");
0633         goto put_clk_gate;
0634     }
0635 
0636     ret = platform_get_irq(pdev, 0);
0637     if (ret < 0)
0638         goto unprep_clk_gate;
0639 
0640     dev->irq = ret;
0641 
0642     ret = devm_request_irq(&pdev->dev, dev->irq, dma2d_isr,
0643                    0, pdev->name, dev);
0644     if (ret) {
0645         dev_err(&pdev->dev, "failed to install IRQ\n");
0646         goto unprep_clk_gate;
0647     }
0648 
0649     ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
0650     if (ret)
0651         goto unprep_clk_gate;
0652 
0653     vfd = video_device_alloc();
0654     if (!vfd) {
0655         v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
0656         ret = -ENOMEM;
0657         goto unreg_v4l2_dev;
0658     }
0659 
0660     *vfd = dma2d_videodev;
0661     vfd->lock = &dev->mutex;
0662     vfd->v4l2_dev = &dev->v4l2_dev;
0663     vfd->device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING;
0664 
0665     platform_set_drvdata(pdev, dev);
0666     dev->m2m_dev = v4l2_m2m_init(&dma2d_m2m_ops);
0667     if (IS_ERR(dev->m2m_dev)) {
0668         v4l2_err(&dev->v4l2_dev, "Failed to init mem2mem device\n");
0669         ret = PTR_ERR(dev->m2m_dev);
0670         goto rel_vdev;
0671     }
0672 
0673     ret = video_register_device(vfd, VFL_TYPE_VIDEO, 0);
0674     if (ret) {
0675         v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
0676         goto free_m2m;
0677     }
0678 
0679     video_set_drvdata(vfd, dev);
0680     dev->vfd = vfd;
0681     v4l2_info(&dev->v4l2_dev, "device registered as /dev/video%d\n",
0682           vfd->num);
0683     return 0;
0684 
0685 free_m2m:
0686     v4l2_m2m_release(dev->m2m_dev);
0687 rel_vdev:
0688     video_device_release(vfd);
0689 unreg_v4l2_dev:
0690     v4l2_device_unregister(&dev->v4l2_dev);
0691 unprep_clk_gate:
0692     clk_unprepare(dev->gate);
0693 put_clk_gate:
0694     clk_put(dev->gate);
0695 
0696     return ret;
0697 }
0698 
0699 static int dma2d_remove(struct platform_device *pdev)
0700 {
0701     struct dma2d_dev *dev = platform_get_drvdata(pdev);
0702 
0703     v4l2_info(&dev->v4l2_dev, "Removing " DMA2D_NAME);
0704     v4l2_m2m_release(dev->m2m_dev);
0705     video_unregister_device(dev->vfd);
0706     v4l2_device_unregister(&dev->v4l2_dev);
0707     vb2_dma_contig_clear_max_seg_size(&pdev->dev);
0708     clk_unprepare(dev->gate);
0709     clk_put(dev->gate);
0710 
0711     return 0;
0712 }
0713 
0714 static const struct of_device_id stm32_dma2d_match[] = {
0715     {
0716         .compatible = "st,stm32-dma2d",
0717         .data = NULL,
0718     },
0719     {},
0720 };
0721 MODULE_DEVICE_TABLE(of, stm32_dma2d_match);
0722 
0723 static struct platform_driver dma2d_pdrv = {
0724     .probe      = dma2d_probe,
0725     .remove     = dma2d_remove,
0726     .driver     = {
0727         .name = DMA2D_NAME,
0728         .of_match_table = stm32_dma2d_match,
0729     },
0730 };
0731 
0732 module_platform_driver(dma2d_pdrv);
0733 
0734 MODULE_AUTHOR("Dillon Min <dillon.minfei@gmail.com>");
0735 MODULE_DESCRIPTION("STM32 Chrom-Art Accelerator DMA2D driver");
0736 MODULE_LICENSE("GPL");
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