stm32/dma2d/dma2d-regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
0004  *
0005  * Copyright (c) 2021 Dillon Min
0006  * Dillon Min, <dillon.minfei@gmail.com>
0007  *
0008  * based on s5p-g2d
0009  *
0010  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0011  * Kamil Debski, <k.debski@samsung.com>
0012  */
0013
0014 #ifndef __DMA2D_REGS_H__
0015 #define __DMA2D_REGS_H__
0016
0017 #define DMA2D_CR_REG        0x0000
0018 #define CR_MODE_MASK        GENMASK(17, 16)
0019 #define CR_MODE_SHIFT       16
0020 #define CR_M2M          0x0000
0021 #define CR_M2M_PFC      BIT(16)
0022 #define CR_M2M_BLEND        BIT(17)
0023 #define CR_R2M          (BIT(17) | BIT(16))
0024 #define CR_CEIE         BIT(13)
0025 #define CR_CTCIE        BIT(12)
0026 #define CR_CAEIE        BIT(11)
0027 #define CR_TWIE         BIT(10)
0028 #define CR_TCIE         BIT(9)
0029 #define CR_TEIE         BIT(8)
0030 #define CR_ABORT        BIT(2)
0031 #define CR_SUSP         BIT(1)
0032 #define CR_START        BIT(0)
0033
0034 #define DMA2D_ISR_REG       0x0004
0035 #define ISR_CEIF        BIT(5)
0036 #define ISR_CTCIF       BIT(4)
0037 #define ISR_CAEIF       BIT(3)
0038 #define ISR_TWIF        BIT(2)
0039 #define ISR_TCIF        BIT(1)
0040 #define ISR_TEIF        BIT(0)
0041
0042 #define DMA2D_IFCR_REG      0x0008
0043 #define IFCR_CCEIF      BIT(5)
0044 #define IFCR_CCTCIF     BIT(4)
0045 #define IFCR_CAECIF     BIT(3)
0046 #define IFCR_CTWIF      BIT(2)
0047 #define IFCR_CTCIF      BIT(1)
0048 #define IFCR_CTEIF      BIT(0)
0049
0050 #define DMA2D_FGMAR_REG     0x000c
0051 #define DMA2D_FGOR_REG      0x0010
0052 #define FGOR_LO_MASK        GENMASK(13, 0)
0053
0054 #define DMA2D_BGMAR_REG     0x0014
0055 #define DMA2D_BGOR_REG      0x0018
0056 #define BGOR_LO_MASK        GENMASK(13, 0)
0057
0058 #define DMA2D_FGPFCCR_REG   0x001c
0059 #define FGPFCCR_ALPHA_MASK  GENMASK(31, 24)
0060 #define FGPFCCR_AM_MASK     GENMASK(17, 16)
0061 #define FGPFCCR_CS_MASK     GENMASK(15, 8)
0062 #define FGPFCCR_START       BIT(5)
0063 #define FGPFCCR_CCM_RGB888  BIT(4)
0064 #define FGPFCCR_CM_MASK     GENMASK(3, 0)
0065
0066 #define DMA2D_FGCOLR_REG    0x0020
0067 #define FGCOLR_REG_MASK     GENMASK(23, 16)
0068 #define FGCOLR_GREEN_MASK   GENMASK(15, 8)
0069 #define FGCOLR_BLUE_MASK    GENMASK(7, 0)
0070
0071 #define DMA2D_BGPFCCR_REG   0x0024
0072 #define BGPFCCR_ALPHA_MASK  GENMASK(31, 24)
0073 #define BGPFCCR_AM_MASK     GENMASK(17, 16)
0074 #define BGPFCCR_CS_MASK     GENMASK(15, 8)
0075 #define BGPFCCR_START       BIT(5)
0076 #define BGPFCCR_CCM_RGB888  BIT(4)
0077 #define BGPFCCR_CM_MASK     GENMASK(3, 0)
0078
0079 #define DMA2D_BGCOLR_REG    0x0028
0080 #define BGCOLR_REG_MASK     GENMASK(23, 16)
0081 #define BGCOLR_GREEN_MASK   GENMASK(15, 8)
0082 #define BGCOLR_BLUE_MASK    GENMASK(7, 0)
0083
0084 #define DMA2D_OPFCCR_REG    0x0034
0085 #define OPFCCR_CM_MASK      GENMASK(2, 0)
0086
0087 #define DMA2D_OCOLR_REG     0x0038
0088 #define OCOLR_ALPHA_MASK    GENMASK(31, 24)
0089 #define OCOLR_RED_MASK      GENMASK(23, 16)
0090 #define OCOLR_GREEN_MASK    GENMASK(15, 8)
0091 #define OCOLR_BLUE_MASK     GENMASK(7, 0)
0092
0093 #define DMA2D_OMAR_REG      0x003c
0094
0095 #define DMA2D_OOR_REG       0x0040
0096 #define OOR_LO_MASK     GENMASK(13, 0)
0097
0098 #define DMA2D_NLR_REG       0x0044
0099 #define NLR_PL_MASK     GENMASK(29, 16)
0100 #define NLR_NL_MASK     GENMASK(15, 0)
0101
0102 /* Hardware limits */
0103 #define MAX_WIDTH       2592
0104 #define MAX_HEIGHT      2592
0105
0106 #define DEFAULT_WIDTH       240
0107 #define DEFAULT_HEIGHT      320
0108 #define DEFAULT_SIZE        307200
0109
0110 #define CM_MODE_ARGB8888    0x00
0111 #define CM_MODE_ARGB4444    0x04
0112 #define CM_MODE_A4      0x0a
0113 #endif /* __DMA2D_REGS_H__ */