stm32/dma2d/dma2d-hw.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * ST stm32 Chrom-Art - 2D Graphics Accelerator Driver
0004  *
0005  * Copyright (c) 2021 Dillon Min
0006  * Dillon Min, <dillon.minfei@gmail.com>
0007  *
0008  * based on s5p-g2d
0009  *
0010  * Copyright (c) 2011 Samsung Electronics Co., Ltd.
0011  * Kamil Debski, <k.debski@samsung.com>
0012  */
0013
0014 #include <linux/io.h>
0015
0016 #include "dma2d.h"
0017 #include "dma2d-regs.h"
0018
0019 static inline u32 reg_read(void __iomem *base, u32 reg)
0020 {
0021     return readl_relaxed(base + reg);
0022 }
0023
0024 static inline void reg_write(void __iomem *base, u32 reg, u32 val)
0025 {
0026     writel_relaxed(val, base + reg);
0027 }
0028
0029 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask,
0030                    u32 val)
0031 {
0032     reg_write(base, reg, (reg_read(base, reg) & ~mask) | val);
0033 }
0034
0035 void dma2d_start(struct dma2d_dev *d)
0036 {
0037     reg_update_bits(d->regs, DMA2D_CR_REG, CR_START, CR_START);
0038 }
0039
0040 u32 dma2d_get_int(struct dma2d_dev *d)
0041 {
0042     return reg_read(d->regs, DMA2D_ISR_REG);
0043 }
0044
0045 void dma2d_clear_int(struct dma2d_dev *d)
0046 {
0047     u32 isr_val = reg_read(d->regs, DMA2D_ISR_REG);
0048
0049     reg_write(d->regs, DMA2D_IFCR_REG, isr_val & 0x003f);
0050 }
0051
0052 void dma2d_config_common(struct dma2d_dev *d, enum dma2d_op_mode op_mode,
0053              u16 width, u16 height)
0054 {
0055     reg_update_bits(d->regs, DMA2D_CR_REG, CR_MODE_MASK,
0056             op_mode << CR_MODE_SHIFT);
0057
0058     reg_write(d->regs, DMA2D_NLR_REG, (width << 16) | height);
0059 }
0060
0061 void dma2d_config_out(struct dma2d_dev *d, struct dma2d_frame *frm,
0062               dma_addr_t o_addr)
0063 {
0064     reg_update_bits(d->regs, DMA2D_CR_REG, CR_CEIE, CR_CEIE);
0065     reg_update_bits(d->regs, DMA2D_CR_REG, CR_CTCIE, CR_CTCIE);
0066     reg_update_bits(d->regs, DMA2D_CR_REG, CR_CAEIE, CR_CAEIE);
0067     reg_update_bits(d->regs, DMA2D_CR_REG, CR_TCIE, CR_TCIE);
0068     reg_update_bits(d->regs, DMA2D_CR_REG, CR_TEIE, CR_TEIE);
0069
0070     if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
0071         frm->fmt->cmode <= CM_MODE_ARGB4444)
0072         reg_update_bits(d->regs, DMA2D_OPFCCR_REG, OPFCCR_CM_MASK,
0073                 frm->fmt->cmode);
0074
0075     reg_write(d->regs, DMA2D_OMAR_REG, o_addr);
0076
0077     reg_write(d->regs, DMA2D_OCOLR_REG,
0078           (frm->a_rgb[3] << 24) |
0079           (frm->a_rgb[2] << 16) |
0080           (frm->a_rgb[1] << 8) |
0081           frm->a_rgb[0]);
0082
0083     reg_update_bits(d->regs, DMA2D_OOR_REG, OOR_LO_MASK,
0084             frm->line_offset & 0x3fff);
0085 }
0086
0087 void dma2d_config_fg(struct dma2d_dev *d, struct dma2d_frame *frm,
0088              dma_addr_t f_addr)
0089 {
0090     reg_write(d->regs, DMA2D_FGMAR_REG, f_addr);
0091     reg_update_bits(d->regs, DMA2D_FGOR_REG, FGOR_LO_MASK,
0092             frm->line_offset);
0093
0094     if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
0095         frm->fmt->cmode <= CM_MODE_A4)
0096         reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_CM_MASK,
0097                 frm->fmt->cmode);
0098
0099     reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_AM_MASK,
0100             (frm->a_mode << 16) & 0x03);
0101
0102     reg_update_bits(d->regs, DMA2D_FGPFCCR_REG, FGPFCCR_ALPHA_MASK,
0103             frm->a_rgb[3] << 24);
0104
0105     reg_write(d->regs, DMA2D_FGCOLR_REG,
0106           (frm->a_rgb[2] << 16) |
0107           (frm->a_rgb[1] << 8) |
0108           frm->a_rgb[0]);
0109 }
0110
0111 void dma2d_config_bg(struct dma2d_dev *d, struct dma2d_frame *frm,
0112              dma_addr_t b_addr)
0113 {
0114     reg_write(d->regs, DMA2D_BGMAR_REG, b_addr);
0115     reg_update_bits(d->regs, DMA2D_BGOR_REG, BGOR_LO_MASK,
0116             frm->line_offset);
0117
0118     if (frm->fmt->cmode >= CM_MODE_ARGB8888 &&
0119         frm->fmt->cmode <= CM_MODE_A4)
0120         reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_CM_MASK,
0121                 frm->fmt->cmode);
0122
0123     reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_AM_MASK,
0124             (frm->a_mode << 16) & 0x03);
0125
0126     reg_update_bits(d->regs, DMA2D_BGPFCCR_REG, BGPFCCR_ALPHA_MASK,
0127             frm->a_rgb[3] << 24);
0128
0129     reg_write(d->regs, DMA2D_BGCOLR_REG,
0130           (frm->a_rgb[2] << 16) |
0131           (frm->a_rgb[1] << 8) |
0132           frm->a_rgb[0]);
0133 }