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0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * R-Car Gen3 Digital Radio Interface (DRIF) driver
0004  *
0005  * Copyright (C) 2017 Renesas Electronics Corporation
0006  */
0007 
0008 /*
0009  * The R-Car DRIF is a receive only MSIOF like controller with an
0010  * external master device driving the SCK. It receives data into a FIFO,
0011  * then this driver uses the SYS-DMAC engine to move the data from
0012  * the device to memory.
0013  *
0014  * Each DRIF channel DRIFx (as per datasheet) contains two internal
0015  * channels DRIFx0 & DRIFx1 within itself with each having its own resources
0016  * like module clk, register set, irq and dma. These internal channels share
0017  * common CLK & SYNC from master. The two data pins D0 & D1 shall be
0018  * considered to represent the two internal channels. This internal split
0019  * is not visible to the master device.
0020  *
0021  * Depending on the master device, a DRIF channel can use
0022  *  (1) both internal channels (D0 & D1) to receive data in parallel (or)
0023  *  (2) one internal channel (D0 or D1) to receive data
0024  *
0025  * The primary design goal of this controller is to act as a Digital Radio
0026  * Interface that receives digital samples from a tuner device. Hence the
0027  * driver exposes the device as a V4L2 SDR device. In order to qualify as
0028  * a V4L2 SDR device, it should possess a tuner interface as mandated by the
0029  * framework. This driver expects a tuner driver (sub-device) to bind
0030  * asynchronously with this device and the combined drivers shall expose
0031  * a V4L2 compliant SDR device. The DRIF driver is independent of the
0032  * tuner vendor.
0033  *
0034  * The DRIF h/w can support I2S mode and Frame start synchronization pulse mode.
0035  * This driver is tested for I2S mode only because of the availability of
0036  * suitable master devices. Hence, not all configurable options of DRIF h/w
0037  * like lsb/msb first, syncdl, dtdl etc. are exposed via DT and I2S defaults
0038  * are used. These can be exposed later if needed after testing.
0039  */
0040 #include <linux/bitops.h>
0041 #include <linux/clk.h>
0042 #include <linux/dma-mapping.h>
0043 #include <linux/dmaengine.h>
0044 #include <linux/ioctl.h>
0045 #include <linux/iopoll.h>
0046 #include <linux/module.h>
0047 #include <linux/of_graph.h>
0048 #include <linux/of_device.h>
0049 #include <linux/platform_device.h>
0050 #include <linux/sched.h>
0051 #include <media/v4l2-async.h>
0052 #include <media/v4l2-ctrls.h>
0053 #include <media/v4l2-device.h>
0054 #include <media/v4l2-event.h>
0055 #include <media/v4l2-fh.h>
0056 #include <media/v4l2-ioctl.h>
0057 #include <media/videobuf2-v4l2.h>
0058 #include <media/videobuf2-vmalloc.h>
0059 
0060 /* DRIF register offsets */
0061 #define RCAR_DRIF_SITMDR1           0x00
0062 #define RCAR_DRIF_SITMDR2           0x04
0063 #define RCAR_DRIF_SITMDR3           0x08
0064 #define RCAR_DRIF_SIRMDR1           0x10
0065 #define RCAR_DRIF_SIRMDR2           0x14
0066 #define RCAR_DRIF_SIRMDR3           0x18
0067 #define RCAR_DRIF_SICTR             0x28
0068 #define RCAR_DRIF_SIFCTR            0x30
0069 #define RCAR_DRIF_SISTR             0x40
0070 #define RCAR_DRIF_SIIER             0x44
0071 #define RCAR_DRIF_SIRFDR            0x60
0072 
0073 #define RCAR_DRIF_RFOVF         BIT(3)  /* Receive FIFO overflow */
0074 #define RCAR_DRIF_RFUDF         BIT(4)  /* Receive FIFO underflow */
0075 #define RCAR_DRIF_RFSERR        BIT(5)  /* Receive frame sync error */
0076 #define RCAR_DRIF_REOF          BIT(7)  /* Frame reception end */
0077 #define RCAR_DRIF_RDREQ         BIT(12) /* Receive data xfer req */
0078 #define RCAR_DRIF_RFFUL         BIT(13) /* Receive FIFO full */
0079 
0080 /* SIRMDR1 */
0081 #define RCAR_DRIF_SIRMDR1_SYNCMD_FRAME      (0 << 28)
0082 #define RCAR_DRIF_SIRMDR1_SYNCMD_LR     (3 << 28)
0083 
0084 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH   (0 << 25)
0085 #define RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW    (1 << 25)
0086 
0087 #define RCAR_DRIF_SIRMDR1_MSB_FIRST     (0 << 24)
0088 #define RCAR_DRIF_SIRMDR1_LSB_FIRST     (1 << 24)
0089 
0090 #define RCAR_DRIF_SIRMDR1_DTDL_0        (0 << 20)
0091 #define RCAR_DRIF_SIRMDR1_DTDL_1        (1 << 20)
0092 #define RCAR_DRIF_SIRMDR1_DTDL_2        (2 << 20)
0093 #define RCAR_DRIF_SIRMDR1_DTDL_0PT5     (5 << 20)
0094 #define RCAR_DRIF_SIRMDR1_DTDL_1PT5     (6 << 20)
0095 
0096 #define RCAR_DRIF_SIRMDR1_SYNCDL_0      (0 << 20)
0097 #define RCAR_DRIF_SIRMDR1_SYNCDL_1      (1 << 20)
0098 #define RCAR_DRIF_SIRMDR1_SYNCDL_2      (2 << 20)
0099 #define RCAR_DRIF_SIRMDR1_SYNCDL_3      (3 << 20)
0100 #define RCAR_DRIF_SIRMDR1_SYNCDL_0PT5       (5 << 20)
0101 #define RCAR_DRIF_SIRMDR1_SYNCDL_1PT5       (6 << 20)
0102 
0103 #define RCAR_DRIF_MDR_GRPCNT(n)         (((n) - 1) << 30)
0104 #define RCAR_DRIF_MDR_BITLEN(n)         (((n) - 1) << 24)
0105 #define RCAR_DRIF_MDR_WDCNT(n)          (((n) - 1) << 16)
0106 
0107 /* Hidden Transmit register that controls CLK & SYNC */
0108 #define RCAR_DRIF_SITMDR1_PCON          BIT(30)
0109 
0110 #define RCAR_DRIF_SICTR_RX_RISING_EDGE      BIT(26)
0111 #define RCAR_DRIF_SICTR_RX_EN           BIT(8)
0112 #define RCAR_DRIF_SICTR_RESET           BIT(0)
0113 
0114 /* Constants */
0115 #define RCAR_DRIF_NUM_HWBUFS            32
0116 #define RCAR_DRIF_MAX_DEVS          4
0117 #define RCAR_DRIF_DEFAULT_NUM_HWBUFS        16
0118 #define RCAR_DRIF_DEFAULT_HWBUF_SIZE        (4 * PAGE_SIZE)
0119 #define RCAR_DRIF_MAX_CHANNEL           2
0120 #define RCAR_SDR_BUFFER_SIZE            SZ_64K
0121 
0122 /* Internal buffer status flags */
0123 #define RCAR_DRIF_BUF_DONE          BIT(0)  /* DMA completed */
0124 #define RCAR_DRIF_BUF_OVERFLOW          BIT(1)  /* Overflow detected */
0125 
0126 #define to_rcar_drif_buf_pair(sdr, ch_num, idx)         \
0127     (&((sdr)->ch[!(ch_num)]->buf[(idx)]))
0128 
0129 #define for_each_rcar_drif_channel(ch, ch_mask)         \
0130     for_each_set_bit(ch, ch_mask, RCAR_DRIF_MAX_CHANNEL)
0131 
0132 /* Debug */
0133 #define rdrif_dbg(sdr, fmt, arg...)             \
0134     dev_dbg(sdr->v4l2_dev.dev, fmt, ## arg)
0135 
0136 #define rdrif_err(sdr, fmt, arg...)             \
0137     dev_err(sdr->v4l2_dev.dev, fmt, ## arg)
0138 
0139 /* Stream formats */
0140 struct rcar_drif_format {
0141     u32 pixelformat;
0142     u32 buffersize;
0143     u32 bitlen;
0144     u32 wdcnt;
0145     u32 num_ch;
0146 };
0147 
0148 /* Format descriptions for capture */
0149 static const struct rcar_drif_format formats[] = {
0150     {
0151         .pixelformat    = V4L2_SDR_FMT_PCU16BE,
0152         .buffersize = RCAR_SDR_BUFFER_SIZE,
0153         .bitlen     = 16,
0154         .wdcnt      = 1,
0155         .num_ch     = 2,
0156     },
0157     {
0158         .pixelformat    = V4L2_SDR_FMT_PCU18BE,
0159         .buffersize = RCAR_SDR_BUFFER_SIZE,
0160         .bitlen     = 18,
0161         .wdcnt      = 1,
0162         .num_ch     = 2,
0163     },
0164     {
0165         .pixelformat    = V4L2_SDR_FMT_PCU20BE,
0166         .buffersize = RCAR_SDR_BUFFER_SIZE,
0167         .bitlen     = 20,
0168         .wdcnt      = 1,
0169         .num_ch     = 2,
0170     },
0171 };
0172 
0173 /* Buffer for a received frame from one or both internal channels */
0174 struct rcar_drif_frame_buf {
0175     /* Common v4l buffer stuff -- must be first */
0176     struct vb2_v4l2_buffer vb;
0177     struct list_head list;
0178 };
0179 
0180 /* OF graph endpoint's V4L2 async data */
0181 struct rcar_drif_graph_ep {
0182     struct v4l2_subdev *subdev; /* Async matched subdev */
0183 };
0184 
0185 /* DMA buffer */
0186 struct rcar_drif_hwbuf {
0187     void *addr;         /* CPU-side address */
0188     unsigned int status;        /* Buffer status flags */
0189 };
0190 
0191 /* Internal channel */
0192 struct rcar_drif {
0193     struct rcar_drif_sdr *sdr;  /* Group device */
0194     struct platform_device *pdev;   /* Channel's pdev */
0195     void __iomem *base;     /* Base register address */
0196     resource_size_t start;      /* I/O resource offset */
0197     struct dma_chan *dmach;     /* Reserved DMA channel */
0198     struct clk *clk;        /* Module clock */
0199     struct rcar_drif_hwbuf buf[RCAR_DRIF_NUM_HWBUFS]; /* H/W bufs */
0200     dma_addr_t dma_handle;      /* Handle for all bufs */
0201     unsigned int num;       /* Channel number */
0202     bool acting_sdr;        /* Channel acting as SDR device */
0203 };
0204 
0205 /* DRIF V4L2 SDR */
0206 struct rcar_drif_sdr {
0207     struct device *dev;     /* Platform device */
0208     struct video_device *vdev;  /* V4L2 SDR device */
0209     struct v4l2_device v4l2_dev;    /* V4L2 device */
0210 
0211     /* Videobuf2 queue and queued buffers list */
0212     struct vb2_queue vb_queue;
0213     struct list_head queued_bufs;
0214     spinlock_t queued_bufs_lock;    /* Protects queued_bufs */
0215     spinlock_t dma_lock;        /* To serialize DMA cb of channels */
0216 
0217     struct mutex v4l2_mutex;    /* To serialize ioctls */
0218     struct mutex vb_queue_mutex;    /* To serialize streaming ioctls */
0219     struct v4l2_ctrl_handler ctrl_hdl;  /* SDR control handler */
0220     struct v4l2_async_notifier notifier;    /* For subdev (tuner) */
0221     struct rcar_drif_graph_ep ep;   /* Endpoint V4L2 async data */
0222 
0223     /* Current V4L2 SDR format ptr */
0224     const struct rcar_drif_format *fmt;
0225 
0226     /* Device tree SYNC properties */
0227     u32 mdr1;
0228 
0229     /* Internals */
0230     struct rcar_drif *ch[RCAR_DRIF_MAX_CHANNEL]; /* DRIFx0,1 */
0231     unsigned long hw_ch_mask;   /* Enabled channels per DT */
0232     unsigned long cur_ch_mask;  /* Used channels for an SDR FMT */
0233     u32 num_hw_ch;          /* Num of DT enabled channels */
0234     u32 num_cur_ch;         /* Num of used channels */
0235     u32 hwbuf_size;         /* Each DMA buffer size */
0236     u32 produced;           /* Buffers produced by sdr dev */
0237 };
0238 
0239 /* Register access functions */
0240 static void rcar_drif_write(struct rcar_drif *ch, u32 offset, u32 data)
0241 {
0242     writel(data, ch->base + offset);
0243 }
0244 
0245 static u32 rcar_drif_read(struct rcar_drif *ch, u32 offset)
0246 {
0247     return readl(ch->base + offset);
0248 }
0249 
0250 /* Release DMA channels */
0251 static void rcar_drif_release_dmachannels(struct rcar_drif_sdr *sdr)
0252 {
0253     unsigned int i;
0254 
0255     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
0256         if (sdr->ch[i]->dmach) {
0257             dma_release_channel(sdr->ch[i]->dmach);
0258             sdr->ch[i]->dmach = NULL;
0259         }
0260 }
0261 
0262 /* Allocate DMA channels */
0263 static int rcar_drif_alloc_dmachannels(struct rcar_drif_sdr *sdr)
0264 {
0265     struct dma_slave_config dma_cfg;
0266     unsigned int i;
0267     int ret;
0268 
0269     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0270         struct rcar_drif *ch = sdr->ch[i];
0271 
0272         ch->dmach = dma_request_chan(&ch->pdev->dev, "rx");
0273         if (IS_ERR(ch->dmach)) {
0274             ret = PTR_ERR(ch->dmach);
0275             if (ret != -EPROBE_DEFER)
0276                 rdrif_err(sdr,
0277                       "ch%u: dma channel req failed: %pe\n",
0278                       i, ch->dmach);
0279             ch->dmach = NULL;
0280             goto dmach_error;
0281         }
0282 
0283         /* Configure slave */
0284         memset(&dma_cfg, 0, sizeof(dma_cfg));
0285         dma_cfg.src_addr = (phys_addr_t)(ch->start + RCAR_DRIF_SIRFDR);
0286         dma_cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
0287         ret = dmaengine_slave_config(ch->dmach, &dma_cfg);
0288         if (ret) {
0289             rdrif_err(sdr, "ch%u: dma slave config failed\n", i);
0290             goto dmach_error;
0291         }
0292     }
0293     return 0;
0294 
0295 dmach_error:
0296     rcar_drif_release_dmachannels(sdr);
0297     return ret;
0298 }
0299 
0300 /* Release queued vb2 buffers */
0301 static void rcar_drif_release_queued_bufs(struct rcar_drif_sdr *sdr,
0302                       enum vb2_buffer_state state)
0303 {
0304     struct rcar_drif_frame_buf *fbuf, *tmp;
0305     unsigned long flags;
0306 
0307     spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
0308     list_for_each_entry_safe(fbuf, tmp, &sdr->queued_bufs, list) {
0309         list_del(&fbuf->list);
0310         vb2_buffer_done(&fbuf->vb.vb2_buf, state);
0311     }
0312     spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
0313 }
0314 
0315 /* Set MDR defaults */
0316 static inline void rcar_drif_set_mdr1(struct rcar_drif_sdr *sdr)
0317 {
0318     unsigned int i;
0319 
0320     /* Set defaults for enabled internal channels */
0321     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0322         /* Refer MSIOF section in manual for this register setting */
0323         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SITMDR1,
0324                 RCAR_DRIF_SITMDR1_PCON);
0325 
0326         /* Setup MDR1 value */
0327         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR1, sdr->mdr1);
0328 
0329         rdrif_dbg(sdr, "ch%u: mdr1 = 0x%08x",
0330               i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR1));
0331     }
0332 }
0333 
0334 /* Set DRIF receive format */
0335 static int rcar_drif_set_format(struct rcar_drif_sdr *sdr)
0336 {
0337     unsigned int i;
0338 
0339     rdrif_dbg(sdr, "setfmt: bitlen %u wdcnt %u num_ch %u\n",
0340           sdr->fmt->bitlen, sdr->fmt->wdcnt, sdr->fmt->num_ch);
0341 
0342     /* Sanity check */
0343     if (sdr->fmt->num_ch > sdr->num_cur_ch) {
0344         rdrif_err(sdr, "fmt num_ch %u cur_ch %u mismatch\n",
0345               sdr->fmt->num_ch, sdr->num_cur_ch);
0346         return -EINVAL;
0347     }
0348 
0349     /* Setup group, bitlen & wdcnt */
0350     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0351         u32 mdr;
0352 
0353         /* Two groups */
0354         mdr = RCAR_DRIF_MDR_GRPCNT(2) |
0355             RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
0356             RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
0357         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR2, mdr);
0358 
0359         mdr = RCAR_DRIF_MDR_BITLEN(sdr->fmt->bitlen) |
0360             RCAR_DRIF_MDR_WDCNT(sdr->fmt->wdcnt);
0361         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SIRMDR3, mdr);
0362 
0363         rdrif_dbg(sdr, "ch%u: new mdr[2,3] = 0x%08x, 0x%08x\n",
0364               i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR2),
0365               rcar_drif_read(sdr->ch[i], RCAR_DRIF_SIRMDR3));
0366     }
0367     return 0;
0368 }
0369 
0370 /* Release DMA buffers */
0371 static void rcar_drif_release_buf(struct rcar_drif_sdr *sdr)
0372 {
0373     unsigned int i;
0374 
0375     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0376         struct rcar_drif *ch = sdr->ch[i];
0377 
0378         /* First entry contains the dma buf ptr */
0379         if (ch->buf[0].addr) {
0380             dma_free_coherent(&ch->pdev->dev,
0381                 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
0382                 ch->buf[0].addr, ch->dma_handle);
0383             ch->buf[0].addr = NULL;
0384         }
0385     }
0386 }
0387 
0388 /* Request DMA buffers */
0389 static int rcar_drif_request_buf(struct rcar_drif_sdr *sdr)
0390 {
0391     int ret = -ENOMEM;
0392     unsigned int i, j;
0393     void *addr;
0394 
0395     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0396         struct rcar_drif *ch = sdr->ch[i];
0397 
0398         /* Allocate DMA buffers */
0399         addr = dma_alloc_coherent(&ch->pdev->dev,
0400                 sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
0401                 &ch->dma_handle, GFP_KERNEL);
0402         if (!addr) {
0403             rdrif_err(sdr,
0404             "ch%u: dma alloc failed. num hwbufs %u size %u\n",
0405             i, RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
0406             goto error;
0407         }
0408 
0409         /* Split the chunk and populate bufctxt */
0410         for (j = 0; j < RCAR_DRIF_NUM_HWBUFS; j++) {
0411             ch->buf[j].addr = addr + (j * sdr->hwbuf_size);
0412             ch->buf[j].status = 0;
0413         }
0414     }
0415     return 0;
0416 error:
0417     return ret;
0418 }
0419 
0420 /* Setup vb_queue minimum buffer requirements */
0421 static int rcar_drif_queue_setup(struct vb2_queue *vq,
0422             unsigned int *num_buffers, unsigned int *num_planes,
0423             unsigned int sizes[], struct device *alloc_devs[])
0424 {
0425     struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
0426 
0427     /* Need at least 16 buffers */
0428     if (vq->num_buffers + *num_buffers < 16)
0429         *num_buffers = 16 - vq->num_buffers;
0430 
0431     *num_planes = 1;
0432     sizes[0] = PAGE_ALIGN(sdr->fmt->buffersize);
0433     rdrif_dbg(sdr, "num_bufs %d sizes[0] %d\n", *num_buffers, sizes[0]);
0434 
0435     return 0;
0436 }
0437 
0438 /* Enqueue buffer */
0439 static void rcar_drif_buf_queue(struct vb2_buffer *vb)
0440 {
0441     struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
0442     struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vb->vb2_queue);
0443     struct rcar_drif_frame_buf *fbuf =
0444             container_of(vbuf, struct rcar_drif_frame_buf, vb);
0445     unsigned long flags;
0446 
0447     rdrif_dbg(sdr, "buf_queue idx %u\n", vb->index);
0448     spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
0449     list_add_tail(&fbuf->list, &sdr->queued_bufs);
0450     spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
0451 }
0452 
0453 /* Get a frame buf from list */
0454 static struct rcar_drif_frame_buf *
0455 rcar_drif_get_fbuf(struct rcar_drif_sdr *sdr)
0456 {
0457     struct rcar_drif_frame_buf *fbuf;
0458     unsigned long flags;
0459 
0460     spin_lock_irqsave(&sdr->queued_bufs_lock, flags);
0461     fbuf = list_first_entry_or_null(&sdr->queued_bufs, struct
0462                     rcar_drif_frame_buf, list);
0463     if (!fbuf) {
0464         /*
0465          * App is late in enqueing buffers. Samples lost & there will
0466          * be a gap in sequence number when app recovers
0467          */
0468         rdrif_dbg(sdr, "\napp late: prod %u\n", sdr->produced);
0469         spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
0470         return NULL;
0471     }
0472     list_del(&fbuf->list);
0473     spin_unlock_irqrestore(&sdr->queued_bufs_lock, flags);
0474 
0475     return fbuf;
0476 }
0477 
0478 /* Helpers to set/clear buf pair status */
0479 static inline bool rcar_drif_bufs_done(struct rcar_drif_hwbuf **buf)
0480 {
0481     return (buf[0]->status & buf[1]->status & RCAR_DRIF_BUF_DONE);
0482 }
0483 
0484 static inline bool rcar_drif_bufs_overflow(struct rcar_drif_hwbuf **buf)
0485 {
0486     return ((buf[0]->status | buf[1]->status) & RCAR_DRIF_BUF_OVERFLOW);
0487 }
0488 
0489 static inline void rcar_drif_bufs_clear(struct rcar_drif_hwbuf **buf,
0490                     unsigned int bit)
0491 {
0492     unsigned int i;
0493 
0494     for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
0495         buf[i]->status &= ~bit;
0496 }
0497 
0498 /* Channel DMA complete */
0499 static void rcar_drif_channel_complete(struct rcar_drif *ch, u32 idx)
0500 {
0501     u32 str;
0502 
0503     ch->buf[idx].status |= RCAR_DRIF_BUF_DONE;
0504 
0505     /* Check for DRIF errors */
0506     str = rcar_drif_read(ch, RCAR_DRIF_SISTR);
0507     if (unlikely(str & RCAR_DRIF_RFOVF)) {
0508         /* Writing the same clears it */
0509         rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
0510 
0511         /* Overflow: some samples are lost */
0512         ch->buf[idx].status |= RCAR_DRIF_BUF_OVERFLOW;
0513     }
0514 }
0515 
0516 /* DMA callback for each stage */
0517 static void rcar_drif_dma_complete(void *dma_async_param)
0518 {
0519     struct rcar_drif *ch = dma_async_param;
0520     struct rcar_drif_sdr *sdr = ch->sdr;
0521     struct rcar_drif_hwbuf *buf[RCAR_DRIF_MAX_CHANNEL];
0522     struct rcar_drif_frame_buf *fbuf;
0523     bool overflow = false;
0524     u32 idx, produced;
0525     unsigned int i;
0526 
0527     spin_lock(&sdr->dma_lock);
0528 
0529     /* DMA can be terminated while the callback was waiting on lock */
0530     if (!vb2_is_streaming(&sdr->vb_queue)) {
0531         spin_unlock(&sdr->dma_lock);
0532         return;
0533     }
0534 
0535     idx = sdr->produced % RCAR_DRIF_NUM_HWBUFS;
0536     rcar_drif_channel_complete(ch, idx);
0537 
0538     if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL) {
0539         buf[0] = ch->num ? to_rcar_drif_buf_pair(sdr, ch->num, idx) :
0540                 &ch->buf[idx];
0541         buf[1] = ch->num ? &ch->buf[idx] :
0542                 to_rcar_drif_buf_pair(sdr, ch->num, idx);
0543 
0544         /* Check if both DMA buffers are done */
0545         if (!rcar_drif_bufs_done(buf)) {
0546             spin_unlock(&sdr->dma_lock);
0547             return;
0548         }
0549 
0550         /* Clear buf done status */
0551         rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_DONE);
0552 
0553         if (rcar_drif_bufs_overflow(buf)) {
0554             overflow = true;
0555             /* Clear the flag in status */
0556             rcar_drif_bufs_clear(buf, RCAR_DRIF_BUF_OVERFLOW);
0557         }
0558     } else {
0559         buf[0] = &ch->buf[idx];
0560         if (buf[0]->status & RCAR_DRIF_BUF_OVERFLOW) {
0561             overflow = true;
0562             /* Clear the flag in status */
0563             buf[0]->status &= ~RCAR_DRIF_BUF_OVERFLOW;
0564         }
0565     }
0566 
0567     /* Buffer produced for consumption */
0568     produced = sdr->produced++;
0569     spin_unlock(&sdr->dma_lock);
0570 
0571     rdrif_dbg(sdr, "ch%u: prod %u\n", ch->num, produced);
0572 
0573     /* Get fbuf */
0574     fbuf = rcar_drif_get_fbuf(sdr);
0575     if (!fbuf)
0576         return;
0577 
0578     for (i = 0; i < RCAR_DRIF_MAX_CHANNEL; i++)
0579         memcpy(vb2_plane_vaddr(&fbuf->vb.vb2_buf, 0) +
0580                i * sdr->hwbuf_size, buf[i]->addr, sdr->hwbuf_size);
0581 
0582     fbuf->vb.field = V4L2_FIELD_NONE;
0583     fbuf->vb.sequence = produced;
0584     fbuf->vb.vb2_buf.timestamp = ktime_get_ns();
0585     vb2_set_plane_payload(&fbuf->vb.vb2_buf, 0, sdr->fmt->buffersize);
0586 
0587     /* Set error state on overflow */
0588     vb2_buffer_done(&fbuf->vb.vb2_buf,
0589             overflow ? VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
0590 }
0591 
0592 static int rcar_drif_qbuf(struct rcar_drif *ch)
0593 {
0594     struct rcar_drif_sdr *sdr = ch->sdr;
0595     dma_addr_t addr = ch->dma_handle;
0596     struct dma_async_tx_descriptor *rxd;
0597     dma_cookie_t cookie;
0598     int ret = -EIO;
0599 
0600     /* Setup cyclic DMA with given buffers */
0601     rxd = dmaengine_prep_dma_cyclic(ch->dmach, addr,
0602                     sdr->hwbuf_size * RCAR_DRIF_NUM_HWBUFS,
0603                     sdr->hwbuf_size, DMA_DEV_TO_MEM,
0604                     DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
0605     if (!rxd) {
0606         rdrif_err(sdr, "ch%u: prep dma cyclic failed\n", ch->num);
0607         return ret;
0608     }
0609 
0610     /* Submit descriptor */
0611     rxd->callback = rcar_drif_dma_complete;
0612     rxd->callback_param = ch;
0613     cookie = dmaengine_submit(rxd);
0614     if (dma_submit_error(cookie)) {
0615         rdrif_err(sdr, "ch%u: dma submit failed\n", ch->num);
0616         return ret;
0617     }
0618 
0619     dma_async_issue_pending(ch->dmach);
0620     return 0;
0621 }
0622 
0623 /* Enable reception */
0624 static int rcar_drif_enable_rx(struct rcar_drif_sdr *sdr)
0625 {
0626     unsigned int i;
0627     u32 ctr;
0628     int ret = -EINVAL;
0629 
0630     /*
0631      * When both internal channels are enabled, they can be synchronized
0632      * only by the master
0633      */
0634 
0635     /* Enable receive */
0636     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0637         ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
0638         ctr |= (RCAR_DRIF_SICTR_RX_RISING_EDGE |
0639              RCAR_DRIF_SICTR_RX_EN);
0640         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
0641     }
0642 
0643     /* Check receive enabled */
0644     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0645         ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
0646                 ctr, ctr & RCAR_DRIF_SICTR_RX_EN, 7, 100000);
0647         if (ret) {
0648             rdrif_err(sdr, "ch%u: rx en failed. ctr 0x%08x\n", i,
0649                   rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
0650             break;
0651         }
0652     }
0653     return ret;
0654 }
0655 
0656 /* Disable reception */
0657 static void rcar_drif_disable_rx(struct rcar_drif_sdr *sdr)
0658 {
0659     unsigned int i;
0660     u32 ctr;
0661     int ret;
0662 
0663     /* Disable receive */
0664     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0665         ctr = rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR);
0666         ctr &= ~RCAR_DRIF_SICTR_RX_EN;
0667         rcar_drif_write(sdr->ch[i], RCAR_DRIF_SICTR, ctr);
0668     }
0669 
0670     /* Check receive disabled */
0671     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0672         ret = readl_poll_timeout(sdr->ch[i]->base + RCAR_DRIF_SICTR,
0673                 ctr, !(ctr & RCAR_DRIF_SICTR_RX_EN), 7, 100000);
0674         if (ret)
0675             dev_warn(&sdr->vdev->dev,
0676             "ch%u: failed to disable rx. ctr 0x%08x\n",
0677             i, rcar_drif_read(sdr->ch[i], RCAR_DRIF_SICTR));
0678     }
0679 }
0680 
0681 /* Stop channel */
0682 static void rcar_drif_stop_channel(struct rcar_drif *ch)
0683 {
0684     /* Disable DMA receive interrupt */
0685     rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00000000);
0686 
0687     /* Terminate all DMA transfers */
0688     dmaengine_terminate_sync(ch->dmach);
0689 }
0690 
0691 /* Stop receive operation */
0692 static void rcar_drif_stop(struct rcar_drif_sdr *sdr)
0693 {
0694     unsigned int i;
0695 
0696     /* Disable Rx */
0697     rcar_drif_disable_rx(sdr);
0698 
0699     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
0700         rcar_drif_stop_channel(sdr->ch[i]);
0701 }
0702 
0703 /* Start channel */
0704 static int rcar_drif_start_channel(struct rcar_drif *ch)
0705 {
0706     struct rcar_drif_sdr *sdr = ch->sdr;
0707     u32 ctr, str;
0708     int ret;
0709 
0710     /* Reset receive */
0711     rcar_drif_write(ch, RCAR_DRIF_SICTR, RCAR_DRIF_SICTR_RESET);
0712     ret = readl_poll_timeout(ch->base + RCAR_DRIF_SICTR, ctr,
0713                  !(ctr & RCAR_DRIF_SICTR_RESET), 7, 100000);
0714     if (ret) {
0715         rdrif_err(sdr, "ch%u: failed to reset rx. ctr 0x%08x\n",
0716               ch->num, rcar_drif_read(ch, RCAR_DRIF_SICTR));
0717         return ret;
0718     }
0719 
0720     /* Queue buffers for DMA */
0721     ret = rcar_drif_qbuf(ch);
0722     if (ret)
0723         return ret;
0724 
0725     /* Clear status register flags */
0726     str = RCAR_DRIF_RFFUL | RCAR_DRIF_REOF | RCAR_DRIF_RFSERR |
0727         RCAR_DRIF_RFUDF | RCAR_DRIF_RFOVF;
0728     rcar_drif_write(ch, RCAR_DRIF_SISTR, str);
0729 
0730     /* Enable DMA receive interrupt */
0731     rcar_drif_write(ch, RCAR_DRIF_SIIER, 0x00009000);
0732 
0733     return ret;
0734 }
0735 
0736 /* Start receive operation */
0737 static int rcar_drif_start(struct rcar_drif_sdr *sdr)
0738 {
0739     unsigned long enabled = 0;
0740     unsigned int i;
0741     int ret;
0742 
0743     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0744         ret = rcar_drif_start_channel(sdr->ch[i]);
0745         if (ret)
0746             goto start_error;
0747         enabled |= BIT(i);
0748     }
0749 
0750     ret = rcar_drif_enable_rx(sdr);
0751     if (ret)
0752         goto enable_error;
0753 
0754     sdr->produced = 0;
0755     return ret;
0756 
0757 enable_error:
0758     rcar_drif_disable_rx(sdr);
0759 start_error:
0760     for_each_rcar_drif_channel(i, &enabled)
0761         rcar_drif_stop_channel(sdr->ch[i]);
0762 
0763     return ret;
0764 }
0765 
0766 /* Start streaming */
0767 static int rcar_drif_start_streaming(struct vb2_queue *vq, unsigned int count)
0768 {
0769     struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
0770     unsigned long enabled = 0;
0771     unsigned int i;
0772     int ret;
0773 
0774     mutex_lock(&sdr->v4l2_mutex);
0775 
0776     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask) {
0777         ret = clk_prepare_enable(sdr->ch[i]->clk);
0778         if (ret)
0779             goto error;
0780         enabled |= BIT(i);
0781     }
0782 
0783     /* Set default MDRx settings */
0784     rcar_drif_set_mdr1(sdr);
0785 
0786     /* Set new format */
0787     ret = rcar_drif_set_format(sdr);
0788     if (ret)
0789         goto error;
0790 
0791     if (sdr->num_cur_ch == RCAR_DRIF_MAX_CHANNEL)
0792         sdr->hwbuf_size = sdr->fmt->buffersize / RCAR_DRIF_MAX_CHANNEL;
0793     else
0794         sdr->hwbuf_size = sdr->fmt->buffersize;
0795 
0796     rdrif_dbg(sdr, "num hwbufs %u, hwbuf_size %u\n",
0797         RCAR_DRIF_NUM_HWBUFS, sdr->hwbuf_size);
0798 
0799     /* Alloc DMA channel */
0800     ret = rcar_drif_alloc_dmachannels(sdr);
0801     if (ret)
0802         goto error;
0803 
0804     /* Request buffers */
0805     ret = rcar_drif_request_buf(sdr);
0806     if (ret)
0807         goto error;
0808 
0809     /* Start Rx */
0810     ret = rcar_drif_start(sdr);
0811     if (ret)
0812         goto error;
0813 
0814     mutex_unlock(&sdr->v4l2_mutex);
0815 
0816     return ret;
0817 
0818 error:
0819     rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_QUEUED);
0820     rcar_drif_release_buf(sdr);
0821     rcar_drif_release_dmachannels(sdr);
0822     for_each_rcar_drif_channel(i, &enabled)
0823         clk_disable_unprepare(sdr->ch[i]->clk);
0824 
0825     mutex_unlock(&sdr->v4l2_mutex);
0826 
0827     return ret;
0828 }
0829 
0830 /* Stop streaming */
0831 static void rcar_drif_stop_streaming(struct vb2_queue *vq)
0832 {
0833     struct rcar_drif_sdr *sdr = vb2_get_drv_priv(vq);
0834     unsigned int i;
0835 
0836     mutex_lock(&sdr->v4l2_mutex);
0837 
0838     /* Stop hardware streaming */
0839     rcar_drif_stop(sdr);
0840 
0841     /* Return all queued buffers to vb2 */
0842     rcar_drif_release_queued_bufs(sdr, VB2_BUF_STATE_ERROR);
0843 
0844     /* Release buf */
0845     rcar_drif_release_buf(sdr);
0846 
0847     /* Release DMA channel resources */
0848     rcar_drif_release_dmachannels(sdr);
0849 
0850     for_each_rcar_drif_channel(i, &sdr->cur_ch_mask)
0851         clk_disable_unprepare(sdr->ch[i]->clk);
0852 
0853     mutex_unlock(&sdr->v4l2_mutex);
0854 }
0855 
0856 /* Vb2 ops */
0857 static const struct vb2_ops rcar_drif_vb2_ops = {
0858     .queue_setup            = rcar_drif_queue_setup,
0859     .buf_queue              = rcar_drif_buf_queue,
0860     .start_streaming        = rcar_drif_start_streaming,
0861     .stop_streaming         = rcar_drif_stop_streaming,
0862     .wait_prepare       = vb2_ops_wait_prepare,
0863     .wait_finish        = vb2_ops_wait_finish,
0864 };
0865 
0866 static int rcar_drif_querycap(struct file *file, void *fh,
0867                   struct v4l2_capability *cap)
0868 {
0869     struct rcar_drif_sdr *sdr = video_drvdata(file);
0870 
0871     strscpy(cap->driver, KBUILD_MODNAME, sizeof(cap->driver));
0872     strscpy(cap->card, sdr->vdev->name, sizeof(cap->card));
0873     snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
0874          sdr->vdev->name);
0875 
0876     return 0;
0877 }
0878 
0879 static int rcar_drif_set_default_format(struct rcar_drif_sdr *sdr)
0880 {
0881     unsigned int i;
0882 
0883     for (i = 0; i < ARRAY_SIZE(formats); i++) {
0884         /* Matching fmt based on required channels is set as default */
0885         if (sdr->num_hw_ch == formats[i].num_ch) {
0886             sdr->fmt = &formats[i];
0887             sdr->cur_ch_mask = sdr->hw_ch_mask;
0888             sdr->num_cur_ch = sdr->num_hw_ch;
0889             dev_dbg(sdr->dev, "default fmt[%u]: mask %lu num %u\n",
0890                 i, sdr->cur_ch_mask, sdr->num_cur_ch);
0891             return 0;
0892         }
0893     }
0894     return -EINVAL;
0895 }
0896 
0897 static int rcar_drif_enum_fmt_sdr_cap(struct file *file, void *priv,
0898                       struct v4l2_fmtdesc *f)
0899 {
0900     if (f->index >= ARRAY_SIZE(formats))
0901         return -EINVAL;
0902 
0903     f->pixelformat = formats[f->index].pixelformat;
0904 
0905     return 0;
0906 }
0907 
0908 static int rcar_drif_g_fmt_sdr_cap(struct file *file, void *priv,
0909                    struct v4l2_format *f)
0910 {
0911     struct rcar_drif_sdr *sdr = video_drvdata(file);
0912 
0913     f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
0914     f->fmt.sdr.buffersize = sdr->fmt->buffersize;
0915 
0916     return 0;
0917 }
0918 
0919 static int rcar_drif_s_fmt_sdr_cap(struct file *file, void *priv,
0920                    struct v4l2_format *f)
0921 {
0922     struct rcar_drif_sdr *sdr = video_drvdata(file);
0923     struct vb2_queue *q = &sdr->vb_queue;
0924     unsigned int i;
0925 
0926     if (vb2_is_busy(q))
0927         return -EBUSY;
0928 
0929     for (i = 0; i < ARRAY_SIZE(formats); i++) {
0930         if (formats[i].pixelformat == f->fmt.sdr.pixelformat)
0931             break;
0932     }
0933 
0934     if (i == ARRAY_SIZE(formats))
0935         i = 0;      /* Set the 1st format as default on no match */
0936 
0937     sdr->fmt = &formats[i];
0938     f->fmt.sdr.pixelformat = sdr->fmt->pixelformat;
0939     f->fmt.sdr.buffersize = formats[i].buffersize;
0940     memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
0941 
0942     /*
0943      * If a format demands one channel only out of two
0944      * enabled channels, pick the 0th channel.
0945      */
0946     if (formats[i].num_ch < sdr->num_hw_ch) {
0947         sdr->cur_ch_mask = BIT(0);
0948         sdr->num_cur_ch = formats[i].num_ch;
0949     } else {
0950         sdr->cur_ch_mask = sdr->hw_ch_mask;
0951         sdr->num_cur_ch = sdr->num_hw_ch;
0952     }
0953 
0954     rdrif_dbg(sdr, "cur: idx %u mask %lu num %u\n",
0955           i, sdr->cur_ch_mask, sdr->num_cur_ch);
0956 
0957     return 0;
0958 }
0959 
0960 static int rcar_drif_try_fmt_sdr_cap(struct file *file, void *priv,
0961                      struct v4l2_format *f)
0962 {
0963     unsigned int i;
0964 
0965     for (i = 0; i < ARRAY_SIZE(formats); i++) {
0966         if (formats[i].pixelformat == f->fmt.sdr.pixelformat) {
0967             f->fmt.sdr.buffersize = formats[i].buffersize;
0968             return 0;
0969         }
0970     }
0971 
0972     f->fmt.sdr.pixelformat = formats[0].pixelformat;
0973     f->fmt.sdr.buffersize = formats[0].buffersize;
0974     memset(f->fmt.sdr.reserved, 0, sizeof(f->fmt.sdr.reserved));
0975 
0976     return 0;
0977 }
0978 
0979 /* Tuner subdev ioctls */
0980 static int rcar_drif_enum_freq_bands(struct file *file, void *priv,
0981                      struct v4l2_frequency_band *band)
0982 {
0983     struct rcar_drif_sdr *sdr = video_drvdata(file);
0984 
0985     return v4l2_subdev_call(sdr->ep.subdev, tuner, enum_freq_bands, band);
0986 }
0987 
0988 static int rcar_drif_g_frequency(struct file *file, void *priv,
0989                  struct v4l2_frequency *f)
0990 {
0991     struct rcar_drif_sdr *sdr = video_drvdata(file);
0992 
0993     return v4l2_subdev_call(sdr->ep.subdev, tuner, g_frequency, f);
0994 }
0995 
0996 static int rcar_drif_s_frequency(struct file *file, void *priv,
0997                  const struct v4l2_frequency *f)
0998 {
0999     struct rcar_drif_sdr *sdr = video_drvdata(file);
1000 
1001     return v4l2_subdev_call(sdr->ep.subdev, tuner, s_frequency, f);
1002 }
1003 
1004 static int rcar_drif_g_tuner(struct file *file, void *priv,
1005                  struct v4l2_tuner *vt)
1006 {
1007     struct rcar_drif_sdr *sdr = video_drvdata(file);
1008 
1009     return v4l2_subdev_call(sdr->ep.subdev, tuner, g_tuner, vt);
1010 }
1011 
1012 static int rcar_drif_s_tuner(struct file *file, void *priv,
1013                  const struct v4l2_tuner *vt)
1014 {
1015     struct rcar_drif_sdr *sdr = video_drvdata(file);
1016 
1017     return v4l2_subdev_call(sdr->ep.subdev, tuner, s_tuner, vt);
1018 }
1019 
1020 static const struct v4l2_ioctl_ops rcar_drif_ioctl_ops = {
1021     .vidioc_querycap          = rcar_drif_querycap,
1022 
1023     .vidioc_enum_fmt_sdr_cap  = rcar_drif_enum_fmt_sdr_cap,
1024     .vidioc_g_fmt_sdr_cap     = rcar_drif_g_fmt_sdr_cap,
1025     .vidioc_s_fmt_sdr_cap     = rcar_drif_s_fmt_sdr_cap,
1026     .vidioc_try_fmt_sdr_cap   = rcar_drif_try_fmt_sdr_cap,
1027 
1028     .vidioc_reqbufs           = vb2_ioctl_reqbufs,
1029     .vidioc_create_bufs       = vb2_ioctl_create_bufs,
1030     .vidioc_prepare_buf       = vb2_ioctl_prepare_buf,
1031     .vidioc_querybuf          = vb2_ioctl_querybuf,
1032     .vidioc_qbuf              = vb2_ioctl_qbuf,
1033     .vidioc_dqbuf             = vb2_ioctl_dqbuf,
1034 
1035     .vidioc_streamon          = vb2_ioctl_streamon,
1036     .vidioc_streamoff         = vb2_ioctl_streamoff,
1037 
1038     .vidioc_s_frequency       = rcar_drif_s_frequency,
1039     .vidioc_g_frequency       = rcar_drif_g_frequency,
1040     .vidioc_s_tuner       = rcar_drif_s_tuner,
1041     .vidioc_g_tuner       = rcar_drif_g_tuner,
1042     .vidioc_enum_freq_bands   = rcar_drif_enum_freq_bands,
1043     .vidioc_subscribe_event   = v4l2_ctrl_subscribe_event,
1044     .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
1045     .vidioc_log_status        = v4l2_ctrl_log_status,
1046 };
1047 
1048 static const struct v4l2_file_operations rcar_drif_fops = {
1049     .owner                    = THIS_MODULE,
1050     .open                     = v4l2_fh_open,
1051     .release                  = vb2_fop_release,
1052     .read                     = vb2_fop_read,
1053     .poll                     = vb2_fop_poll,
1054     .mmap                     = vb2_fop_mmap,
1055     .unlocked_ioctl           = video_ioctl2,
1056 };
1057 
1058 static int rcar_drif_sdr_register(struct rcar_drif_sdr *sdr)
1059 {
1060     int ret;
1061 
1062     /* Init video_device structure */
1063     sdr->vdev = video_device_alloc();
1064     if (!sdr->vdev)
1065         return -ENOMEM;
1066 
1067     snprintf(sdr->vdev->name, sizeof(sdr->vdev->name), "R-Car DRIF");
1068     sdr->vdev->fops = &rcar_drif_fops;
1069     sdr->vdev->ioctl_ops = &rcar_drif_ioctl_ops;
1070     sdr->vdev->release = video_device_release;
1071     sdr->vdev->lock = &sdr->v4l2_mutex;
1072     sdr->vdev->queue = &sdr->vb_queue;
1073     sdr->vdev->queue->lock = &sdr->vb_queue_mutex;
1074     sdr->vdev->ctrl_handler = &sdr->ctrl_hdl;
1075     sdr->vdev->v4l2_dev = &sdr->v4l2_dev;
1076     sdr->vdev->device_caps = V4L2_CAP_SDR_CAPTURE | V4L2_CAP_TUNER |
1077         V4L2_CAP_STREAMING | V4L2_CAP_READWRITE;
1078     video_set_drvdata(sdr->vdev, sdr);
1079 
1080     /* Register V4L2 SDR device */
1081     ret = video_register_device(sdr->vdev, VFL_TYPE_SDR, -1);
1082     if (ret) {
1083         video_device_release(sdr->vdev);
1084         sdr->vdev = NULL;
1085         dev_err(sdr->dev, "failed video_register_device (%d)\n", ret);
1086     }
1087 
1088     return ret;
1089 }
1090 
1091 static void rcar_drif_sdr_unregister(struct rcar_drif_sdr *sdr)
1092 {
1093     video_unregister_device(sdr->vdev);
1094     sdr->vdev = NULL;
1095 }
1096 
1097 /* Sub-device bound callback */
1098 static int rcar_drif_notify_bound(struct v4l2_async_notifier *notifier,
1099                    struct v4l2_subdev *subdev,
1100                    struct v4l2_async_subdev *asd)
1101 {
1102     struct rcar_drif_sdr *sdr =
1103         container_of(notifier, struct rcar_drif_sdr, notifier);
1104 
1105     v4l2_set_subdev_hostdata(subdev, sdr);
1106     sdr->ep.subdev = subdev;
1107     rdrif_dbg(sdr, "bound asd %s\n", subdev->name);
1108 
1109     return 0;
1110 }
1111 
1112 /* Sub-device unbind callback */
1113 static void rcar_drif_notify_unbind(struct v4l2_async_notifier *notifier,
1114                    struct v4l2_subdev *subdev,
1115                    struct v4l2_async_subdev *asd)
1116 {
1117     struct rcar_drif_sdr *sdr =
1118         container_of(notifier, struct rcar_drif_sdr, notifier);
1119 
1120     if (sdr->ep.subdev != subdev) {
1121         rdrif_err(sdr, "subdev %s is not bound\n", subdev->name);
1122         return;
1123     }
1124 
1125     /* Free ctrl handler if initialized */
1126     v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1127     sdr->v4l2_dev.ctrl_handler = NULL;
1128     sdr->ep.subdev = NULL;
1129 
1130     rcar_drif_sdr_unregister(sdr);
1131     rdrif_dbg(sdr, "unbind asd %s\n", subdev->name);
1132 }
1133 
1134 /* Sub-device registered notification callback */
1135 static int rcar_drif_notify_complete(struct v4l2_async_notifier *notifier)
1136 {
1137     struct rcar_drif_sdr *sdr =
1138         container_of(notifier, struct rcar_drif_sdr, notifier);
1139     int ret;
1140 
1141     /*
1142      * The subdev tested at this point uses 4 controls. Using 10 as a worst
1143      * case scenario hint. When less controls are needed there will be some
1144      * unused memory and when more controls are needed the framework uses
1145      * hash to manage controls within this number.
1146      */
1147     ret = v4l2_ctrl_handler_init(&sdr->ctrl_hdl, 10);
1148     if (ret)
1149         return -ENOMEM;
1150 
1151     sdr->v4l2_dev.ctrl_handler = &sdr->ctrl_hdl;
1152     ret = v4l2_device_register_subdev_nodes(&sdr->v4l2_dev);
1153     if (ret) {
1154         rdrif_err(sdr, "failed: register subdev nodes ret %d\n", ret);
1155         goto error;
1156     }
1157 
1158     ret = v4l2_ctrl_add_handler(&sdr->ctrl_hdl,
1159                     sdr->ep.subdev->ctrl_handler, NULL, true);
1160     if (ret) {
1161         rdrif_err(sdr, "failed: ctrl add hdlr ret %d\n", ret);
1162         goto error;
1163     }
1164 
1165     ret = rcar_drif_sdr_register(sdr);
1166     if (ret)
1167         goto error;
1168 
1169     return ret;
1170 
1171 error:
1172     v4l2_ctrl_handler_free(&sdr->ctrl_hdl);
1173 
1174     return ret;
1175 }
1176 
1177 static const struct v4l2_async_notifier_operations rcar_drif_notify_ops = {
1178     .bound = rcar_drif_notify_bound,
1179     .unbind = rcar_drif_notify_unbind,
1180     .complete = rcar_drif_notify_complete,
1181 };
1182 
1183 /* Read endpoint properties */
1184 static void rcar_drif_get_ep_properties(struct rcar_drif_sdr *sdr,
1185                     struct fwnode_handle *fwnode)
1186 {
1187     u32 val;
1188 
1189     /* Set the I2S defaults for SIRMDR1*/
1190     sdr->mdr1 = RCAR_DRIF_SIRMDR1_SYNCMD_LR | RCAR_DRIF_SIRMDR1_MSB_FIRST |
1191         RCAR_DRIF_SIRMDR1_DTDL_1 | RCAR_DRIF_SIRMDR1_SYNCDL_0;
1192 
1193     /* Parse sync polarity from endpoint */
1194     if (!fwnode_property_read_u32(fwnode, "sync-active", &val))
1195         sdr->mdr1 |= val ? RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH :
1196             RCAR_DRIF_SIRMDR1_SYNCAC_POL_LOW;
1197     else
1198         sdr->mdr1 |= RCAR_DRIF_SIRMDR1_SYNCAC_POL_HIGH; /* default */
1199 
1200     dev_dbg(sdr->dev, "mdr1 0x%08x\n", sdr->mdr1);
1201 }
1202 
1203 /* Parse sub-devs (tuner) to find a matching device */
1204 static int rcar_drif_parse_subdevs(struct rcar_drif_sdr *sdr)
1205 {
1206     struct v4l2_async_notifier *notifier = &sdr->notifier;
1207     struct fwnode_handle *fwnode, *ep;
1208     struct v4l2_async_subdev *asd;
1209 
1210     v4l2_async_nf_init(notifier);
1211 
1212     ep = fwnode_graph_get_next_endpoint(of_fwnode_handle(sdr->dev->of_node),
1213                         NULL);
1214     if (!ep)
1215         return 0;
1216 
1217     /* Get the endpoint properties */
1218     rcar_drif_get_ep_properties(sdr, ep);
1219 
1220     fwnode = fwnode_graph_get_remote_port_parent(ep);
1221     fwnode_handle_put(ep);
1222     if (!fwnode) {
1223         dev_warn(sdr->dev, "bad remote port parent\n");
1224         return -EINVAL;
1225     }
1226 
1227     asd = v4l2_async_nf_add_fwnode(notifier, fwnode,
1228                        struct v4l2_async_subdev);
1229     fwnode_handle_put(fwnode);
1230     if (IS_ERR(asd))
1231         return PTR_ERR(asd);
1232 
1233     return 0;
1234 }
1235 
1236 /* Check if the given device is the primary bond */
1237 static bool rcar_drif_primary_bond(struct platform_device *pdev)
1238 {
1239     return of_property_read_bool(pdev->dev.of_node, "renesas,primary-bond");
1240 }
1241 
1242 /* Check if both devices of the bond are enabled */
1243 static struct device_node *rcar_drif_bond_enabled(struct platform_device *p)
1244 {
1245     struct device_node *np;
1246 
1247     np = of_parse_phandle(p->dev.of_node, "renesas,bonding", 0);
1248     if (np && of_device_is_available(np))
1249         return np;
1250 
1251     return NULL;
1252 }
1253 
1254 /* Check if the bonded device is probed */
1255 static int rcar_drif_bond_available(struct rcar_drif_sdr *sdr,
1256                     struct device_node *np)
1257 {
1258     struct platform_device *pdev;
1259     struct rcar_drif *ch;
1260     int ret = 0;
1261 
1262     pdev = of_find_device_by_node(np);
1263     if (!pdev) {
1264         dev_err(sdr->dev, "failed to get bonded device from node\n");
1265         return -ENODEV;
1266     }
1267 
1268     device_lock(&pdev->dev);
1269     ch = platform_get_drvdata(pdev);
1270     if (ch) {
1271         /* Update sdr data in the bonded device */
1272         ch->sdr = sdr;
1273 
1274         /* Update sdr with bonded device data */
1275         sdr->ch[ch->num] = ch;
1276         sdr->hw_ch_mask |= BIT(ch->num);
1277     } else {
1278         /* Defer */
1279         dev_info(sdr->dev, "defer probe\n");
1280         ret = -EPROBE_DEFER;
1281     }
1282     device_unlock(&pdev->dev);
1283 
1284     put_device(&pdev->dev);
1285 
1286     return ret;
1287 }
1288 
1289 /* V4L2 SDR device probe */
1290 static int rcar_drif_sdr_probe(struct rcar_drif_sdr *sdr)
1291 {
1292     int ret;
1293 
1294     /* Validate any supported format for enabled channels */
1295     ret = rcar_drif_set_default_format(sdr);
1296     if (ret) {
1297         dev_err(sdr->dev, "failed to set default format\n");
1298         return ret;
1299     }
1300 
1301     /* Set defaults */
1302     sdr->hwbuf_size = RCAR_DRIF_DEFAULT_HWBUF_SIZE;
1303 
1304     mutex_init(&sdr->v4l2_mutex);
1305     mutex_init(&sdr->vb_queue_mutex);
1306     spin_lock_init(&sdr->queued_bufs_lock);
1307     spin_lock_init(&sdr->dma_lock);
1308     INIT_LIST_HEAD(&sdr->queued_bufs);
1309 
1310     /* Init videobuf2 queue structure */
1311     sdr->vb_queue.type = V4L2_BUF_TYPE_SDR_CAPTURE;
1312     sdr->vb_queue.io_modes = VB2_READ | VB2_MMAP | VB2_DMABUF;
1313     sdr->vb_queue.drv_priv = sdr;
1314     sdr->vb_queue.buf_struct_size = sizeof(struct rcar_drif_frame_buf);
1315     sdr->vb_queue.ops = &rcar_drif_vb2_ops;
1316     sdr->vb_queue.mem_ops = &vb2_vmalloc_memops;
1317     sdr->vb_queue.timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
1318 
1319     /* Init videobuf2 queue */
1320     ret = vb2_queue_init(&sdr->vb_queue);
1321     if (ret) {
1322         dev_err(sdr->dev, "failed: vb2_queue_init ret %d\n", ret);
1323         return ret;
1324     }
1325 
1326     /* Register the v4l2_device */
1327     ret = v4l2_device_register(sdr->dev, &sdr->v4l2_dev);
1328     if (ret) {
1329         dev_err(sdr->dev, "failed: v4l2_device_register ret %d\n", ret);
1330         return ret;
1331     }
1332 
1333     /*
1334      * Parse subdevs after v4l2_device_register because if the subdev
1335      * is already probed, bound and complete will be called immediately
1336      */
1337     ret = rcar_drif_parse_subdevs(sdr);
1338     if (ret)
1339         goto error;
1340 
1341     sdr->notifier.ops = &rcar_drif_notify_ops;
1342 
1343     /* Register notifier */
1344     ret = v4l2_async_nf_register(&sdr->v4l2_dev, &sdr->notifier);
1345     if (ret < 0) {
1346         dev_err(sdr->dev, "failed: notifier register ret %d\n", ret);
1347         goto cleanup;
1348     }
1349 
1350     return ret;
1351 
1352 cleanup:
1353     v4l2_async_nf_cleanup(&sdr->notifier);
1354 error:
1355     v4l2_device_unregister(&sdr->v4l2_dev);
1356 
1357     return ret;
1358 }
1359 
1360 /* V4L2 SDR device remove */
1361 static void rcar_drif_sdr_remove(struct rcar_drif_sdr *sdr)
1362 {
1363     v4l2_async_nf_unregister(&sdr->notifier);
1364     v4l2_async_nf_cleanup(&sdr->notifier);
1365     v4l2_device_unregister(&sdr->v4l2_dev);
1366 }
1367 
1368 /* DRIF channel probe */
1369 static int rcar_drif_probe(struct platform_device *pdev)
1370 {
1371     struct rcar_drif_sdr *sdr;
1372     struct device_node *np;
1373     struct rcar_drif *ch;
1374     struct resource *res;
1375     int ret;
1376 
1377     /* Reserve memory for enabled channel */
1378     ch = devm_kzalloc(&pdev->dev, sizeof(*ch), GFP_KERNEL);
1379     if (!ch)
1380         return -ENOMEM;
1381 
1382     ch->pdev = pdev;
1383 
1384     /* Module clock */
1385     ch->clk = devm_clk_get(&pdev->dev, "fck");
1386     if (IS_ERR(ch->clk)) {
1387         ret = PTR_ERR(ch->clk);
1388         dev_err(&pdev->dev, "clk get failed (%d)\n", ret);
1389         return ret;
1390     }
1391 
1392     /* Register map */
1393     ch->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1394     if (IS_ERR(ch->base))
1395         return PTR_ERR(ch->base);
1396 
1397     ch->start = res->start;
1398     platform_set_drvdata(pdev, ch);
1399 
1400     /* Check if both channels of the bond are enabled */
1401     np = rcar_drif_bond_enabled(pdev);
1402     if (np) {
1403         /* Check if current channel acting as primary-bond */
1404         if (!rcar_drif_primary_bond(pdev)) {
1405             ch->num = 1;    /* Primary bond is channel 0 always */
1406             of_node_put(np);
1407             return 0;
1408         }
1409     }
1410 
1411     /* Reserve memory for SDR structure */
1412     sdr = devm_kzalloc(&pdev->dev, sizeof(*sdr), GFP_KERNEL);
1413     if (!sdr) {
1414         of_node_put(np);
1415         return -ENOMEM;
1416     }
1417     ch->sdr = sdr;
1418     sdr->dev = &pdev->dev;
1419 
1420     /* Establish links between SDR and channel(s) */
1421     sdr->ch[ch->num] = ch;
1422     sdr->hw_ch_mask = BIT(ch->num);
1423     if (np) {
1424         /* Check if bonded device is ready */
1425         ret = rcar_drif_bond_available(sdr, np);
1426         of_node_put(np);
1427         if (ret)
1428             return ret;
1429     }
1430     sdr->num_hw_ch = hweight_long(sdr->hw_ch_mask);
1431 
1432     return rcar_drif_sdr_probe(sdr);
1433 }
1434 
1435 /* DRIF channel remove */
1436 static int rcar_drif_remove(struct platform_device *pdev)
1437 {
1438     struct rcar_drif *ch = platform_get_drvdata(pdev);
1439     struct rcar_drif_sdr *sdr = ch->sdr;
1440 
1441     /* Channel 0 will be the SDR instance */
1442     if (ch->num)
1443         return 0;
1444 
1445     /* SDR instance */
1446     rcar_drif_sdr_remove(sdr);
1447 
1448     return 0;
1449 }
1450 
1451 /* FIXME: Implement suspend/resume support */
1452 static int __maybe_unused rcar_drif_suspend(struct device *dev)
1453 {
1454     return 0;
1455 }
1456 
1457 static int __maybe_unused rcar_drif_resume(struct device *dev)
1458 {
1459     return 0;
1460 }
1461 
1462 static SIMPLE_DEV_PM_OPS(rcar_drif_pm_ops, rcar_drif_suspend,
1463              rcar_drif_resume);
1464 
1465 static const struct of_device_id rcar_drif_of_table[] = {
1466     { .compatible = "renesas,rcar-gen3-drif" },
1467     { }
1468 };
1469 MODULE_DEVICE_TABLE(of, rcar_drif_of_table);
1470 
1471 #define RCAR_DRIF_DRV_NAME "rcar_drif"
1472 static struct platform_driver rcar_drif_driver = {
1473     .driver = {
1474         .name = RCAR_DRIF_DRV_NAME,
1475         .of_match_table = rcar_drif_of_table,
1476         .pm = &rcar_drif_pm_ops,
1477         },
1478     .probe = rcar_drif_probe,
1479     .remove = rcar_drif_remove,
1480 };
1481 
1482 module_platform_driver(rcar_drif_driver);
1483 
1484 MODULE_DESCRIPTION("Renesas R-Car Gen3 DRIF driver");
1485 MODULE_ALIAS("platform:" RCAR_DRIF_DRV_NAME);
1486 MODULE_LICENSE("GPL");
1487 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
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