platform/allegro-dvt/nal-hevc.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) 2019-2020 Pengutronix, Michael Tretter <kernel@pengutronix.de>
0004  *
0005  * Convert NAL units between raw byte sequence payloads (RBSP) and C structs.
0006  *
0007  * The conversion is defined in "ITU-T Rec. H.265 (02/2018) high efficiency
0008  * video coding". Decoder drivers may use the parser to parse RBSP from
0009  * encoded streams and configure the hardware, if the hardware is not able to
0010  * parse RBSP itself. Encoder drivers may use the generator to generate the
0011  * RBSP for VPS/SPS/PPS nal units and add them to the encoded stream if the
0012  * hardware does not generate the units.
0013  */
0014
0015 #include <linux/kernel.h>
0016 #include <linux/types.h>
0017 #include <linux/string.h>
0018 #include <linux/v4l2-controls.h>
0019
0020 #include <linux/device.h>
0021 #include <linux/export.h>
0022 #include <linux/log2.h>
0023
0024 #include "nal-hevc.h"
0025 #include "nal-rbsp.h"
0026
0027 /*
0028  * See Rec. ITU-T H.265 (02/2018) Table 7-1 - NAL unit type codes and NAL unit
0029  * type classes
0030  */
0031 enum nal_unit_type {
0032     VPS_NUT = 32,
0033     SPS_NUT = 33,
0034     PPS_NUT = 34,
0035     FD_NUT = 38,
0036 };
0037
0038 static void nal_hevc_write_start_code_prefix(struct rbsp *rbsp)
0039 {
0040     u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8);
0041     int i = 4;
0042
0043     if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) {
0044         rbsp->error = -EINVAL;
0045         return;
0046     }
0047
0048     p[0] = 0x00;
0049     p[1] = 0x00;
0050     p[2] = 0x00;
0051     p[3] = 0x01;
0052
0053     rbsp->pos += i * 8;
0054 }
0055
0056 static void nal_hevc_read_start_code_prefix(struct rbsp *rbsp)
0057 {
0058     u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8);
0059     int i = 4;
0060
0061     if (DIV_ROUND_UP(rbsp->pos, 8) + i > rbsp->size) {
0062         rbsp->error = -EINVAL;
0063         return;
0064     }
0065
0066     if (p[0] != 0x00 || p[1] != 0x00 || p[2] != 0x00 || p[3] != 0x01) {
0067         rbsp->error = -EINVAL;
0068         return;
0069     }
0070
0071     rbsp->pos += i * 8;
0072 }
0073
0074 static void nal_hevc_write_filler_data(struct rbsp *rbsp)
0075 {
0076     u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8);
0077     int i;
0078
0079     /* Keep 1 byte extra for terminating the NAL unit */
0080     i = rbsp->size - DIV_ROUND_UP(rbsp->pos, 8) - 1;
0081     memset(p, 0xff, i);
0082     rbsp->pos += i * 8;
0083 }
0084
0085 static void nal_hevc_read_filler_data(struct rbsp *rbsp)
0086 {
0087     u8 *p = rbsp->data + DIV_ROUND_UP(rbsp->pos, 8);
0088
0089     while (*p == 0xff) {
0090         if (DIV_ROUND_UP(rbsp->pos, 8) > rbsp->size) {
0091             rbsp->error = -EINVAL;
0092             return;
0093         }
0094
0095         p++;
0096         rbsp->pos += 8;
0097     }
0098 }
0099
0100 static void nal_hevc_rbsp_profile_tier_level(struct rbsp *rbsp,
0101                          struct nal_hevc_profile_tier_level *ptl)
0102 {
0103     unsigned int i;
0104     unsigned int max_num_sub_layers_minus_1 = 0;
0105
0106     rbsp_bits(rbsp, 2, &ptl->general_profile_space);
0107     rbsp_bit(rbsp, &ptl->general_tier_flag);
0108     rbsp_bits(rbsp, 5, &ptl->general_profile_idc);
0109     for (i = 0; i < 32; i++)
0110         rbsp_bit(rbsp, &ptl->general_profile_compatibility_flag[i]);
0111     rbsp_bit(rbsp, &ptl->general_progressive_source_flag);
0112     rbsp_bit(rbsp, &ptl->general_interlaced_source_flag);
0113     rbsp_bit(rbsp, &ptl->general_non_packed_constraint_flag);
0114     rbsp_bit(rbsp, &ptl->general_frame_only_constraint_flag);
0115     if (ptl->general_profile_idc == 4 ||
0116         ptl->general_profile_compatibility_flag[4] ||
0117         ptl->general_profile_idc == 5 ||
0118         ptl->general_profile_compatibility_flag[5] ||
0119         ptl->general_profile_idc == 6 ||
0120         ptl->general_profile_compatibility_flag[6] ||
0121         ptl->general_profile_idc == 7 ||
0122         ptl->general_profile_compatibility_flag[7] ||
0123         ptl->general_profile_idc == 8 ||
0124         ptl->general_profile_compatibility_flag[8] ||
0125         ptl->general_profile_idc == 9 ||
0126         ptl->general_profile_compatibility_flag[9] ||
0127         ptl->general_profile_idc == 10 ||
0128         ptl->general_profile_compatibility_flag[10]) {
0129         rbsp_bit(rbsp, &ptl->general_max_12bit_constraint_flag);
0130         rbsp_bit(rbsp, &ptl->general_max_10bit_constraint_flag);
0131         rbsp_bit(rbsp, &ptl->general_max_8bit_constraint_flag);
0132         rbsp_bit(rbsp, &ptl->general_max_422chroma_constraint_flag);
0133         rbsp_bit(rbsp, &ptl->general_max_420chroma_constraint_flag);
0134         rbsp_bit(rbsp, &ptl->general_max_monochrome_constraint_flag);
0135         rbsp_bit(rbsp, &ptl->general_intra_constraint_flag);
0136         rbsp_bit(rbsp, &ptl->general_one_picture_only_constraint_flag);
0137         rbsp_bit(rbsp, &ptl->general_lower_bit_rate_constraint_flag);
0138         if (ptl->general_profile_idc == 5 ||
0139             ptl->general_profile_compatibility_flag[5] ||
0140             ptl->general_profile_idc == 9 ||
0141             ptl->general_profile_compatibility_flag[9] ||
0142             ptl->general_profile_idc == 10 ||
0143             ptl->general_profile_compatibility_flag[10]) {
0144             rbsp_bit(rbsp, &ptl->general_max_14bit_constraint_flag);
0145             rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_33bits);
0146             rbsp_bits(rbsp, 33 - 32, &ptl->general_reserved_zero_33bits);
0147         } else {
0148             rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_34bits);
0149             rbsp_bits(rbsp, 34 - 2, &ptl->general_reserved_zero_34bits);
0150         }
0151     } else if (ptl->general_profile_idc == 2 ||
0152            ptl->general_profile_compatibility_flag[2]) {
0153         rbsp_bits(rbsp, 7, &ptl->general_reserved_zero_7bits);
0154         rbsp_bit(rbsp, &ptl->general_one_picture_only_constraint_flag);
0155         rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_35bits);
0156         rbsp_bits(rbsp, 35 - 32, &ptl->general_reserved_zero_35bits);
0157     } else {
0158         rbsp_bits(rbsp, 32, &ptl->general_reserved_zero_43bits);
0159         rbsp_bits(rbsp, 43 - 32, &ptl->general_reserved_zero_43bits);
0160     }
0161     if ((ptl->general_profile_idc >= 1 && ptl->general_profile_idc <= 5) ||
0162         ptl->general_profile_idc == 9 ||
0163         ptl->general_profile_compatibility_flag[1] ||
0164         ptl->general_profile_compatibility_flag[2] ||
0165         ptl->general_profile_compatibility_flag[3] ||
0166         ptl->general_profile_compatibility_flag[4] ||
0167         ptl->general_profile_compatibility_flag[5] ||
0168         ptl->general_profile_compatibility_flag[9])
0169         rbsp_bit(rbsp, &ptl->general_inbld_flag);
0170     else
0171         rbsp_bit(rbsp, &ptl->general_reserved_zero_bit);
0172     rbsp_bits(rbsp, 8, &ptl->general_level_idc);
0173     if (max_num_sub_layers_minus_1 > 0)
0174         rbsp_unsupported(rbsp);
0175 }
0176
0177 static void nal_hevc_rbsp_vps(struct rbsp *rbsp, struct nal_hevc_vps *vps)
0178 {
0179     unsigned int i, j;
0180     unsigned int reserved_0xffff_16bits = 0xffff;
0181
0182     rbsp_bits(rbsp, 4, &vps->video_parameter_set_id);
0183     rbsp_bit(rbsp, &vps->base_layer_internal_flag);
0184     rbsp_bit(rbsp, &vps->base_layer_available_flag);
0185     rbsp_bits(rbsp, 6, &vps->max_layers_minus1);
0186     rbsp_bits(rbsp, 3, &vps->max_sub_layers_minus1);
0187     rbsp_bits(rbsp, 1, &vps->temporal_id_nesting_flag);
0188     rbsp_bits(rbsp, 16, &reserved_0xffff_16bits);
0189     nal_hevc_rbsp_profile_tier_level(rbsp, &vps->profile_tier_level);
0190     rbsp_bit(rbsp, &vps->sub_layer_ordering_info_present_flag);
0191     for (i = vps->sub_layer_ordering_info_present_flag ? 0 : vps->max_sub_layers_minus1;
0192          i <= vps->max_sub_layers_minus1; i++) {
0193         rbsp_uev(rbsp, &vps->max_dec_pic_buffering_minus1[i]);
0194         rbsp_uev(rbsp, &vps->max_num_reorder_pics[i]);
0195         rbsp_uev(rbsp, &vps->max_latency_increase_plus1[i]);
0196     }
0197     rbsp_bits(rbsp, 6, &vps->max_layer_id);
0198     rbsp_uev(rbsp, &vps->num_layer_sets_minus1);
0199     for (i = 0; i <= vps->num_layer_sets_minus1; i++)
0200         for (j = 0; j <= vps->max_layer_id; j++)
0201             rbsp_bit(rbsp, &vps->layer_id_included_flag[i][j]);
0202     rbsp_bit(rbsp, &vps->timing_info_present_flag);
0203     if (vps->timing_info_present_flag)
0204         rbsp_unsupported(rbsp);
0205     rbsp_bit(rbsp, &vps->extension_flag);
0206     if (vps->extension_flag)
0207         rbsp_unsupported(rbsp);
0208 }
0209
0210 static void nal_hevc_rbsp_sub_layer_hrd_parameters(struct rbsp *rbsp,
0211                            struct nal_hevc_sub_layer_hrd_parameters *hrd)
0212 {
0213     unsigned int i;
0214     unsigned int cpb_cnt = 1;
0215
0216     for (i = 0; i < cpb_cnt; i++) {
0217         rbsp_uev(rbsp, &hrd->bit_rate_value_minus1[i]);
0218         rbsp_uev(rbsp, &hrd->cpb_size_value_minus1[i]);
0219         rbsp_bit(rbsp, &hrd->cbr_flag[i]);
0220     }
0221 }
0222
0223 static void nal_hevc_rbsp_hrd_parameters(struct rbsp *rbsp,
0224                      struct nal_hevc_hrd_parameters *hrd)
0225 {
0226     unsigned int i;
0227     unsigned int max_num_sub_layers_minus_1 = 0;
0228
0229     rbsp_bit(rbsp, &hrd->nal_hrd_parameters_present_flag);
0230     rbsp_bit(rbsp, &hrd->vcl_hrd_parameters_present_flag);
0231     if (hrd->nal_hrd_parameters_present_flag || hrd->vcl_hrd_parameters_present_flag) {
0232         rbsp_bit(rbsp, &hrd->sub_pic_hrd_params_present_flag);
0233         if (hrd->sub_pic_hrd_params_present_flag) {
0234             rbsp_bits(rbsp, 8, &hrd->tick_divisor_minus2);
0235             rbsp_bits(rbsp, 5, &hrd->du_cpb_removal_delay_increment_length_minus1);
0236             rbsp_bit(rbsp, &hrd->sub_pic_cpb_params_in_pic_timing_sei_flag);
0237             rbsp_bits(rbsp, 5, &hrd->dpb_output_delay_du_length_minus1);
0238         }
0239         rbsp_bits(rbsp, 4, &hrd->bit_rate_scale);
0240         rbsp_bits(rbsp, 4, &hrd->cpb_size_scale);
0241         if (hrd->sub_pic_hrd_params_present_flag)
0242             rbsp_bits(rbsp, 4, &hrd->cpb_size_du_scale);
0243         rbsp_bits(rbsp, 5, &hrd->initial_cpb_removal_delay_length_minus1);
0244         rbsp_bits(rbsp, 5, &hrd->au_cpb_removal_delay_length_minus1);
0245         rbsp_bits(rbsp, 5, &hrd->dpb_output_delay_length_minus1);
0246     }
0247     for (i = 0; i <= max_num_sub_layers_minus_1; i++) {
0248         rbsp_bit(rbsp, &hrd->fixed_pic_rate_general_flag[i]);
0249         if (!hrd->fixed_pic_rate_general_flag[i])
0250             rbsp_bit(rbsp, &hrd->fixed_pic_rate_within_cvs_flag[i]);
0251         if (hrd->fixed_pic_rate_within_cvs_flag[i])
0252             rbsp_uev(rbsp, &hrd->elemental_duration_in_tc_minus1[i]);
0253         else
0254             rbsp_bit(rbsp, &hrd->low_delay_hrd_flag[i]);
0255         if (!hrd->low_delay_hrd_flag[i])
0256             rbsp_uev(rbsp, &hrd->cpb_cnt_minus1[i]);
0257         if (hrd->nal_hrd_parameters_present_flag)
0258             nal_hevc_rbsp_sub_layer_hrd_parameters(rbsp, &hrd->vcl_hrd[i]);
0259         if (hrd->vcl_hrd_parameters_present_flag)
0260             nal_hevc_rbsp_sub_layer_hrd_parameters(rbsp, &hrd->vcl_hrd[i]);
0261     }
0262 }
0263
0264 static void nal_hevc_rbsp_vui_parameters(struct rbsp *rbsp,
0265                      struct nal_hevc_vui_parameters *vui)
0266 {
0267     if (!vui) {
0268         rbsp->error = -EINVAL;
0269         return;
0270     }
0271
0272     rbsp_bit(rbsp, &vui->aspect_ratio_info_present_flag);
0273     if (vui->aspect_ratio_info_present_flag) {
0274         rbsp_bits(rbsp, 8, &vui->aspect_ratio_idc);
0275         if (vui->aspect_ratio_idc == 255) {
0276             rbsp_bits(rbsp, 16, &vui->sar_width);
0277             rbsp_bits(rbsp, 16, &vui->sar_height);
0278         }
0279     }
0280
0281     rbsp_bit(rbsp, &vui->overscan_info_present_flag);
0282     if (vui->overscan_info_present_flag)
0283         rbsp_bit(rbsp, &vui->overscan_appropriate_flag);
0284
0285     rbsp_bit(rbsp, &vui->video_signal_type_present_flag);
0286     if (vui->video_signal_type_present_flag) {
0287         rbsp_bits(rbsp, 3, &vui->video_format);
0288         rbsp_bit(rbsp, &vui->video_full_range_flag);
0289
0290         rbsp_bit(rbsp, &vui->colour_description_present_flag);
0291         if (vui->colour_description_present_flag) {
0292             rbsp_bits(rbsp, 8, &vui->colour_primaries);
0293             rbsp_bits(rbsp, 8, &vui->transfer_characteristics);
0294             rbsp_bits(rbsp, 8, &vui->matrix_coeffs);
0295         }
0296     }
0297
0298     rbsp_bit(rbsp, &vui->chroma_loc_info_present_flag);
0299     if (vui->chroma_loc_info_present_flag) {
0300         rbsp_uev(rbsp, &vui->chroma_sample_loc_type_top_field);
0301         rbsp_uev(rbsp, &vui->chroma_sample_loc_type_bottom_field);
0302     }
0303
0304     rbsp_bit(rbsp, &vui->neutral_chroma_indication_flag);
0305     rbsp_bit(rbsp, &vui->field_seq_flag);
0306     rbsp_bit(rbsp, &vui->frame_field_info_present_flag);
0307     rbsp_bit(rbsp, &vui->default_display_window_flag);
0308     if (vui->default_display_window_flag) {
0309         rbsp_uev(rbsp, &vui->def_disp_win_left_offset);
0310         rbsp_uev(rbsp, &vui->def_disp_win_right_offset);
0311         rbsp_uev(rbsp, &vui->def_disp_win_top_offset);
0312         rbsp_uev(rbsp, &vui->def_disp_win_bottom_offset);
0313     }
0314
0315     rbsp_bit(rbsp, &vui->vui_timing_info_present_flag);
0316     if (vui->vui_timing_info_present_flag) {
0317         rbsp_bits(rbsp, 32, &vui->vui_num_units_in_tick);
0318         rbsp_bits(rbsp, 32, &vui->vui_time_scale);
0319         rbsp_bit(rbsp, &vui->vui_poc_proportional_to_timing_flag);
0320         if (vui->vui_poc_proportional_to_timing_flag)
0321             rbsp_uev(rbsp, &vui->vui_num_ticks_poc_diff_one_minus1);
0322         rbsp_bit(rbsp, &vui->vui_hrd_parameters_present_flag);
0323         if (vui->vui_hrd_parameters_present_flag)
0324             nal_hevc_rbsp_hrd_parameters(rbsp, &vui->nal_hrd_parameters);
0325     }
0326
0327     rbsp_bit(rbsp, &vui->bitstream_restriction_flag);
0328     if (vui->bitstream_restriction_flag) {
0329         rbsp_bit(rbsp, &vui->tiles_fixed_structure_flag);
0330         rbsp_bit(rbsp, &vui->motion_vectors_over_pic_boundaries_flag);
0331         rbsp_bit(rbsp, &vui->restricted_ref_pic_lists_flag);
0332         rbsp_uev(rbsp, &vui->min_spatial_segmentation_idc);
0333         rbsp_uev(rbsp, &vui->max_bytes_per_pic_denom);
0334         rbsp_uev(rbsp, &vui->max_bits_per_min_cu_denom);
0335         rbsp_uev(rbsp, &vui->log2_max_mv_length_horizontal);
0336         rbsp_uev(rbsp, &vui->log2_max_mv_length_vertical);
0337     }
0338 }
0339
0340 static void nal_hevc_rbsp_sps(struct rbsp *rbsp, struct nal_hevc_sps *sps)
0341 {
0342     unsigned int i;
0343
0344     rbsp_bits(rbsp, 4, &sps->video_parameter_set_id);
0345     rbsp_bits(rbsp, 3, &sps->max_sub_layers_minus1);
0346     rbsp_bit(rbsp, &sps->temporal_id_nesting_flag);
0347     nal_hevc_rbsp_profile_tier_level(rbsp, &sps->profile_tier_level);
0348     rbsp_uev(rbsp, &sps->seq_parameter_set_id);
0349
0350     rbsp_uev(rbsp, &sps->chroma_format_idc);
0351     if (sps->chroma_format_idc == 3)
0352         rbsp_bit(rbsp, &sps->separate_colour_plane_flag);
0353     rbsp_uev(rbsp, &sps->pic_width_in_luma_samples);
0354     rbsp_uev(rbsp, &sps->pic_height_in_luma_samples);
0355     rbsp_bit(rbsp, &sps->conformance_window_flag);
0356     if (sps->conformance_window_flag) {
0357         rbsp_uev(rbsp, &sps->conf_win_left_offset);
0358         rbsp_uev(rbsp, &sps->conf_win_right_offset);
0359         rbsp_uev(rbsp, &sps->conf_win_top_offset);
0360         rbsp_uev(rbsp, &sps->conf_win_bottom_offset);
0361     }
0362     rbsp_uev(rbsp, &sps->bit_depth_luma_minus8);
0363     rbsp_uev(rbsp, &sps->bit_depth_chroma_minus8);
0364
0365     rbsp_uev(rbsp, &sps->log2_max_pic_order_cnt_lsb_minus4);
0366
0367     rbsp_bit(rbsp, &sps->sub_layer_ordering_info_present_flag);
0368     for (i = (sps->sub_layer_ordering_info_present_flag ? 0 : sps->max_sub_layers_minus1);
0369          i <= sps->max_sub_layers_minus1; i++) {
0370         rbsp_uev(rbsp, &sps->max_dec_pic_buffering_minus1[i]);
0371         rbsp_uev(rbsp, &sps->max_num_reorder_pics[i]);
0372         rbsp_uev(rbsp, &sps->max_latency_increase_plus1[i]);
0373     }
0374     rbsp_uev(rbsp, &sps->log2_min_luma_coding_block_size_minus3);
0375     rbsp_uev(rbsp, &sps->log2_diff_max_min_luma_coding_block_size);
0376     rbsp_uev(rbsp, &sps->log2_min_luma_transform_block_size_minus2);
0377     rbsp_uev(rbsp, &sps->log2_diff_max_min_luma_transform_block_size);
0378     rbsp_uev(rbsp, &sps->max_transform_hierarchy_depth_inter);
0379     rbsp_uev(rbsp, &sps->max_transform_hierarchy_depth_intra);
0380
0381     rbsp_bit(rbsp, &sps->scaling_list_enabled_flag);
0382     if (sps->scaling_list_enabled_flag)
0383         rbsp_unsupported(rbsp);
0384
0385     rbsp_bit(rbsp, &sps->amp_enabled_flag);
0386     rbsp_bit(rbsp, &sps->sample_adaptive_offset_enabled_flag);
0387     rbsp_bit(rbsp, &sps->pcm_enabled_flag);
0388     if (sps->pcm_enabled_flag) {
0389         rbsp_bits(rbsp, 4, &sps->pcm_sample_bit_depth_luma_minus1);
0390         rbsp_bits(rbsp, 4, &sps->pcm_sample_bit_depth_chroma_minus1);
0391         rbsp_uev(rbsp, &sps->log2_min_pcm_luma_coding_block_size_minus3);
0392         rbsp_uev(rbsp, &sps->log2_diff_max_min_pcm_luma_coding_block_size);
0393         rbsp_bit(rbsp, &sps->pcm_loop_filter_disabled_flag);
0394     }
0395
0396     rbsp_uev(rbsp, &sps->num_short_term_ref_pic_sets);
0397     if (sps->num_short_term_ref_pic_sets > 0)
0398         rbsp_unsupported(rbsp);
0399
0400     rbsp_bit(rbsp, &sps->long_term_ref_pics_present_flag);
0401     if (sps->long_term_ref_pics_present_flag)
0402         rbsp_unsupported(rbsp);
0403
0404     rbsp_bit(rbsp, &sps->sps_temporal_mvp_enabled_flag);
0405     rbsp_bit(rbsp, &sps->strong_intra_smoothing_enabled_flag);
0406     rbsp_bit(rbsp, &sps->vui_parameters_present_flag);
0407     if (sps->vui_parameters_present_flag)
0408         nal_hevc_rbsp_vui_parameters(rbsp, &sps->vui);
0409
0410     rbsp_bit(rbsp, &sps->extension_present_flag);
0411     if (sps->extension_present_flag) {
0412         rbsp_bit(rbsp, &sps->sps_range_extension_flag);
0413         rbsp_bit(rbsp, &sps->sps_multilayer_extension_flag);
0414         rbsp_bit(rbsp, &sps->sps_3d_extension_flag);
0415         rbsp_bit(rbsp, &sps->sps_scc_extension_flag);
0416         rbsp_bits(rbsp, 5, &sps->sps_extension_4bits);
0417     }
0418     if (sps->sps_range_extension_flag)
0419         rbsp_unsupported(rbsp);
0420     if (sps->sps_multilayer_extension_flag)
0421         rbsp_unsupported(rbsp);
0422     if (sps->sps_3d_extension_flag)
0423         rbsp_unsupported(rbsp);
0424     if (sps->sps_scc_extension_flag)
0425         rbsp_unsupported(rbsp);
0426     if (sps->sps_extension_4bits)
0427         rbsp_unsupported(rbsp);
0428 }
0429
0430 static void nal_hevc_rbsp_pps(struct rbsp *rbsp, struct nal_hevc_pps *pps)
0431 {
0432     unsigned int i;
0433
0434     rbsp_uev(rbsp, &pps->pps_pic_parameter_set_id);
0435     rbsp_uev(rbsp, &pps->pps_seq_parameter_set_id);
0436     rbsp_bit(rbsp, &pps->dependent_slice_segments_enabled_flag);
0437     rbsp_bit(rbsp, &pps->output_flag_present_flag);
0438     rbsp_bits(rbsp, 3, &pps->num_extra_slice_header_bits);
0439     rbsp_bit(rbsp, &pps->sign_data_hiding_enabled_flag);
0440     rbsp_bit(rbsp, &pps->cabac_init_present_flag);
0441     rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1);
0442     rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1);
0443     rbsp_sev(rbsp, &pps->init_qp_minus26);
0444     rbsp_bit(rbsp, &pps->constrained_intra_pred_flag);
0445     rbsp_bit(rbsp, &pps->transform_skip_enabled_flag);
0446     rbsp_bit(rbsp, &pps->cu_qp_delta_enabled_flag);
0447     if (pps->cu_qp_delta_enabled_flag)
0448         rbsp_uev(rbsp, &pps->diff_cu_qp_delta_depth);
0449     rbsp_sev(rbsp, &pps->pps_cb_qp_offset);
0450     rbsp_sev(rbsp, &pps->pps_cr_qp_offset);
0451     rbsp_bit(rbsp, &pps->pps_slice_chroma_qp_offsets_present_flag);
0452     rbsp_bit(rbsp, &pps->weighted_pred_flag);
0453     rbsp_bit(rbsp, &pps->weighted_bipred_flag);
0454     rbsp_bit(rbsp, &pps->transquant_bypass_enabled_flag);
0455     rbsp_bit(rbsp, &pps->tiles_enabled_flag);
0456     rbsp_bit(rbsp, &pps->entropy_coding_sync_enabled_flag);
0457     if (pps->tiles_enabled_flag) {
0458         rbsp_uev(rbsp, &pps->num_tile_columns_minus1);
0459         rbsp_uev(rbsp, &pps->num_tile_rows_minus1);
0460         rbsp_bit(rbsp, &pps->uniform_spacing_flag);
0461         if (!pps->uniform_spacing_flag) {
0462             for (i = 0; i < pps->num_tile_columns_minus1; i++)
0463                 rbsp_uev(rbsp, &pps->column_width_minus1[i]);
0464             for (i = 0; i < pps->num_tile_rows_minus1; i++)
0465                 rbsp_uev(rbsp, &pps->row_height_minus1[i]);
0466         }
0467         rbsp_bit(rbsp, &pps->loop_filter_across_tiles_enabled_flag);
0468     }
0469     rbsp_bit(rbsp, &pps->pps_loop_filter_across_slices_enabled_flag);
0470     rbsp_bit(rbsp, &pps->deblocking_filter_control_present_flag);
0471     if (pps->deblocking_filter_control_present_flag) {
0472         rbsp_bit(rbsp, &pps->deblocking_filter_override_enabled_flag);
0473         rbsp_bit(rbsp, &pps->pps_deblocking_filter_disabled_flag);
0474         if (!pps->pps_deblocking_filter_disabled_flag) {
0475             rbsp_sev(rbsp, &pps->pps_beta_offset_div2);
0476             rbsp_sev(rbsp, &pps->pps_tc_offset_div2);
0477         }
0478     }
0479     rbsp_bit(rbsp, &pps->pps_scaling_list_data_present_flag);
0480     if (pps->pps_scaling_list_data_present_flag)
0481         rbsp_unsupported(rbsp);
0482     rbsp_bit(rbsp, &pps->lists_modification_present_flag);
0483     rbsp_uev(rbsp, &pps->log2_parallel_merge_level_minus2);
0484     rbsp_bit(rbsp, &pps->slice_segment_header_extension_present_flag);
0485     rbsp_bit(rbsp, &pps->pps_extension_present_flag);
0486     if (pps->pps_extension_present_flag) {
0487         rbsp_bit(rbsp, &pps->pps_range_extension_flag);
0488         rbsp_bit(rbsp, &pps->pps_multilayer_extension_flag);
0489         rbsp_bit(rbsp, &pps->pps_3d_extension_flag);
0490         rbsp_bit(rbsp, &pps->pps_scc_extension_flag);
0491         rbsp_bits(rbsp, 4, &pps->pps_extension_4bits);
0492     }
0493     if (pps->pps_range_extension_flag)
0494         rbsp_unsupported(rbsp);
0495     if (pps->pps_multilayer_extension_flag)
0496         rbsp_unsupported(rbsp);
0497     if (pps->pps_3d_extension_flag)
0498         rbsp_unsupported(rbsp);
0499     if (pps->pps_scc_extension_flag)
0500         rbsp_unsupported(rbsp);
0501     if (pps->pps_extension_4bits)
0502         rbsp_unsupported(rbsp);
0503 }
0504
0505 /**
0506  * nal_hevc_write_vps() - Write PPS NAL unit into RBSP format
0507  * @dev: device pointer
0508  * @dest: the buffer that is filled with RBSP data
0509  * @n: maximum size of @dest in bytes
0510  * @vps: &struct nal_hevc_vps to convert to RBSP
0511  *
0512  * Convert @vps to RBSP data and write it into @dest.
0513  *
0514  * The size of the VPS NAL unit is not known in advance and this function will
0515  * fail, if @dest does not hold sufficient space for the VPS NAL unit.
0516  *
0517  * Return: number of bytes written to @dest or negative error code
0518  */
0519 ssize_t nal_hevc_write_vps(const struct device *dev,
0520                void *dest, size_t n, struct nal_hevc_vps *vps)
0521 {
0522     struct rbsp rbsp;
0523     unsigned int forbidden_zero_bit = 0;
0524     unsigned int nal_unit_type = VPS_NUT;
0525     unsigned int nuh_layer_id = 0;
0526     unsigned int nuh_temporal_id_plus1 = 1;
0527
0528     if (!dest)
0529         return -EINVAL;
0530
0531     rbsp_init(&rbsp, dest, n, &write);
0532
0533     nal_hevc_write_start_code_prefix(&rbsp);
0534
0535     /* NAL unit header */
0536     rbsp_bit(&rbsp, &forbidden_zero_bit);
0537     rbsp_bits(&rbsp, 6, &nal_unit_type);
0538     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0539     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0540
0541     nal_hevc_rbsp_vps(&rbsp, vps);
0542
0543     rbsp_trailing_bits(&rbsp);
0544
0545     if (rbsp.error)
0546         return rbsp.error;
0547
0548     return DIV_ROUND_UP(rbsp.pos, 8);
0549 }
0550 EXPORT_SYMBOL_GPL(nal_hevc_write_vps);
0551
0552 /**
0553  * nal_hevc_read_vps() - Read VPS NAL unit from RBSP format
0554  * @dev: device pointer
0555  * @vps: the &struct nal_hevc_vps to fill from the RBSP data
0556  * @src: the buffer that contains the RBSP data
0557  * @n: size of @src in bytes
0558  *
0559  * Read RBSP data from @src and use it to fill @vps.
0560  *
0561  * Return: number of bytes read from @src or negative error code
0562  */
0563 ssize_t nal_hevc_read_vps(const struct device *dev,
0564               struct nal_hevc_vps *vps, void *src, size_t n)
0565 {
0566     struct rbsp rbsp;
0567     unsigned int forbidden_zero_bit;
0568     unsigned int nal_unit_type;
0569     unsigned int nuh_layer_id;
0570     unsigned int nuh_temporal_id_plus1;
0571
0572     if (!src)
0573         return -EINVAL;
0574
0575     rbsp_init(&rbsp, src, n, &read);
0576
0577     nal_hevc_read_start_code_prefix(&rbsp);
0578
0579     rbsp_bit(&rbsp, &forbidden_zero_bit);
0580     rbsp_bits(&rbsp, 6, &nal_unit_type);
0581     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0582     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0583
0584     if (rbsp.error ||
0585         forbidden_zero_bit != 0 ||
0586         nal_unit_type != VPS_NUT)
0587         return -EINVAL;
0588
0589     nal_hevc_rbsp_vps(&rbsp, vps);
0590
0591     rbsp_trailing_bits(&rbsp);
0592
0593     if (rbsp.error)
0594         return rbsp.error;
0595
0596     return DIV_ROUND_UP(rbsp.pos, 8);
0597 }
0598 EXPORT_SYMBOL_GPL(nal_hevc_read_vps);
0599
0600 /**
0601  * nal_hevc_write_sps() - Write SPS NAL unit into RBSP format
0602  * @dev: device pointer
0603  * @dest: the buffer that is filled with RBSP data
0604  * @n: maximum size of @dest in bytes
0605  * @sps: &struct nal_hevc_sps to convert to RBSP
0606  *
0607  * Convert @sps to RBSP data and write it into @dest.
0608  *
0609  * The size of the SPS NAL unit is not known in advance and this function will
0610  * fail, if @dest does not hold sufficient space for the SPS NAL unit.
0611  *
0612  * Return: number of bytes written to @dest or negative error code
0613  */
0614 ssize_t nal_hevc_write_sps(const struct device *dev,
0615                void *dest, size_t n, struct nal_hevc_sps *sps)
0616 {
0617     struct rbsp rbsp;
0618     unsigned int forbidden_zero_bit = 0;
0619     unsigned int nal_unit_type = SPS_NUT;
0620     unsigned int nuh_layer_id = 0;
0621     unsigned int nuh_temporal_id_plus1 = 1;
0622
0623     if (!dest)
0624         return -EINVAL;
0625
0626     rbsp_init(&rbsp, dest, n, &write);
0627
0628     nal_hevc_write_start_code_prefix(&rbsp);
0629
0630     /* NAL unit header */
0631     rbsp_bit(&rbsp, &forbidden_zero_bit);
0632     rbsp_bits(&rbsp, 6, &nal_unit_type);
0633     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0634     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0635
0636     nal_hevc_rbsp_sps(&rbsp, sps);
0637
0638     rbsp_trailing_bits(&rbsp);
0639
0640     if (rbsp.error)
0641         return rbsp.error;
0642
0643     return DIV_ROUND_UP(rbsp.pos, 8);
0644 }
0645 EXPORT_SYMBOL_GPL(nal_hevc_write_sps);
0646
0647 /**
0648  * nal_hevc_read_sps() - Read SPS NAL unit from RBSP format
0649  * @dev: device pointer
0650  * @sps: the &struct nal_hevc_sps to fill from the RBSP data
0651  * @src: the buffer that contains the RBSP data
0652  * @n: size of @src in bytes
0653  *
0654  * Read RBSP data from @src and use it to fill @sps.
0655  *
0656  * Return: number of bytes read from @src or negative error code
0657  */
0658 ssize_t nal_hevc_read_sps(const struct device *dev,
0659               struct nal_hevc_sps *sps, void *src, size_t n)
0660 {
0661     struct rbsp rbsp;
0662     unsigned int forbidden_zero_bit;
0663     unsigned int nal_unit_type;
0664     unsigned int nuh_layer_id;
0665     unsigned int nuh_temporal_id_plus1;
0666
0667     if (!src)
0668         return -EINVAL;
0669
0670     rbsp_init(&rbsp, src, n, &read);
0671
0672     nal_hevc_read_start_code_prefix(&rbsp);
0673
0674     rbsp_bit(&rbsp, &forbidden_zero_bit);
0675     rbsp_bits(&rbsp, 6, &nal_unit_type);
0676     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0677     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0678
0679     if (rbsp.error ||
0680         forbidden_zero_bit != 0 ||
0681         nal_unit_type != SPS_NUT)
0682         return -EINVAL;
0683
0684     nal_hevc_rbsp_sps(&rbsp, sps);
0685
0686     rbsp_trailing_bits(&rbsp);
0687
0688     if (rbsp.error)
0689         return rbsp.error;
0690
0691     return DIV_ROUND_UP(rbsp.pos, 8);
0692 }
0693 EXPORT_SYMBOL_GPL(nal_hevc_read_sps);
0694
0695 /**
0696  * nal_hevc_write_pps() - Write PPS NAL unit into RBSP format
0697  * @dev: device pointer
0698  * @dest: the buffer that is filled with RBSP data
0699  * @n: maximum size of @dest in bytes
0700  * @pps: &struct nal_hevc_pps to convert to RBSP
0701  *
0702  * Convert @pps to RBSP data and write it into @dest.
0703  *
0704  * The size of the PPS NAL unit is not known in advance and this function will
0705  * fail, if @dest does not hold sufficient space for the PPS NAL unit.
0706  *
0707  * Return: number of bytes written to @dest or negative error code
0708  */
0709 ssize_t nal_hevc_write_pps(const struct device *dev,
0710                void *dest, size_t n, struct nal_hevc_pps *pps)
0711 {
0712     struct rbsp rbsp;
0713     unsigned int forbidden_zero_bit = 0;
0714     unsigned int nal_unit_type = PPS_NUT;
0715     unsigned int nuh_layer_id = 0;
0716     unsigned int nuh_temporal_id_plus1 = 1;
0717
0718     if (!dest)
0719         return -EINVAL;
0720
0721     rbsp_init(&rbsp, dest, n, &write);
0722
0723     nal_hevc_write_start_code_prefix(&rbsp);
0724
0725     /* NAL unit header */
0726     rbsp_bit(&rbsp, &forbidden_zero_bit);
0727     rbsp_bits(&rbsp, 6, &nal_unit_type);
0728     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0729     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0730
0731     nal_hevc_rbsp_pps(&rbsp, pps);
0732
0733     rbsp_trailing_bits(&rbsp);
0734
0735     if (rbsp.error)
0736         return rbsp.error;
0737
0738     return DIV_ROUND_UP(rbsp.pos, 8);
0739 }
0740 EXPORT_SYMBOL_GPL(nal_hevc_write_pps);
0741
0742 /**
0743  * nal_hevc_read_pps() - Read PPS NAL unit from RBSP format
0744  * @dev: device pointer
0745  * @pps: the &struct nal_hevc_pps to fill from the RBSP data
0746  * @src: the buffer that contains the RBSP data
0747  * @n: size of @src in bytes
0748  *
0749  * Read RBSP data from @src and use it to fill @pps.
0750  *
0751  * Return: number of bytes read from @src or negative error code
0752  */
0753 ssize_t nal_hevc_read_pps(const struct device *dev,
0754               struct nal_hevc_pps *pps, void *src, size_t n)
0755 {
0756     struct rbsp rbsp;
0757     unsigned int forbidden_zero_bit;
0758     unsigned int nal_unit_type;
0759     unsigned int nuh_layer_id;
0760     unsigned int nuh_temporal_id_plus1;
0761
0762     if (!src)
0763         return -EINVAL;
0764
0765     rbsp_init(&rbsp, src, n, &read);
0766
0767     nal_hevc_read_start_code_prefix(&rbsp);
0768
0769     /* NAL unit header */
0770     rbsp_bit(&rbsp, &forbidden_zero_bit);
0771     rbsp_bits(&rbsp, 6, &nal_unit_type);
0772     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0773     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0774
0775     nal_hevc_rbsp_pps(&rbsp, pps);
0776
0777     rbsp_trailing_bits(&rbsp);
0778
0779     if (rbsp.error)
0780         return rbsp.error;
0781
0782     return DIV_ROUND_UP(rbsp.pos, 8);
0783 }
0784 EXPORT_SYMBOL_GPL(nal_hevc_read_pps);
0785
0786 /**
0787  * nal_hevc_write_filler() - Write filler data RBSP
0788  * @dev: device pointer
0789  * @dest: buffer to fill with filler data
0790  * @n: size of the buffer to fill with filler data
0791  *
0792  * Write a filler data RBSP to @dest with a size of @n bytes and return the
0793  * number of written filler data bytes.
0794  *
0795  * Use this function to generate dummy data in an RBSP data stream that can be
0796  * safely ignored by hevc decoders.
0797  *
0798  * The RBSP format of the filler data is specified in Rec. ITU-T H.265
0799  * (02/2018) 7.3.2.8 Filler data RBSP syntax.
0800  *
0801  * Return: number of filler data bytes (including marker) or negative error
0802  */
0803 ssize_t nal_hevc_write_filler(const struct device *dev, void *dest, size_t n)
0804 {
0805     struct rbsp rbsp;
0806     unsigned int forbidden_zero_bit = 0;
0807     unsigned int nal_unit_type = FD_NUT;
0808     unsigned int nuh_layer_id = 0;
0809     unsigned int nuh_temporal_id_plus1 = 1;
0810
0811     if (!dest)
0812         return -EINVAL;
0813
0814     rbsp_init(&rbsp, dest, n, &write);
0815
0816     nal_hevc_write_start_code_prefix(&rbsp);
0817
0818     rbsp_bit(&rbsp, &forbidden_zero_bit);
0819     rbsp_bits(&rbsp, 6, &nal_unit_type);
0820     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0821     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0822
0823     nal_hevc_write_filler_data(&rbsp);
0824     rbsp_trailing_bits(&rbsp);
0825
0826     if (rbsp.error)
0827         return rbsp.error;
0828
0829     return DIV_ROUND_UP(rbsp.pos, 8);
0830 }
0831 EXPORT_SYMBOL_GPL(nal_hevc_write_filler);
0832
0833 /**
0834  * nal_hevc_read_filler() - Read filler data RBSP
0835  * @dev: device pointer
0836  * @src: buffer with RBSP data that is read
0837  * @n: maximum size of src that shall be read
0838  *
0839  * Read a filler data RBSP from @src up to a maximum size of @n bytes and
0840  * return the size of the filler data in bytes including the marker.
0841  *
0842  * This function is used to parse filler data and skip the respective bytes in
0843  * the RBSP data.
0844  *
0845  * The RBSP format of the filler data is specified in Rec. ITU-T H.265
0846  * (02/2018) 7.3.2.8 Filler data RBSP syntax.
0847  *
0848  * Return: number of filler data bytes (including marker) or negative error
0849  */
0850 ssize_t nal_hevc_read_filler(const struct device *dev, void *src, size_t n)
0851 {
0852     struct rbsp rbsp;
0853     unsigned int forbidden_zero_bit;
0854     unsigned int nal_unit_type;
0855     unsigned int nuh_layer_id;
0856     unsigned int nuh_temporal_id_plus1;
0857
0858     if (!src)
0859         return -EINVAL;
0860
0861     rbsp_init(&rbsp, src, n, &read);
0862
0863     nal_hevc_read_start_code_prefix(&rbsp);
0864
0865     rbsp_bit(&rbsp, &forbidden_zero_bit);
0866     rbsp_bits(&rbsp, 6, &nal_unit_type);
0867     rbsp_bits(&rbsp, 6, &nuh_layer_id);
0868     rbsp_bits(&rbsp, 3, &nuh_temporal_id_plus1);
0869
0870     if (rbsp.error)
0871         return rbsp.error;
0872     if (forbidden_zero_bit != 0 ||
0873         nal_unit_type != FD_NUT)
0874         return -EINVAL;
0875
0876     nal_hevc_read_filler_data(&rbsp);
0877     rbsp_trailing_bits(&rbsp);
0878
0879     if (rbsp.error)
0880         return rbsp.error;
0881
0882     return DIV_ROUND_UP(rbsp.pos, 8);
0883 }
0884 EXPORT_SYMBOL_GPL(nal_hevc_read_filler);