pci/tw68/tw68-risc.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  *  tw68_risc.c
0004  *  Part of the device driver for Techwell 68xx based cards
0005  *
0006  *  Much of this code is derived from the cx88 and sa7134 drivers, which
0007  *  were in turn derived from the bt87x driver.  The original work was by
0008  *  Gerd Knorr; more recently the code was enhanced by Mauro Carvalho Chehab,
0009  *  Hans Verkuil, Andy Walls and many others.  Their work is gratefully
0010  *  acknowledged.  Full credit goes to them - any problems within this code
0011  *  are mine.
0012  *
0013  *  Copyright (C) 2009  William M. Brack
0014  *
0015  *  Refactored and updated to the latest v4l core frameworks:
0016  *
0017  *  Copyright (C) 2014 Hans Verkuil <hverkuil@xs4all.nl>
0018  */
0019
0020 #include "tw68.h"
0021
0022 /**
0023  * tw68_risc_field
0024  *  @rp:    pointer to current risc program position
0025  *  @sglist:    pointer to "scatter-gather list" of buffer pointers
0026  *  @offset:    offset to target memory buffer
0027  *  @sync_line: 0 -> no sync, 1 -> odd sync, 2 -> even sync
0028  *  @bpl:   number of bytes per scan line
0029  *  @padding:   number of bytes of padding to add
0030  *  @lines: number of lines in field
0031  *  @jump:  insert a jump at the start
0032  */
0033 static __le32 *tw68_risc_field(__le32 *rp, struct scatterlist *sglist,
0034                 unsigned int offset, u32 sync_line,
0035                 unsigned int bpl, unsigned int padding,
0036                 unsigned int lines, bool jump)
0037 {
0038     struct scatterlist *sg;
0039     unsigned int line, todo, done;
0040
0041     if (jump) {
0042         *(rp++) = cpu_to_le32(RISC_JUMP);
0043         *(rp++) = 0;
0044     }
0045
0046     /* sync instruction */
0047     if (sync_line == 1)
0048         *(rp++) = cpu_to_le32(RISC_SYNCO);
0049     else
0050         *(rp++) = cpu_to_le32(RISC_SYNCE);
0051     *(rp++) = 0;
0052
0053     /* scan lines */
0054     sg = sglist;
0055     for (line = 0; line < lines; line++) {
0056         /* calculate next starting position */
0057         while (offset && offset >= sg_dma_len(sg)) {
0058             offset -= sg_dma_len(sg);
0059             sg = sg_next(sg);
0060         }
0061         if (bpl <= sg_dma_len(sg) - offset) {
0062             /* fits into current chunk */
0063             *(rp++) = cpu_to_le32(RISC_LINESTART |
0064                           /* (offset<<12) |*/  bpl);
0065             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
0066             offset += bpl;
0067         } else {
0068             /*
0069              * scanline needs to be split.  Put the start in
0070              * whatever memory remains using RISC_LINESTART,
0071              * then the remainder into following addresses
0072              * given by the scatter-gather list.
0073              */
0074             todo = bpl; /* one full line to be done */
0075             /* first fragment */
0076             done = (sg_dma_len(sg) - offset);
0077             *(rp++) = cpu_to_le32(RISC_LINESTART |
0078                         (7 << 24) |
0079                         done);
0080             *(rp++) = cpu_to_le32(sg_dma_address(sg) + offset);
0081             todo -= done;
0082             sg = sg_next(sg);
0083             /* succeeding fragments have no offset */
0084             while (todo > sg_dma_len(sg)) {
0085                 *(rp++) = cpu_to_le32(RISC_INLINE |
0086                         (done << 12) |
0087                         sg_dma_len(sg));
0088                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
0089                 todo -= sg_dma_len(sg);
0090                 sg = sg_next(sg);
0091                 done += sg_dma_len(sg);
0092             }
0093             if (todo) {
0094                 /* final chunk - offset 0, count 'todo' */
0095                 *(rp++) = cpu_to_le32(RISC_INLINE |
0096                             (done << 12) |
0097                             todo);
0098                 *(rp++) = cpu_to_le32(sg_dma_address(sg));
0099             }
0100             offset = todo;
0101         }
0102         offset += padding;
0103     }
0104
0105     return rp;
0106 }
0107
0108 /**
0109  * tw68_risc_buffer
0110  *
0111  *  This routine is called by tw68-video.  It allocates
0112  *  memory for the dma controller "program" and then fills in that
0113  *  memory with the appropriate "instructions".
0114  *
0115  *  @pci:       structure with info about the pci
0116  *          slot which our device is in.
0117  *  @buf:       structure with info about the memory
0118  *          used for our controller program.
0119  *  @sglist:    scatter-gather list entry
0120  *  @top_offset:    offset within the risc program area for the
0121  *          first odd frame line
0122  *  @bottom_offset: offset within the risc program area for the
0123  *          first even frame line
0124  *  @bpl:       number of data bytes per scan line
0125  *  @padding:   number of extra bytes to add at end of line
0126  *  @lines:     number of scan lines
0127  */
0128 int tw68_risc_buffer(struct pci_dev *pci,
0129             struct tw68_buf *buf,
0130             struct scatterlist *sglist,
0131             unsigned int top_offset,
0132             unsigned int bottom_offset,
0133             unsigned int bpl,
0134             unsigned int padding,
0135             unsigned int lines)
0136 {
0137     u32 instructions, fields;
0138     __le32 *rp;
0139
0140     fields = 0;
0141     if (UNSET != top_offset)
0142         fields++;
0143     if (UNSET != bottom_offset)
0144         fields++;
0145     /*
0146      * estimate risc mem: worst case is one write per page border +
0147      * one write per scan line + syncs + 2 jumps (all 2 dwords).
0148      * Padding can cause next bpl to start close to a page border.
0149      * First DMA region may be smaller than PAGE_SIZE
0150      */
0151     instructions  = fields * (1 + (((bpl + padding) * lines) /
0152              PAGE_SIZE) + lines) + 4;
0153     buf->size = instructions * 8;
0154     buf->cpu = dma_alloc_coherent(&pci->dev, buf->size, &buf->dma,
0155                       GFP_KERNEL);
0156     if (buf->cpu == NULL)
0157         return -ENOMEM;
0158
0159     /* write risc instructions */
0160     rp = buf->cpu;
0161     if (UNSET != top_offset)    /* generates SYNCO */
0162         rp = tw68_risc_field(rp, sglist, top_offset, 1,
0163                      bpl, padding, lines, true);
0164     if (UNSET != bottom_offset) /* generates SYNCE */
0165         rp = tw68_risc_field(rp, sglist, bottom_offset, 2,
0166                      bpl, padding, lines, top_offset == UNSET);
0167
0168     /* save pointer to jmp instruction address */
0169     buf->jmp = rp;
0170     buf->cpu[1] = cpu_to_le32(buf->dma + 8);
0171     /* assure risc buffer hasn't overflowed */
0172     BUG_ON((buf->jmp - buf->cpu + 2) * sizeof(buf->cpu[0]) > buf->size);
0173     return 0;
0174 }
0175
0176 #if 0
0177 /* ------------------------------------------------------------------ */
0178 /* debug helper code                                                  */
0179
0180 static void tw68_risc_decode(u32 risc, u32 addr)
0181 {
0182 #define RISC_OP(reg)    (((reg) >> 28) & 7)
0183     static struct instr_details {
0184         char *name;
0185         u8 has_data_type;
0186         u8 has_byte_info;
0187         u8 has_addr;
0188     } instr[8] = {
0189         [RISC_OP(RISC_SYNCO)]     = {"syncOdd", 0, 0, 0},
0190         [RISC_OP(RISC_SYNCE)]     = {"syncEven", 0, 0, 0},
0191         [RISC_OP(RISC_JUMP)]      = {"jump", 0, 0, 1},
0192         [RISC_OP(RISC_LINESTART)] = {"lineStart", 1, 1, 1},
0193         [RISC_OP(RISC_INLINE)]    = {"inline", 1, 1, 1},
0194     };
0195     u32 p;
0196
0197     p = RISC_OP(risc);
0198     if (!(risc & 0x80000000) || !instr[p].name) {
0199         pr_debug("0x%08x [ INVALID ]\n", risc);
0200         return;
0201     }
0202     pr_debug("0x%08x %-9s IRQ=%d",
0203         risc, instr[p].name, (risc >> 27) & 1);
0204     if (instr[p].has_data_type)
0205         pr_debug(" Type=%d", (risc >> 24) & 7);
0206     if (instr[p].has_byte_info)
0207         pr_debug(" Start=0x%03x Count=%03u",
0208             (risc >> 12) & 0xfff, risc & 0xfff);
0209     if (instr[p].has_addr)
0210         pr_debug(" StartAddr=0x%08x", addr);
0211     pr_debug("\n");
0212 }
0213
0214 void tw68_risc_program_dump(struct tw68_core *core, struct tw68_buf *buf)
0215 {
0216     const __le32 *addr;
0217
0218     pr_debug("%s: risc_program_dump: risc=%p, buf->cpu=0x%p, buf->jmp=0x%p\n",
0219           core->name, buf, buf->cpu, buf->jmp);
0220     for (addr = buf->cpu; addr <= buf->jmp; addr += 2)
0221         tw68_risc_decode(*addr, *(addr+1));
0222 }
0223 #endif