pci/tw5864/tw5864.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  TW5864 driver  - common header file
0004  *
0005  *  Copyright (C) 2016 Bluecherry, LLC <maintainers@bluecherrydvr.com>
0006  */
0007
0008 #include <linux/pci.h>
0009 #include <linux/videodev2.h>
0010 #include <linux/notifier.h>
0011 #include <linux/delay.h>
0012 #include <linux/mutex.h>
0013 #include <linux/io.h>
0014 #include <linux/interrupt.h>
0015
0016 #include <media/v4l2-common.h>
0017 #include <media/v4l2-ioctl.h>
0018 #include <media/v4l2-ctrls.h>
0019 #include <media/v4l2-device.h>
0020 #include <media/videobuf2-dma-sg.h>
0021
0022 #include "tw5864-reg.h"
0023
0024 #define PCI_DEVICE_ID_TECHWELL_5864 0x5864
0025
0026 #define TW5864_NORMS V4L2_STD_ALL
0027
0028 /* ----------------------------------------------------------- */
0029 /* card configuration   */
0030
0031 #define TW5864_INPUTS 4
0032
0033 /* The TW5864 uses 192 (16x12) detection cells in full screen for motion
0034  * detection. Each detection cell is composed of 44 pixels and 20 lines for
0035  * NTSC and 24 lines for PAL.
0036  */
0037 #define MD_CELLS_HOR 16
0038 #define MD_CELLS_VERT 12
0039 #define MD_CELLS (MD_CELLS_HOR * MD_CELLS_VERT)
0040
0041 #define H264_VLC_BUF_SIZE 0x80000
0042 #define H264_MV_BUF_SIZE 0x2000 /* device writes 5396 bytes */
0043 #define QP_VALUE 28
0044 #define MAX_GOP_SIZE 255
0045 #define GOP_SIZE MAX_GOP_SIZE
0046
0047 enum resolution {
0048     D1 = 1,
0049     HD1 = 2, /* half d1 - 360x(240|288) */
0050     CIF = 3,
0051     QCIF = 4,
0052 };
0053
0054 /* ----------------------------------------------------------- */
0055 /* device / file handle status                                 */
0056
0057 struct tw5864_dev; /* forward delclaration */
0058
0059 /* buffer for one video/vbi/ts frame */
0060 struct tw5864_buf {
0061     struct vb2_v4l2_buffer vb;
0062     struct list_head list;
0063
0064     unsigned int size;
0065 };
0066
0067 struct tw5864_dma_buf {
0068     void *addr;
0069     dma_addr_t dma_addr;
0070 };
0071
0072 enum tw5864_vid_std {
0073     STD_NTSC = 0, /* NTSC (M) */
0074     STD_PAL = 1, /* PAL (B, D, G, H, I) */
0075     STD_SECAM = 2, /* SECAM */
0076     STD_NTSC443 = 3, /* NTSC4.43 */
0077     STD_PAL_M = 4, /* PAL (M) */
0078     STD_PAL_CN = 5, /* PAL (CN) */
0079     STD_PAL_60 = 6, /* PAL 60 */
0080     STD_INVALID = 7,
0081     STD_AUTO = 7,
0082 };
0083
0084 struct tw5864_input {
0085     int nr; /* input number */
0086     struct tw5864_dev *root;
0087     struct mutex lock; /* used for vidq and vdev */
0088     spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
0089     struct video_device vdev;
0090     struct v4l2_ctrl_handler hdl;
0091     struct vb2_queue vidq;
0092     struct list_head active;
0093     enum resolution resolution;
0094     unsigned int width, height;
0095     unsigned int frame_seqno;
0096     unsigned int frame_gop_seqno;
0097     unsigned int h264_idr_pic_id;
0098     int enabled;
0099     enum tw5864_vid_std std;
0100     v4l2_std_id v4l2_std;
0101     int tail_nb_bits;
0102     u8 tail;
0103     u8 *buf_cur_ptr;
0104     int buf_cur_space_left;
0105
0106     u32 reg_interlacing;
0107     u32 reg_vlc;
0108     u32 reg_dsp_codec;
0109     u32 reg_dsp;
0110     u32 reg_emu;
0111     u32 reg_dsp_qp;
0112     u32 reg_dsp_ref_mvp_lambda;
0113     u32 reg_dsp_i4x4_weight;
0114     u32 buf_id;
0115
0116     struct tw5864_buf *vb;
0117
0118     struct v4l2_ctrl *md_threshold_grid_ctrl;
0119     u16 md_threshold_grid_values[12 * 16];
0120     int qp;
0121     int gop;
0122
0123     /*
0124      * In (1/MAX_FPS) units.
0125      * For max FPS (default), set to 1.
0126      * For 1 FPS, set to e.g. 32.
0127      */
0128     int frame_interval;
0129     unsigned long new_frame_deadline;
0130 };
0131
0132 struct tw5864_h264_frame {
0133     struct tw5864_dma_buf vlc;
0134     struct tw5864_dma_buf mv;
0135     int vlc_len;
0136     u32 checksum;
0137     struct tw5864_input *input;
0138     u64 timestamp;
0139     unsigned int seqno;
0140     unsigned int gop_seqno;
0141 };
0142
0143 /* global device status */
0144 struct tw5864_dev {
0145     spinlock_t slock; /* used for sync between ISR, tasklet & V4L2 API */
0146     struct v4l2_device v4l2_dev;
0147     struct tw5864_input inputs[TW5864_INPUTS];
0148 #define H264_BUF_CNT 4
0149     struct tw5864_h264_frame h264_buf[H264_BUF_CNT];
0150     int h264_buf_r_index;
0151     int h264_buf_w_index;
0152
0153     struct tasklet_struct tasklet;
0154
0155     int encoder_busy;
0156     /* Input number to check next for ready raw picture (in RR fashion) */
0157     int next_input;
0158
0159     /* pci i/o */
0160     char name[64];
0161     struct pci_dev *pci;
0162     void __iomem *mmio;
0163     u32 irqmask;
0164 };
0165
0166 #define tw_readl(reg) readl(dev->mmio + reg)
0167 #define tw_mask_readl(reg, mask) \
0168     (tw_readl(reg) & (mask))
0169 #define tw_mask_shift_readl(reg, mask, shift) \
0170     (tw_mask_readl((reg), ((mask) << (shift))) >> (shift))
0171
0172 #define tw_writel(reg, value) writel((value), dev->mmio + reg)
0173 #define tw_mask_writel(reg, mask, value) \
0174     tw_writel(reg, (tw_readl(reg) & ~(mask)) | ((value) & (mask)))
0175 #define tw_mask_shift_writel(reg, mask, shift, value) \
0176     tw_mask_writel((reg), ((mask) << (shift)), ((value) << (shift)))
0177
0178 #define tw_setl(reg, bit) tw_writel((reg), tw_readl(reg) | (bit))
0179 #define tw_clearl(reg, bit) tw_writel((reg), tw_readl(reg) & ~(bit))
0180
0181 u8 tw5864_indir_readb(struct tw5864_dev *dev, u16 addr);
0182 #define tw_indir_readb(addr) tw5864_indir_readb(dev, addr)
0183 void tw5864_indir_writeb(struct tw5864_dev *dev, u16 addr, u8 data);
0184 #define tw_indir_writeb(addr, data) tw5864_indir_writeb(dev, addr, data)
0185
0186 void tw5864_irqmask_apply(struct tw5864_dev *dev);
0187 int tw5864_video_init(struct tw5864_dev *dev, int *video_nr);
0188 void tw5864_video_fini(struct tw5864_dev *dev);
0189 void tw5864_prepare_frame_headers(struct tw5864_input *input);
0190 void tw5864_h264_put_stream_header(u8 **buf, size_t *space_left, int qp,
0191                    int width, int height);
0192 void tw5864_h264_put_slice_header(u8 **buf, size_t *space_left,
0193                   unsigned int idr_pic_id,
0194                   unsigned int frame_gop_seqno,
0195                   int *tail_nb_bits, u8 *tail);
0196 void tw5864_request_encoded_frame(struct tw5864_input *input);