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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * budget-ci.c: driver for the SAA7146 based Budget DVB cards
0004  *
0005  * Compiled from various sources by Michael Hunold <michael@mihu.de>
0006  *
0007  *     msp430 IR support contributed by Jack Thomasson <jkt@Helius.COM>
0008  *     partially based on the Siemens DVB driver by Ralph+Marcus Metzler
0009  *
0010  * CI interface support (c) 2004 Andrew de Quincey <adq_dvb@lidskialf.net>
0011  *
0012  * the project's page is at https://linuxtv.org
0013  */
0014 
0015 #include <linux/module.h>
0016 #include <linux/errno.h>
0017 #include <linux/slab.h>
0018 #include <linux/interrupt.h>
0019 #include <linux/spinlock.h>
0020 #include <media/rc-core.h>
0021 
0022 #include "budget.h"
0023 
0024 #include <media/dvb_ca_en50221.h>
0025 #include "stv0299.h"
0026 #include "stv0297.h"
0027 #include "tda1004x.h"
0028 #include "stb0899_drv.h"
0029 #include "stb0899_reg.h"
0030 #include "stb0899_cfg.h"
0031 #include "stb6100.h"
0032 #include "stb6100_cfg.h"
0033 #include "lnbp21.h"
0034 #include "bsbe1.h"
0035 #include "bsru6.h"
0036 #include "tda1002x.h"
0037 #include "tda827x.h"
0038 #include "bsbe1-d01a.h"
0039 
0040 #define MODULE_NAME "budget_ci"
0041 
0042 /*
0043  * Regarding DEBIADDR_IR:
0044  * Some CI modules hang if random addresses are read.
0045  * Using address 0x4000 for the IR read means that we
0046  * use the same address as for CI version, which should
0047  * be a safe default.
0048  */
0049 #define DEBIADDR_IR     0x4000
0050 #define DEBIADDR_CICONTROL  0x0000
0051 #define DEBIADDR_CIVERSION  0x4000
0052 #define DEBIADDR_IO     0x1000
0053 #define DEBIADDR_ATTR       0x3000
0054 
0055 #define CICONTROL_RESET     0x01
0056 #define CICONTROL_ENABLETS  0x02
0057 #define CICONTROL_CAMDETECT 0x08
0058 
0059 #define DEBICICTL       0x00420000
0060 #define DEBICICAM       0x02420000
0061 
0062 #define SLOTSTATUS_NONE     1
0063 #define SLOTSTATUS_PRESENT  2
0064 #define SLOTSTATUS_RESET    4
0065 #define SLOTSTATUS_READY    8
0066 #define SLOTSTATUS_OCCUPIED (SLOTSTATUS_PRESENT|SLOTSTATUS_RESET|SLOTSTATUS_READY)
0067 
0068 /* RC5 device wildcard */
0069 #define IR_DEVICE_ANY       255
0070 
0071 static int rc5_device = -1;
0072 module_param(rc5_device, int, 0644);
0073 MODULE_PARM_DESC(rc5_device, "only IR commands to given RC5 device (device = 0 - 31, any device = 255, default: autodetect)");
0074 
0075 static int ir_debug;
0076 module_param(ir_debug, int, 0644);
0077 MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
0078 
0079 DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
0080 
0081 struct budget_ci_ir {
0082     struct rc_dev *dev;
0083     struct tasklet_struct msp430_irq_tasklet;
0084     char name[72]; /* 40 + 32 for (struct saa7146_dev).name */
0085     char phys[32];
0086     int rc5_device;
0087     u32 ir_key;
0088     bool have_command;
0089     bool full_rc5;      /* Outputs a full RC5 code */
0090 };
0091 
0092 struct budget_ci {
0093     struct budget budget;
0094     struct tasklet_struct ciintf_irq_tasklet;
0095     int slot_status;
0096     int ci_irq;
0097     struct dvb_ca_en50221 ca;
0098     struct budget_ci_ir ir;
0099     u8 tuner_pll_address; /* used for philips_tdm1316l configs */
0100 };
0101 
0102 static void msp430_ir_interrupt(struct tasklet_struct *t)
0103 {
0104     struct budget_ci_ir *ir = from_tasklet(ir, t, msp430_irq_tasklet);
0105     struct budget_ci *budget_ci = container_of(ir, typeof(*budget_ci), ir);
0106     struct rc_dev *dev = budget_ci->ir.dev;
0107     u32 command = ttpci_budget_debiread(&budget_ci->budget, DEBINOSWAP, DEBIADDR_IR, 2, 1, 0) >> 8;
0108 
0109     /*
0110      * The msp430 chip can generate two different bytes, command and device
0111      *
0112      * type1: X1CCCCCC, C = command bits (0 - 63)
0113      * type2: X0TDDDDD, D = device bits (0 - 31), T = RC5 toggle bit
0114      *
0115      * Each signal from the remote control can generate one or more command
0116      * bytes and one or more device bytes. For the repeated bytes, the
0117      * highest bit (X) is set. The first command byte is always generated
0118      * before the first device byte. Other than that, no specific order
0119      * seems to apply. To make life interesting, bytes can also be lost.
0120      *
0121      * Only when we have a command and device byte, a keypress is
0122      * generated.
0123      */
0124 
0125     if (ir_debug)
0126         printk("budget_ci: received byte 0x%02x\n", command);
0127 
0128     /* Remove repeat bit, we use every command */
0129     command = command & 0x7f;
0130 
0131     /* Is this a RC5 command byte? */
0132     if (command & 0x40) {
0133         budget_ci->ir.have_command = true;
0134         budget_ci->ir.ir_key = command & 0x3f;
0135         return;
0136     }
0137 
0138     /* It's a RC5 device byte */
0139     if (!budget_ci->ir.have_command)
0140         return;
0141     budget_ci->ir.have_command = false;
0142 
0143     if (budget_ci->ir.rc5_device != IR_DEVICE_ANY &&
0144         budget_ci->ir.rc5_device != (command & 0x1f))
0145         return;
0146 
0147     if (budget_ci->ir.full_rc5) {
0148         rc_keydown(dev, RC_PROTO_RC5,
0149                RC_SCANCODE_RC5(budget_ci->ir.rc5_device, budget_ci->ir.ir_key),
0150                !!(command & 0x20));
0151         return;
0152     }
0153 
0154     /* FIXME: We should generate complete scancodes for all devices */
0155     rc_keydown(dev, RC_PROTO_UNKNOWN, budget_ci->ir.ir_key,
0156            !!(command & 0x20));
0157 }
0158 
0159 static int msp430_ir_init(struct budget_ci *budget_ci)
0160 {
0161     struct saa7146_dev *saa = budget_ci->budget.dev;
0162     struct rc_dev *dev;
0163     int error;
0164 
0165     dev = rc_allocate_device(RC_DRIVER_SCANCODE);
0166     if (!dev) {
0167         printk(KERN_ERR "budget_ci: IR interface initialisation failed\n");
0168         return -ENOMEM;
0169     }
0170 
0171     snprintf(budget_ci->ir.name, sizeof(budget_ci->ir.name),
0172          "Budget-CI dvb ir receiver %s", saa->name);
0173     snprintf(budget_ci->ir.phys, sizeof(budget_ci->ir.phys),
0174          "pci-%s/ir0", pci_name(saa->pci));
0175 
0176     dev->driver_name = MODULE_NAME;
0177     dev->device_name = budget_ci->ir.name;
0178     dev->input_phys = budget_ci->ir.phys;
0179     dev->input_id.bustype = BUS_PCI;
0180     dev->input_id.version = 1;
0181     if (saa->pci->subsystem_vendor) {
0182         dev->input_id.vendor = saa->pci->subsystem_vendor;
0183         dev->input_id.product = saa->pci->subsystem_device;
0184     } else {
0185         dev->input_id.vendor = saa->pci->vendor;
0186         dev->input_id.product = saa->pci->device;
0187     }
0188     dev->dev.parent = &saa->pci->dev;
0189 
0190     if (rc5_device < 0)
0191         budget_ci->ir.rc5_device = IR_DEVICE_ANY;
0192     else
0193         budget_ci->ir.rc5_device = rc5_device;
0194 
0195     /* Select keymap and address */
0196     switch (budget_ci->budget.dev->pci->subsystem_device) {
0197     case 0x100c:
0198     case 0x100f:
0199     case 0x1011:
0200     case 0x1012:
0201         /* The hauppauge keymap is a superset of these remotes */
0202         dev->map_name = RC_MAP_HAUPPAUGE;
0203         budget_ci->ir.full_rc5 = true;
0204 
0205         if (rc5_device < 0)
0206             budget_ci->ir.rc5_device = 0x1f;
0207         break;
0208     case 0x1010:
0209     case 0x1017:
0210     case 0x1019:
0211     case 0x101a:
0212     case 0x101b:
0213         /* for the Technotrend 1500 bundled remote */
0214         dev->map_name = RC_MAP_TT_1500;
0215         break;
0216     default:
0217         /* unknown remote */
0218         dev->map_name = RC_MAP_BUDGET_CI_OLD;
0219         break;
0220     }
0221     if (!budget_ci->ir.full_rc5)
0222         dev->scancode_mask = 0xff;
0223 
0224     error = rc_register_device(dev);
0225     if (error) {
0226         printk(KERN_ERR "budget_ci: could not init driver for IR device (code %d)\n", error);
0227         rc_free_device(dev);
0228         return error;
0229     }
0230 
0231     budget_ci->ir.dev = dev;
0232 
0233     tasklet_setup(&budget_ci->ir.msp430_irq_tasklet, msp430_ir_interrupt);
0234 
0235     SAA7146_IER_ENABLE(saa, MASK_06);
0236     saa7146_setgpio(saa, 3, SAA7146_GPIO_IRQHI);
0237 
0238     return 0;
0239 }
0240 
0241 static void msp430_ir_deinit(struct budget_ci *budget_ci)
0242 {
0243     struct saa7146_dev *saa = budget_ci->budget.dev;
0244 
0245     SAA7146_IER_DISABLE(saa, MASK_06);
0246     saa7146_setgpio(saa, 3, SAA7146_GPIO_INPUT);
0247     tasklet_kill(&budget_ci->ir.msp430_irq_tasklet);
0248 
0249     rc_unregister_device(budget_ci->ir.dev);
0250 }
0251 
0252 static int ciintf_read_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address)
0253 {
0254     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0255 
0256     if (slot != 0)
0257         return -EINVAL;
0258 
0259     return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
0260                      DEBIADDR_ATTR | (address & 0xfff), 1, 1, 0);
0261 }
0262 
0263 static int ciintf_write_attribute_mem(struct dvb_ca_en50221 *ca, int slot, int address, u8 value)
0264 {
0265     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0266 
0267     if (slot != 0)
0268         return -EINVAL;
0269 
0270     return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
0271                       DEBIADDR_ATTR | (address & 0xfff), 1, value, 1, 0);
0272 }
0273 
0274 static int ciintf_read_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address)
0275 {
0276     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0277 
0278     if (slot != 0)
0279         return -EINVAL;
0280 
0281     return ttpci_budget_debiread(&budget_ci->budget, DEBICICAM,
0282                      DEBIADDR_IO | (address & 3), 1, 1, 0);
0283 }
0284 
0285 static int ciintf_write_cam_control(struct dvb_ca_en50221 *ca, int slot, u8 address, u8 value)
0286 {
0287     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0288 
0289     if (slot != 0)
0290         return -EINVAL;
0291 
0292     return ttpci_budget_debiwrite(&budget_ci->budget, DEBICICAM,
0293                       DEBIADDR_IO | (address & 3), 1, value, 1, 0);
0294 }
0295 
0296 static int ciintf_slot_reset(struct dvb_ca_en50221 *ca, int slot)
0297 {
0298     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0299     struct saa7146_dev *saa = budget_ci->budget.dev;
0300 
0301     if (slot != 0)
0302         return -EINVAL;
0303 
0304     if (budget_ci->ci_irq) {
0305         // trigger on RISING edge during reset so we know when READY is re-asserted
0306         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
0307     }
0308     budget_ci->slot_status = SLOTSTATUS_RESET;
0309     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
0310     msleep(1);
0311     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
0312                    CICONTROL_RESET, 1, 0);
0313 
0314     saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
0315     ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
0316     return 0;
0317 }
0318 
0319 static int ciintf_slot_shutdown(struct dvb_ca_en50221 *ca, int slot)
0320 {
0321     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0322     struct saa7146_dev *saa = budget_ci->budget.dev;
0323 
0324     if (slot != 0)
0325         return -EINVAL;
0326 
0327     saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTHI);
0328     ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTB);
0329     return 0;
0330 }
0331 
0332 static int ciintf_slot_ts_enable(struct dvb_ca_en50221 *ca, int slot)
0333 {
0334     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0335     struct saa7146_dev *saa = budget_ci->budget.dev;
0336     int tmp;
0337 
0338     if (slot != 0)
0339         return -EINVAL;
0340 
0341     saa7146_setgpio(saa, 1, SAA7146_GPIO_OUTLO);
0342 
0343     tmp = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
0344     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
0345                    tmp | CICONTROL_ENABLETS, 1, 0);
0346 
0347     ttpci_budget_set_video_port(saa, BUDGET_VIDEO_PORTA);
0348     return 0;
0349 }
0350 
0351 static void ciintf_interrupt(struct tasklet_struct *t)
0352 {
0353     struct budget_ci *budget_ci = from_tasklet(budget_ci, t,
0354                            ciintf_irq_tasklet);
0355     struct saa7146_dev *saa = budget_ci->budget.dev;
0356     unsigned int flags;
0357 
0358     // ensure we don't get spurious IRQs during initialisation
0359     if (!budget_ci->budget.ci_present)
0360         return;
0361 
0362     // read the CAM status
0363     flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
0364     if (flags & CICONTROL_CAMDETECT) {
0365 
0366         // GPIO should be set to trigger on falling edge if a CAM is present
0367         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
0368 
0369         if (budget_ci->slot_status & SLOTSTATUS_NONE) {
0370             // CAM insertion IRQ
0371             budget_ci->slot_status = SLOTSTATUS_PRESENT;
0372             dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
0373                              DVB_CA_EN50221_CAMCHANGE_INSERTED);
0374 
0375         } else if (budget_ci->slot_status & SLOTSTATUS_RESET) {
0376             // CAM ready (reset completed)
0377             budget_ci->slot_status = SLOTSTATUS_READY;
0378             dvb_ca_en50221_camready_irq(&budget_ci->ca, 0);
0379 
0380         } else if (budget_ci->slot_status & SLOTSTATUS_READY) {
0381             // FR/DA IRQ
0382             dvb_ca_en50221_frda_irq(&budget_ci->ca, 0);
0383         }
0384     } else {
0385 
0386         // trigger on rising edge if a CAM is not present - when a CAM is inserted, we
0387         // only want to get the IRQ when it sets READY. If we trigger on the falling edge,
0388         // the CAM might not actually be ready yet.
0389         saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
0390 
0391         // generate a CAM removal IRQ if we haven't already
0392         if (budget_ci->slot_status & SLOTSTATUS_OCCUPIED) {
0393             // CAM removal IRQ
0394             budget_ci->slot_status = SLOTSTATUS_NONE;
0395             dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0,
0396                              DVB_CA_EN50221_CAMCHANGE_REMOVED);
0397         }
0398     }
0399 }
0400 
0401 static int ciintf_poll_slot_status(struct dvb_ca_en50221 *ca, int slot, int open)
0402 {
0403     struct budget_ci *budget_ci = (struct budget_ci *) ca->data;
0404     unsigned int flags;
0405 
0406     // ensure we don't get spurious IRQs during initialisation
0407     if (!budget_ci->budget.ci_present)
0408         return -EINVAL;
0409 
0410     // read the CAM status
0411     flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
0412     if (flags & CICONTROL_CAMDETECT) {
0413         // mark it as present if it wasn't before
0414         if (budget_ci->slot_status & SLOTSTATUS_NONE) {
0415             budget_ci->slot_status = SLOTSTATUS_PRESENT;
0416         }
0417 
0418         // during a RESET, we check if we can read from IO memory to see when CAM is ready
0419         if (budget_ci->slot_status & SLOTSTATUS_RESET) {
0420             if (ciintf_read_attribute_mem(ca, slot, 0) == 0x1d) {
0421                 budget_ci->slot_status = SLOTSTATUS_READY;
0422             }
0423         }
0424     } else {
0425         budget_ci->slot_status = SLOTSTATUS_NONE;
0426     }
0427 
0428     if (budget_ci->slot_status != SLOTSTATUS_NONE) {
0429         if (budget_ci->slot_status & SLOTSTATUS_READY) {
0430             return DVB_CA_EN50221_POLL_CAM_PRESENT | DVB_CA_EN50221_POLL_CAM_READY;
0431         }
0432         return DVB_CA_EN50221_POLL_CAM_PRESENT;
0433     }
0434 
0435     return 0;
0436 }
0437 
0438 static int ciintf_init(struct budget_ci *budget_ci)
0439 {
0440     struct saa7146_dev *saa = budget_ci->budget.dev;
0441     int flags;
0442     int result;
0443     int ci_version;
0444     int ca_flags;
0445 
0446     memset(&budget_ci->ca, 0, sizeof(struct dvb_ca_en50221));
0447 
0448     // enable DEBI pins
0449     saa7146_write(saa, MC1, MASK_27 | MASK_11);
0450 
0451     // test if it is there
0452     ci_version = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CIVERSION, 1, 1, 0);
0453     if ((ci_version & 0xa0) != 0xa0) {
0454         result = -ENODEV;
0455         goto error;
0456     }
0457 
0458     // determine whether a CAM is present or not
0459     flags = ttpci_budget_debiread(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 1, 0);
0460     budget_ci->slot_status = SLOTSTATUS_NONE;
0461     if (flags & CICONTROL_CAMDETECT)
0462         budget_ci->slot_status = SLOTSTATUS_PRESENT;
0463 
0464     // version 0xa2 of the CI firmware doesn't generate interrupts
0465     if (ci_version == 0xa2) {
0466         ca_flags = 0;
0467         budget_ci->ci_irq = 0;
0468     } else {
0469         ca_flags = DVB_CA_EN50221_FLAG_IRQ_CAMCHANGE |
0470                 DVB_CA_EN50221_FLAG_IRQ_FR |
0471                 DVB_CA_EN50221_FLAG_IRQ_DA;
0472         budget_ci->ci_irq = 1;
0473     }
0474 
0475     // register CI interface
0476     budget_ci->ca.owner = THIS_MODULE;
0477     budget_ci->ca.read_attribute_mem = ciintf_read_attribute_mem;
0478     budget_ci->ca.write_attribute_mem = ciintf_write_attribute_mem;
0479     budget_ci->ca.read_cam_control = ciintf_read_cam_control;
0480     budget_ci->ca.write_cam_control = ciintf_write_cam_control;
0481     budget_ci->ca.slot_reset = ciintf_slot_reset;
0482     budget_ci->ca.slot_shutdown = ciintf_slot_shutdown;
0483     budget_ci->ca.slot_ts_enable = ciintf_slot_ts_enable;
0484     budget_ci->ca.poll_slot_status = ciintf_poll_slot_status;
0485     budget_ci->ca.data = budget_ci;
0486     if ((result = dvb_ca_en50221_init(&budget_ci->budget.dvb_adapter,
0487                       &budget_ci->ca,
0488                       ca_flags, 1)) != 0) {
0489         printk("budget_ci: CI interface detected, but initialisation failed.\n");
0490         goto error;
0491     }
0492 
0493     // Setup CI slot IRQ
0494     if (budget_ci->ci_irq) {
0495         tasklet_setup(&budget_ci->ciintf_irq_tasklet, ciintf_interrupt);
0496         if (budget_ci->slot_status != SLOTSTATUS_NONE) {
0497             saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQLO);
0498         } else {
0499             saa7146_setgpio(saa, 0, SAA7146_GPIO_IRQHI);
0500         }
0501         SAA7146_IER_ENABLE(saa, MASK_03);
0502     }
0503 
0504     // enable interface
0505     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
0506                    CICONTROL_RESET, 1, 0);
0507 
0508     // success!
0509     printk("budget_ci: CI interface initialised\n");
0510     budget_ci->budget.ci_present = 1;
0511 
0512     // forge a fake CI IRQ so the CAM state is setup correctly
0513     if (budget_ci->ci_irq) {
0514         flags = DVB_CA_EN50221_CAMCHANGE_REMOVED;
0515         if (budget_ci->slot_status != SLOTSTATUS_NONE)
0516             flags = DVB_CA_EN50221_CAMCHANGE_INSERTED;
0517         dvb_ca_en50221_camchange_irq(&budget_ci->ca, 0, flags);
0518     }
0519 
0520     return 0;
0521 
0522 error:
0523     saa7146_write(saa, MC1, MASK_27);
0524     return result;
0525 }
0526 
0527 static void ciintf_deinit(struct budget_ci *budget_ci)
0528 {
0529     struct saa7146_dev *saa = budget_ci->budget.dev;
0530 
0531     // disable CI interrupts
0532     if (budget_ci->ci_irq) {
0533         SAA7146_IER_DISABLE(saa, MASK_03);
0534         saa7146_setgpio(saa, 0, SAA7146_GPIO_INPUT);
0535         tasklet_kill(&budget_ci->ciintf_irq_tasklet);
0536     }
0537 
0538     // reset interface
0539     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1, 0, 1, 0);
0540     msleep(1);
0541     ttpci_budget_debiwrite(&budget_ci->budget, DEBICICTL, DEBIADDR_CICONTROL, 1,
0542                    CICONTROL_RESET, 1, 0);
0543 
0544     // disable TS data stream to CI interface
0545     saa7146_setgpio(saa, 1, SAA7146_GPIO_INPUT);
0546 
0547     // release the CA device
0548     dvb_ca_en50221_release(&budget_ci->ca);
0549 
0550     // disable DEBI pins
0551     saa7146_write(saa, MC1, MASK_27);
0552 }
0553 
0554 static void budget_ci_irq(struct saa7146_dev *dev, u32 * isr)
0555 {
0556     struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
0557 
0558     dprintk(8, "dev: %p, budget_ci: %p\n", dev, budget_ci);
0559 
0560     if (*isr & MASK_06)
0561         tasklet_schedule(&budget_ci->ir.msp430_irq_tasklet);
0562 
0563     if (*isr & MASK_10)
0564         ttpci_budget_irq10_handler(dev, isr);
0565 
0566     if ((*isr & MASK_03) && (budget_ci->budget.ci_present) && (budget_ci->ci_irq))
0567         tasklet_schedule(&budget_ci->ciintf_irq_tasklet);
0568 }
0569 
0570 static u8 philips_su1278_tt_inittab[] = {
0571     0x01, 0x0f,
0572     0x02, 0x30,
0573     0x03, 0x00,
0574     0x04, 0x5b,
0575     0x05, 0x85,
0576     0x06, 0x02,
0577     0x07, 0x00,
0578     0x08, 0x02,
0579     0x09, 0x00,
0580     0x0C, 0x01,
0581     0x0D, 0x81,
0582     0x0E, 0x44,
0583     0x0f, 0x14,
0584     0x10, 0x3c,
0585     0x11, 0x84,
0586     0x12, 0xda,
0587     0x13, 0x97,
0588     0x14, 0x95,
0589     0x15, 0xc9,
0590     0x16, 0x19,
0591     0x17, 0x8c,
0592     0x18, 0x59,
0593     0x19, 0xf8,
0594     0x1a, 0xfe,
0595     0x1c, 0x7f,
0596     0x1d, 0x00,
0597     0x1e, 0x00,
0598     0x1f, 0x50,
0599     0x20, 0x00,
0600     0x21, 0x00,
0601     0x22, 0x00,
0602     0x23, 0x00,
0603     0x28, 0x00,
0604     0x29, 0x28,
0605     0x2a, 0x14,
0606     0x2b, 0x0f,
0607     0x2c, 0x09,
0608     0x2d, 0x09,
0609     0x31, 0x1f,
0610     0x32, 0x19,
0611     0x33, 0xfc,
0612     0x34, 0x93,
0613     0xff, 0xff
0614 };
0615 
0616 static int philips_su1278_tt_set_symbol_rate(struct dvb_frontend *fe, u32 srate, u32 ratio)
0617 {
0618     stv0299_writereg(fe, 0x0e, 0x44);
0619     if (srate >= 10000000) {
0620         stv0299_writereg(fe, 0x13, 0x97);
0621         stv0299_writereg(fe, 0x14, 0x95);
0622         stv0299_writereg(fe, 0x15, 0xc9);
0623         stv0299_writereg(fe, 0x17, 0x8c);
0624         stv0299_writereg(fe, 0x1a, 0xfe);
0625         stv0299_writereg(fe, 0x1c, 0x7f);
0626         stv0299_writereg(fe, 0x2d, 0x09);
0627     } else {
0628         stv0299_writereg(fe, 0x13, 0x99);
0629         stv0299_writereg(fe, 0x14, 0x8d);
0630         stv0299_writereg(fe, 0x15, 0xce);
0631         stv0299_writereg(fe, 0x17, 0x43);
0632         stv0299_writereg(fe, 0x1a, 0x1d);
0633         stv0299_writereg(fe, 0x1c, 0x12);
0634         stv0299_writereg(fe, 0x2d, 0x05);
0635     }
0636     stv0299_writereg(fe, 0x0e, 0x23);
0637     stv0299_writereg(fe, 0x0f, 0x94);
0638     stv0299_writereg(fe, 0x10, 0x39);
0639     stv0299_writereg(fe, 0x15, 0xc9);
0640 
0641     stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);
0642     stv0299_writereg(fe, 0x20, (ratio >> 8) & 0xff);
0643     stv0299_writereg(fe, 0x21, (ratio) & 0xf0);
0644 
0645     return 0;
0646 }
0647 
0648 static int philips_su1278_tt_tuner_set_params(struct dvb_frontend *fe)
0649 {
0650     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0651     struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
0652     u32 div;
0653     u8 buf[4];
0654     struct i2c_msg msg = {.addr = 0x60,.flags = 0,.buf = buf,.len = sizeof(buf) };
0655 
0656     if ((p->frequency < 950000) || (p->frequency > 2150000))
0657         return -EINVAL;
0658 
0659     div = (p->frequency + (500 - 1)) / 500; /* round correctly */
0660     buf[0] = (div >> 8) & 0x7f;
0661     buf[1] = div & 0xff;
0662     buf[2] = 0x80 | ((div & 0x18000) >> 10) | 2;
0663     buf[3] = 0x20;
0664 
0665     if (p->symbol_rate < 4000000)
0666         buf[3] |= 1;
0667 
0668     if (p->frequency < 1250000)
0669         buf[3] |= 0;
0670     else if (p->frequency < 1550000)
0671         buf[3] |= 0x40;
0672     else if (p->frequency < 2050000)
0673         buf[3] |= 0x80;
0674     else if (p->frequency < 2150000)
0675         buf[3] |= 0xC0;
0676 
0677     if (fe->ops.i2c_gate_ctrl)
0678         fe->ops.i2c_gate_ctrl(fe, 1);
0679     if (i2c_transfer(&budget_ci->budget.i2c_adap, &msg, 1) != 1)
0680         return -EIO;
0681     return 0;
0682 }
0683 
0684 static const struct stv0299_config philips_su1278_tt_config = {
0685 
0686     .demod_address = 0x68,
0687     .inittab = philips_su1278_tt_inittab,
0688     .mclk = 64000000UL,
0689     .invert = 0,
0690     .skip_reinit = 1,
0691     .lock_output = STV0299_LOCKOUTPUT_1,
0692     .volt13_op0_op1 = STV0299_VOLT13_OP1,
0693     .min_delay_ms = 50,
0694     .set_symbol_rate = philips_su1278_tt_set_symbol_rate,
0695 };
0696 
0697 
0698 
0699 static int philips_tdm1316l_tuner_init(struct dvb_frontend *fe)
0700 {
0701     struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
0702     static u8 td1316_init[] = { 0x0b, 0xf5, 0x85, 0xab };
0703     static u8 disable_mc44BC374c[] = { 0x1d, 0x74, 0xa0, 0x68 };
0704     struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = td1316_init,.len =
0705             sizeof(td1316_init) };
0706 
0707     // setup PLL configuration
0708     if (fe->ops.i2c_gate_ctrl)
0709         fe->ops.i2c_gate_ctrl(fe, 1);
0710     if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
0711         return -EIO;
0712     msleep(1);
0713 
0714     // disable the mc44BC374c (do not check for errors)
0715     tuner_msg.addr = 0x65;
0716     tuner_msg.buf = disable_mc44BC374c;
0717     tuner_msg.len = sizeof(disable_mc44BC374c);
0718     if (fe->ops.i2c_gate_ctrl)
0719         fe->ops.i2c_gate_ctrl(fe, 1);
0720     if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1) {
0721         if (fe->ops.i2c_gate_ctrl)
0722             fe->ops.i2c_gate_ctrl(fe, 1);
0723         i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1);
0724     }
0725 
0726     return 0;
0727 }
0728 
0729 static int philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe)
0730 {
0731     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0732     struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
0733     u8 tuner_buf[4];
0734     struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,.flags = 0,.buf = tuner_buf,.len = sizeof(tuner_buf) };
0735     int tuner_frequency = 0;
0736     u8 band, cp, filter;
0737 
0738     // determine charge pump
0739     tuner_frequency = p->frequency + 36130000;
0740     if (tuner_frequency < 87000000)
0741         return -EINVAL;
0742     else if (tuner_frequency < 130000000)
0743         cp = 3;
0744     else if (tuner_frequency < 160000000)
0745         cp = 5;
0746     else if (tuner_frequency < 200000000)
0747         cp = 6;
0748     else if (tuner_frequency < 290000000)
0749         cp = 3;
0750     else if (tuner_frequency < 420000000)
0751         cp = 5;
0752     else if (tuner_frequency < 480000000)
0753         cp = 6;
0754     else if (tuner_frequency < 620000000)
0755         cp = 3;
0756     else if (tuner_frequency < 830000000)
0757         cp = 5;
0758     else if (tuner_frequency < 895000000)
0759         cp = 7;
0760     else
0761         return -EINVAL;
0762 
0763     // determine band
0764     if (p->frequency < 49000000)
0765         return -EINVAL;
0766     else if (p->frequency < 159000000)
0767         band = 1;
0768     else if (p->frequency < 444000000)
0769         band = 2;
0770     else if (p->frequency < 861000000)
0771         band = 4;
0772     else
0773         return -EINVAL;
0774 
0775     // setup PLL filter and TDA9889
0776     switch (p->bandwidth_hz) {
0777     case 6000000:
0778         tda1004x_writereg(fe, 0x0C, 0x14);
0779         filter = 0;
0780         break;
0781 
0782     case 7000000:
0783         tda1004x_writereg(fe, 0x0C, 0x80);
0784         filter = 0;
0785         break;
0786 
0787     case 8000000:
0788         tda1004x_writereg(fe, 0x0C, 0x14);
0789         filter = 1;
0790         break;
0791 
0792     default:
0793         return -EINVAL;
0794     }
0795 
0796     // calculate divisor
0797     // ((36130000+((1000000/6)/2)) + Finput)/(1000000/6)
0798     tuner_frequency = (((p->frequency / 1000) * 6) + 217280) / 1000;
0799 
0800     // setup tuner buffer
0801     tuner_buf[0] = tuner_frequency >> 8;
0802     tuner_buf[1] = tuner_frequency & 0xff;
0803     tuner_buf[2] = 0xca;
0804     tuner_buf[3] = (cp << 5) | (filter << 3) | band;
0805 
0806     if (fe->ops.i2c_gate_ctrl)
0807         fe->ops.i2c_gate_ctrl(fe, 1);
0808     if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
0809         return -EIO;
0810 
0811     msleep(1);
0812     return 0;
0813 }
0814 
0815 static int philips_tdm1316l_request_firmware(struct dvb_frontend *fe,
0816                          const struct firmware **fw, char *name)
0817 {
0818     struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
0819 
0820     return request_firmware(fw, name, &budget_ci->budget.dev->pci->dev);
0821 }
0822 
0823 static struct tda1004x_config philips_tdm1316l_config = {
0824 
0825     .demod_address = 0x8,
0826     .invert = 0,
0827     .invert_oclk = 0,
0828     .xtal_freq = TDA10046_XTAL_4M,
0829     .agc_config = TDA10046_AGC_DEFAULT,
0830     .if_freq = TDA10046_FREQ_3617,
0831     .request_firmware = philips_tdm1316l_request_firmware,
0832 };
0833 
0834 static struct tda1004x_config philips_tdm1316l_config_invert = {
0835 
0836     .demod_address = 0x8,
0837     .invert = 1,
0838     .invert_oclk = 0,
0839     .xtal_freq = TDA10046_XTAL_4M,
0840     .agc_config = TDA10046_AGC_DEFAULT,
0841     .if_freq = TDA10046_FREQ_3617,
0842     .request_firmware = philips_tdm1316l_request_firmware,
0843 };
0844 
0845 static int dvbc_philips_tdm1316l_tuner_set_params(struct dvb_frontend *fe)
0846 {
0847     struct dtv_frontend_properties *p = &fe->dtv_property_cache;
0848     struct budget_ci *budget_ci = (struct budget_ci *) fe->dvb->priv;
0849     u8 tuner_buf[5];
0850     struct i2c_msg tuner_msg = {.addr = budget_ci->tuner_pll_address,
0851                     .flags = 0,
0852                     .buf = tuner_buf,
0853                     .len = sizeof(tuner_buf) };
0854     int tuner_frequency = 0;
0855     u8 band, cp, filter;
0856 
0857     // determine charge pump
0858     tuner_frequency = p->frequency + 36125000;
0859     if (tuner_frequency < 87000000)
0860         return -EINVAL;
0861     else if (tuner_frequency < 130000000) {
0862         cp = 3;
0863         band = 1;
0864     } else if (tuner_frequency < 160000000) {
0865         cp = 5;
0866         band = 1;
0867     } else if (tuner_frequency < 200000000) {
0868         cp = 6;
0869         band = 1;
0870     } else if (tuner_frequency < 290000000) {
0871         cp = 3;
0872         band = 2;
0873     } else if (tuner_frequency < 420000000) {
0874         cp = 5;
0875         band = 2;
0876     } else if (tuner_frequency < 480000000) {
0877         cp = 6;
0878         band = 2;
0879     } else if (tuner_frequency < 620000000) {
0880         cp = 3;
0881         band = 4;
0882     } else if (tuner_frequency < 830000000) {
0883         cp = 5;
0884         band = 4;
0885     } else if (tuner_frequency < 895000000) {
0886         cp = 7;
0887         band = 4;
0888     } else
0889         return -EINVAL;
0890 
0891     // assume PLL filter should always be 8MHz for the moment.
0892     filter = 1;
0893 
0894     // calculate divisor
0895     tuner_frequency = (p->frequency + 36125000 + (62500/2)) / 62500;
0896 
0897     // setup tuner buffer
0898     tuner_buf[0] = tuner_frequency >> 8;
0899     tuner_buf[1] = tuner_frequency & 0xff;
0900     tuner_buf[2] = 0xc8;
0901     tuner_buf[3] = (cp << 5) | (filter << 3) | band;
0902     tuner_buf[4] = 0x80;
0903 
0904     if (fe->ops.i2c_gate_ctrl)
0905         fe->ops.i2c_gate_ctrl(fe, 1);
0906     if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
0907         return -EIO;
0908 
0909     msleep(50);
0910 
0911     if (fe->ops.i2c_gate_ctrl)
0912         fe->ops.i2c_gate_ctrl(fe, 1);
0913     if (i2c_transfer(&budget_ci->budget.i2c_adap, &tuner_msg, 1) != 1)
0914         return -EIO;
0915 
0916     msleep(1);
0917 
0918     return 0;
0919 }
0920 
0921 static u8 dvbc_philips_tdm1316l_inittab[] = {
0922     0x80, 0x01,
0923     0x80, 0x00,
0924     0x81, 0x01,
0925     0x81, 0x00,
0926     0x00, 0x09,
0927     0x01, 0x69,
0928     0x03, 0x00,
0929     0x04, 0x00,
0930     0x07, 0x00,
0931     0x08, 0x00,
0932     0x20, 0x00,
0933     0x21, 0x40,
0934     0x22, 0x00,
0935     0x23, 0x00,
0936     0x24, 0x40,
0937     0x25, 0x88,
0938     0x30, 0xff,
0939     0x31, 0x00,
0940     0x32, 0xff,
0941     0x33, 0x00,
0942     0x34, 0x50,
0943     0x35, 0x7f,
0944     0x36, 0x00,
0945     0x37, 0x20,
0946     0x38, 0x00,
0947     0x40, 0x1c,
0948     0x41, 0xff,
0949     0x42, 0x29,
0950     0x43, 0x20,
0951     0x44, 0xff,
0952     0x45, 0x00,
0953     0x46, 0x00,
0954     0x49, 0x04,
0955     0x4a, 0x00,
0956     0x4b, 0x7b,
0957     0x52, 0x30,
0958     0x55, 0xae,
0959     0x56, 0x47,
0960     0x57, 0xe1,
0961     0x58, 0x3a,
0962     0x5a, 0x1e,
0963     0x5b, 0x34,
0964     0x60, 0x00,
0965     0x63, 0x00,
0966     0x64, 0x00,
0967     0x65, 0x00,
0968     0x66, 0x00,
0969     0x67, 0x00,
0970     0x68, 0x00,
0971     0x69, 0x00,
0972     0x6a, 0x02,
0973     0x6b, 0x00,
0974     0x70, 0xff,
0975     0x71, 0x00,
0976     0x72, 0x00,
0977     0x73, 0x00,
0978     0x74, 0x0c,
0979     0x80, 0x00,
0980     0x81, 0x00,
0981     0x82, 0x00,
0982     0x83, 0x00,
0983     0x84, 0x04,
0984     0x85, 0x80,
0985     0x86, 0x24,
0986     0x87, 0x78,
0987     0x88, 0x10,
0988     0x89, 0x00,
0989     0x90, 0x01,
0990     0x91, 0x01,
0991     0xa0, 0x04,
0992     0xa1, 0x00,
0993     0xa2, 0x00,
0994     0xb0, 0x91,
0995     0xb1, 0x0b,
0996     0xc0, 0x53,
0997     0xc1, 0x70,
0998     0xc2, 0x12,
0999     0xd0, 0x00,
1000     0xd1, 0x00,
1001     0xd2, 0x00,
1002     0xd3, 0x00,
1003     0xd4, 0x00,
1004     0xd5, 0x00,
1005     0xde, 0x00,
1006     0xdf, 0x00,
1007     0x61, 0x38,
1008     0x62, 0x0a,
1009     0x53, 0x13,
1010     0x59, 0x08,
1011     0xff, 0xff,
1012 };
1013 
1014 static struct stv0297_config dvbc_philips_tdm1316l_config = {
1015     .demod_address = 0x1c,
1016     .inittab = dvbc_philips_tdm1316l_inittab,
1017     .invert = 0,
1018     .stop_during_read = 1,
1019 };
1020 
1021 static struct tda10023_config tda10023_config = {
1022     .demod_address = 0xc,
1023     .invert = 0,
1024     .xtal = 16000000,
1025     .pll_m = 11,
1026     .pll_p = 3,
1027     .pll_n = 1,
1028     .deltaf = 0xa511,
1029 };
1030 
1031 static struct tda827x_config tda827x_config = {
1032     .config = 0,
1033 };
1034 
1035 /* TT S2-3200 DVB-S (STB0899) Inittab */
1036 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_1[] = {
1037 
1038     { STB0899_DEV_ID        , 0x81 },
1039     { STB0899_DISCNTRL1     , 0x32 },
1040     { STB0899_DISCNTRL2     , 0x80 },
1041     { STB0899_DISRX_ST0     , 0x04 },
1042     { STB0899_DISRX_ST1     , 0x00 },
1043     { STB0899_DISPARITY     , 0x00 },
1044     { STB0899_DISSTATUS     , 0x20 },
1045     { STB0899_DISF22        , 0x8c },
1046     { STB0899_DISF22RX      , 0x9a },
1047     { STB0899_SYSREG        , 0x0b },
1048     { STB0899_ACRPRESC      , 0x11 },
1049     { STB0899_ACRDIV1       , 0x0a },
1050     { STB0899_ACRDIV2       , 0x05 },
1051     { STB0899_DACR1         , 0x00 },
1052     { STB0899_DACR2         , 0x00 },
1053     { STB0899_OUTCFG        , 0x00 },
1054     { STB0899_MODECFG       , 0x00 },
1055     { STB0899_IRQSTATUS_3       , 0x30 },
1056     { STB0899_IRQSTATUS_2       , 0x00 },
1057     { STB0899_IRQSTATUS_1       , 0x00 },
1058     { STB0899_IRQSTATUS_0       , 0x00 },
1059     { STB0899_IRQMSK_3      , 0xf3 },
1060     { STB0899_IRQMSK_2      , 0xfc },
1061     { STB0899_IRQMSK_1      , 0xff },
1062     { STB0899_IRQMSK_0      , 0xff },
1063     { STB0899_IRQCFG        , 0x00 },
1064     { STB0899_I2CCFG        , 0x88 },
1065     { STB0899_I2CRPT        , 0x48 }, /* 12k Pullup, Repeater=16, Stop=disabled */
1066     { STB0899_IOPVALUE5     , 0x00 },
1067     { STB0899_IOPVALUE4     , 0x20 },
1068     { STB0899_IOPVALUE3     , 0xc9 },
1069     { STB0899_IOPVALUE2     , 0x90 },
1070     { STB0899_IOPVALUE1     , 0x40 },
1071     { STB0899_IOPVALUE0     , 0x00 },
1072     { STB0899_GPIO00CFG     , 0x82 },
1073     { STB0899_GPIO01CFG     , 0x82 },
1074     { STB0899_GPIO02CFG     , 0x82 },
1075     { STB0899_GPIO03CFG     , 0x82 },
1076     { STB0899_GPIO04CFG     , 0x82 },
1077     { STB0899_GPIO05CFG     , 0x82 },
1078     { STB0899_GPIO06CFG     , 0x82 },
1079     { STB0899_GPIO07CFG     , 0x82 },
1080     { STB0899_GPIO08CFG     , 0x82 },
1081     { STB0899_GPIO09CFG     , 0x82 },
1082     { STB0899_GPIO10CFG     , 0x82 },
1083     { STB0899_GPIO11CFG     , 0x82 },
1084     { STB0899_GPIO12CFG     , 0x82 },
1085     { STB0899_GPIO13CFG     , 0x82 },
1086     { STB0899_GPIO14CFG     , 0x82 },
1087     { STB0899_GPIO15CFG     , 0x82 },
1088     { STB0899_GPIO16CFG     , 0x82 },
1089     { STB0899_GPIO17CFG     , 0x82 },
1090     { STB0899_GPIO18CFG     , 0x82 },
1091     { STB0899_GPIO19CFG     , 0x82 },
1092     { STB0899_GPIO20CFG     , 0x82 },
1093     { STB0899_SDATCFG       , 0xb8 },
1094     { STB0899_SCLTCFG       , 0xba },
1095     { STB0899_AGCRFCFG      , 0x1c }, /* 0x11 */
1096     { STB0899_GPIO22        , 0x82 }, /* AGCBB2CFG */
1097     { STB0899_GPIO21        , 0x91 }, /* AGCBB1CFG */
1098     { STB0899_DIRCLKCFG     , 0x82 },
1099     { STB0899_CLKOUT27CFG       , 0x7e },
1100     { STB0899_STDBYCFG      , 0x82 },
1101     { STB0899_CS0CFG        , 0x82 },
1102     { STB0899_CS1CFG        , 0x82 },
1103     { STB0899_DISEQCOCFG        , 0x20 },
1104     { STB0899_GPIO32CFG     , 0x82 },
1105     { STB0899_GPIO33CFG     , 0x82 },
1106     { STB0899_GPIO34CFG     , 0x82 },
1107     { STB0899_GPIO35CFG     , 0x82 },
1108     { STB0899_GPIO36CFG     , 0x82 },
1109     { STB0899_GPIO37CFG     , 0x82 },
1110     { STB0899_GPIO38CFG     , 0x82 },
1111     { STB0899_GPIO39CFG     , 0x82 },
1112     { STB0899_NCOARSE       , 0x15 }, /* 0x15 = 27 Mhz Clock, F/3 = 198MHz, F/6 = 99MHz */
1113     { STB0899_SYNTCTRL      , 0x02 }, /* 0x00 = CLK from CLKI, 0x02 = CLK from XTALI */
1114     { STB0899_FILTCTRL      , 0x00 },
1115     { STB0899_SYSCTRL       , 0x00 },
1116     { STB0899_STOPCLK1      , 0x20 },
1117     { STB0899_STOPCLK2      , 0x00 },
1118     { STB0899_INTBUFSTATUS      , 0x00 },
1119     { STB0899_INTBUFCTRL        , 0x0a },
1120     { 0xffff            , 0xff },
1121 };
1122 
1123 static const struct stb0899_s1_reg tt3200_stb0899_s1_init_3[] = {
1124     { STB0899_DEMOD         , 0x00 },
1125     { STB0899_RCOMPC        , 0xc9 },
1126     { STB0899_AGC1CN        , 0x41 },
1127     { STB0899_AGC1REF       , 0x10 },
1128     { STB0899_RTC           , 0x7a },
1129     { STB0899_TMGCFG        , 0x4e },
1130     { STB0899_AGC2REF       , 0x34 },
1131     { STB0899_TLSR          , 0x84 },
1132     { STB0899_CFD           , 0xc7 },
1133     { STB0899_ACLC          , 0x87 },
1134     { STB0899_BCLC          , 0x94 },
1135     { STB0899_EQON          , 0x41 },
1136     { STB0899_LDT           , 0xdd },
1137     { STB0899_LDT2          , 0xc9 },
1138     { STB0899_EQUALREF      , 0xb4 },
1139     { STB0899_TMGRAMP       , 0x10 },
1140     { STB0899_TMGTHD        , 0x30 },
1141     { STB0899_IDCCOMP       , 0xfb },
1142     { STB0899_QDCCOMP       , 0x03 },
1143     { STB0899_POWERI        , 0x3b },
1144     { STB0899_POWERQ        , 0x3d },
1145     { STB0899_RCOMP         , 0x81 },
1146     { STB0899_AGCIQIN       , 0x80 },
1147     { STB0899_AGC2I1        , 0x04 },
1148     { STB0899_AGC2I2        , 0xf5 },
1149     { STB0899_TLIR          , 0x25 },
1150     { STB0899_RTF           , 0x80 },
1151     { STB0899_DSTATUS       , 0x00 },
1152     { STB0899_LDI           , 0xca },
1153     { STB0899_CFRM          , 0xf1 },
1154     { STB0899_CFRL          , 0xf3 },
1155     { STB0899_NIRM          , 0x2a },
1156     { STB0899_NIRL          , 0x05 },
1157     { STB0899_ISYMB         , 0x17 },
1158     { STB0899_QSYMB         , 0xfa },
1159     { STB0899_SFRH          , 0x2f },
1160     { STB0899_SFRM          , 0x68 },
1161     { STB0899_SFRL          , 0x40 },
1162     { STB0899_SFRUPH        , 0x2f },
1163     { STB0899_SFRUPM        , 0x68 },
1164     { STB0899_SFRUPL        , 0x40 },
1165     { STB0899_EQUAI1        , 0xfd },
1166     { STB0899_EQUAQ1        , 0x04 },
1167     { STB0899_EQUAI2        , 0x0f },
1168     { STB0899_EQUAQ2        , 0xff },
1169     { STB0899_EQUAI3        , 0xdf },
1170     { STB0899_EQUAQ3        , 0xfa },
1171     { STB0899_EQUAI4        , 0x37 },
1172     { STB0899_EQUAQ4        , 0x0d },
1173     { STB0899_EQUAI5        , 0xbd },
1174     { STB0899_EQUAQ5        , 0xf7 },
1175     { STB0899_DSTATUS2      , 0x00 },
1176     { STB0899_VSTATUS       , 0x00 },
1177     { STB0899_VERROR        , 0xff },
1178     { STB0899_IQSWAP        , 0x2a },
1179     { STB0899_ECNT1M        , 0x00 },
1180     { STB0899_ECNT1L        , 0x00 },
1181     { STB0899_ECNT2M        , 0x00 },
1182     { STB0899_ECNT2L        , 0x00 },
1183     { STB0899_ECNT3M        , 0x00 },
1184     { STB0899_ECNT3L        , 0x00 },
1185     { STB0899_FECAUTO1      , 0x06 },
1186     { STB0899_FECM          , 0x01 },
1187     { STB0899_VTH12         , 0xf0 },
1188     { STB0899_VTH23         , 0xa0 },
1189     { STB0899_VTH34         , 0x78 },
1190     { STB0899_VTH56         , 0x4e },
1191     { STB0899_VTH67         , 0x48 },
1192     { STB0899_VTH78         , 0x38 },
1193     { STB0899_PRVIT         , 0xff },
1194     { STB0899_VITSYNC       , 0x19 },
1195     { STB0899_RSULC         , 0xb1 }, /* DVB = 0xb1, DSS = 0xa1 */
1196     { STB0899_TSULC         , 0x42 },
1197     { STB0899_RSLLC         , 0x40 },
1198     { STB0899_TSLPL         , 0x12 },
1199     { STB0899_TSCFGH        , 0x0c },
1200     { STB0899_TSCFGM        , 0x00 },
1201     { STB0899_TSCFGL        , 0x0c },
1202     { STB0899_TSOUT         , 0x4d }, /* 0x0d for CAM */
1203     { STB0899_RSSYNCDEL     , 0x00 },
1204     { STB0899_TSINHDELH     , 0x02 },
1205     { STB0899_TSINHDELM     , 0x00 },
1206     { STB0899_TSINHDELL     , 0x00 },
1207     { STB0899_TSLLSTKM      , 0x00 },
1208     { STB0899_TSLLSTKL      , 0x00 },
1209     { STB0899_TSULSTKM      , 0x00 },
1210     { STB0899_TSULSTKL      , 0xab },
1211     { STB0899_PCKLENUL      , 0x00 },
1212     { STB0899_PCKLENLL      , 0xcc },
1213     { STB0899_RSPCKLEN      , 0xcc },
1214     { STB0899_TSSTATUS      , 0x80 },
1215     { STB0899_ERRCTRL1      , 0xb6 },
1216     { STB0899_ERRCTRL2      , 0x96 },
1217     { STB0899_ERRCTRL3      , 0x89 },
1218     { STB0899_DMONMSK1      , 0x27 },
1219     { STB0899_DMONMSK0      , 0x03 },
1220     { STB0899_DEMAPVIT      , 0x5c },
1221     { STB0899_PLPARM        , 0x1f },
1222     { STB0899_PDELCTRL      , 0x48 },
1223     { STB0899_PDELCTRL2     , 0x00 },
1224     { STB0899_BBHCTRL1      , 0x00 },
1225     { STB0899_BBHCTRL2      , 0x00 },
1226     { STB0899_HYSTTHRESH        , 0x77 },
1227     { STB0899_MATCSTM       , 0x00 },
1228     { STB0899_MATCSTL       , 0x00 },
1229     { STB0899_UPLCSTM       , 0x00 },
1230     { STB0899_UPLCSTL       , 0x00 },
1231     { STB0899_DFLCSTM       , 0x00 },
1232     { STB0899_DFLCSTL       , 0x00 },
1233     { STB0899_SYNCCST       , 0x00 },
1234     { STB0899_SYNCDCSTM     , 0x00 },
1235     { STB0899_SYNCDCSTL     , 0x00 },
1236     { STB0899_ISI_ENTRY     , 0x00 },
1237     { STB0899_ISI_BIT_EN        , 0x00 },
1238     { STB0899_MATSTRM       , 0x00 },
1239     { STB0899_MATSTRL       , 0x00 },
1240     { STB0899_UPLSTRM       , 0x00 },
1241     { STB0899_UPLSTRL       , 0x00 },
1242     { STB0899_DFLSTRM       , 0x00 },
1243     { STB0899_DFLSTRL       , 0x00 },
1244     { STB0899_SYNCSTR       , 0x00 },
1245     { STB0899_SYNCDSTRM     , 0x00 },
1246     { STB0899_SYNCDSTRL     , 0x00 },
1247     { STB0899_CFGPDELSTATUS1    , 0x10 },
1248     { STB0899_CFGPDELSTATUS2    , 0x00 },
1249     { STB0899_BBFERRORM     , 0x00 },
1250     { STB0899_BBFERRORL     , 0x00 },
1251     { STB0899_UPKTERRORM        , 0x00 },
1252     { STB0899_UPKTERRORL        , 0x00 },
1253     { 0xffff            , 0xff },
1254 };
1255 
1256 static struct stb0899_config tt3200_config = {
1257     .init_dev       = tt3200_stb0899_s1_init_1,
1258     .init_s2_demod      = stb0899_s2_init_2,
1259     .init_s1_demod      = tt3200_stb0899_s1_init_3,
1260     .init_s2_fec        = stb0899_s2_init_4,
1261     .init_tst       = stb0899_s1_init_5,
1262 
1263     .postproc       = NULL,
1264 
1265     .demod_address      = 0x68,
1266 
1267     .xtal_freq      = 27000000,
1268     .inversion      = IQ_SWAP_ON,
1269 
1270     .lo_clk         = 76500000,
1271     .hi_clk         = 99000000,
1272 
1273     .esno_ave       = STB0899_DVBS2_ESNO_AVE,
1274     .esno_quant     = STB0899_DVBS2_ESNO_QUANT,
1275     .avframes_coarse    = STB0899_DVBS2_AVFRAMES_COARSE,
1276     .avframes_fine      = STB0899_DVBS2_AVFRAMES_FINE,
1277     .miss_threshold     = STB0899_DVBS2_MISS_THRESHOLD,
1278     .uwp_threshold_acq  = STB0899_DVBS2_UWP_THRESHOLD_ACQ,
1279     .uwp_threshold_track    = STB0899_DVBS2_UWP_THRESHOLD_TRACK,
1280     .uwp_threshold_sof  = STB0899_DVBS2_UWP_THRESHOLD_SOF,
1281     .sof_search_timeout = STB0899_DVBS2_SOF_SEARCH_TIMEOUT,
1282 
1283     .btr_nco_bits       = STB0899_DVBS2_BTR_NCO_BITS,
1284     .btr_gain_shift_offset  = STB0899_DVBS2_BTR_GAIN_SHIFT_OFFSET,
1285     .crl_nco_bits       = STB0899_DVBS2_CRL_NCO_BITS,
1286     .ldpc_max_iter      = STB0899_DVBS2_LDPC_MAX_ITER,
1287 
1288     .tuner_get_frequency    = stb6100_get_frequency,
1289     .tuner_set_frequency    = stb6100_set_frequency,
1290     .tuner_set_bandwidth    = stb6100_set_bandwidth,
1291     .tuner_get_bandwidth    = stb6100_get_bandwidth,
1292     .tuner_set_rfsiggain    = NULL
1293 };
1294 
1295 static struct stb6100_config tt3200_stb6100_config = {
1296     .tuner_address  = 0x60,
1297     .refclock   = 27000000,
1298 };
1299 
1300 static void frontend_init(struct budget_ci *budget_ci)
1301 {
1302     switch (budget_ci->budget.dev->pci->subsystem_device) {
1303     case 0x100c:        // Hauppauge/TT Nova-CI budget (stv0299/ALPS BSRU6(tsa5059))
1304         budget_ci->budget.dvb_frontend =
1305             dvb_attach(stv0299_attach, &alps_bsru6_config, &budget_ci->budget.i2c_adap);
1306         if (budget_ci->budget.dvb_frontend) {
1307             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsru6_tuner_set_params;
1308             budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1309             break;
1310         }
1311         break;
1312 
1313     case 0x100f:        // Hauppauge/TT Nova-CI budget (stv0299b/Philips su1278(tsa5059))
1314         budget_ci->budget.dvb_frontend =
1315             dvb_attach(stv0299_attach, &philips_su1278_tt_config, &budget_ci->budget.i2c_adap);
1316         if (budget_ci->budget.dvb_frontend) {
1317             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_su1278_tt_tuner_set_params;
1318             break;
1319         }
1320         break;
1321 
1322     case 0x1010:        // TT DVB-C CI budget (stv0297/Philips tdm1316l(tda6651tt))
1323         budget_ci->tuner_pll_address = 0x61;
1324         budget_ci->budget.dvb_frontend =
1325             dvb_attach(stv0297_attach, &dvbc_philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1326         if (budget_ci->budget.dvb_frontend) {
1327             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = dvbc_philips_tdm1316l_tuner_set_params;
1328             break;
1329         }
1330         break;
1331 
1332     case 0x1011:        // Hauppauge/TT Nova-T budget (tda10045/Philips tdm1316l(tda6651tt) + TDA9889)
1333         budget_ci->tuner_pll_address = 0x63;
1334         budget_ci->budget.dvb_frontend =
1335             dvb_attach(tda10045_attach, &philips_tdm1316l_config, &budget_ci->budget.i2c_adap);
1336         if (budget_ci->budget.dvb_frontend) {
1337             budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1338             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1339             break;
1340         }
1341         break;
1342 
1343     case 0x1012:        // TT DVB-T CI budget (tda10046/Philips tdm1316l(tda6651tt))
1344         budget_ci->tuner_pll_address = 0x60;
1345         budget_ci->budget.dvb_frontend =
1346             dvb_attach(tda10046_attach, &philips_tdm1316l_config_invert, &budget_ci->budget.i2c_adap);
1347         if (budget_ci->budget.dvb_frontend) {
1348             budget_ci->budget.dvb_frontend->ops.tuner_ops.init = philips_tdm1316l_tuner_init;
1349             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = philips_tdm1316l_tuner_set_params;
1350             break;
1351         }
1352         break;
1353 
1354     case 0x1017:        // TT S-1500 PCI
1355         budget_ci->budget.dvb_frontend = dvb_attach(stv0299_attach, &alps_bsbe1_config, &budget_ci->budget.i2c_adap);
1356         if (budget_ci->budget.dvb_frontend) {
1357             budget_ci->budget.dvb_frontend->ops.tuner_ops.set_params = alps_bsbe1_tuner_set_params;
1358             budget_ci->budget.dvb_frontend->tuner_priv = &budget_ci->budget.i2c_adap;
1359 
1360             budget_ci->budget.dvb_frontend->ops.dishnetwork_send_legacy_command = NULL;
1361             if (dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, LNBP21_LLC, 0) == NULL) {
1362                 printk("%s: No LNBP21 found!\n", __func__);
1363                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1364                 budget_ci->budget.dvb_frontend = NULL;
1365             }
1366         }
1367         break;
1368 
1369     case 0x101a: /* TT Budget-C-1501 (philips tda10023/philips tda8274A) */
1370         budget_ci->budget.dvb_frontend = dvb_attach(tda10023_attach, &tda10023_config, &budget_ci->budget.i2c_adap, 0x48);
1371         if (budget_ci->budget.dvb_frontend) {
1372             if (dvb_attach(tda827x_attach, budget_ci->budget.dvb_frontend, 0x61, &budget_ci->budget.i2c_adap, &tda827x_config) == NULL) {
1373                 printk(KERN_ERR "%s: No tda827x found!\n", __func__);
1374                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1375                 budget_ci->budget.dvb_frontend = NULL;
1376             }
1377         }
1378         break;
1379 
1380     case 0x101b: /* TT S-1500B (BSBE1-D01A - STV0288/STB6000/LNBP21) */
1381         budget_ci->budget.dvb_frontend = dvb_attach(stv0288_attach, &stv0288_bsbe1_d01a_config, &budget_ci->budget.i2c_adap);
1382         if (budget_ci->budget.dvb_frontend) {
1383             if (dvb_attach(stb6000_attach, budget_ci->budget.dvb_frontend, 0x63, &budget_ci->budget.i2c_adap)) {
1384                 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1385                     printk(KERN_ERR "%s: No LNBP21 found!\n", __func__);
1386                     dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1387                     budget_ci->budget.dvb_frontend = NULL;
1388                 }
1389             } else {
1390                 printk(KERN_ERR "%s: No STB6000 found!\n", __func__);
1391                 dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1392                 budget_ci->budget.dvb_frontend = NULL;
1393             }
1394         }
1395         break;
1396 
1397     case 0x1019:        // TT S2-3200 PCI
1398         /*
1399          * NOTE! on some STB0899 versions, the internal PLL takes a longer time
1400          * to settle, aka LOCK. On the older revisions of the chip, we don't see
1401          * this, as a result on the newer chips the entire clock tree, will not
1402          * be stable after a freshly POWER 'ed up situation.
1403          * In this case, we should RESET the STB0899 (Active LOW) and wait for
1404          * PLL stabilization.
1405          *
1406          * On the TT S2 3200 and clones, the STB0899 demodulator's RESETB is
1407          * connected to the SAA7146 GPIO, GPIO2, Pin 142
1408          */
1409         /* Reset Demodulator */
1410         saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTLO);
1411         /* Wait for everything to die */
1412         msleep(50);
1413         /* Pull it up out of Reset state */
1414         saa7146_setgpio(budget_ci->budget.dev, 2, SAA7146_GPIO_OUTHI);
1415         /* Wait for PLL to stabilize */
1416         msleep(250);
1417         /*
1418          * PLL state should be stable now. Ideally, we should check
1419          * for PLL LOCK status. But well, never mind!
1420          */
1421         budget_ci->budget.dvb_frontend = dvb_attach(stb0899_attach, &tt3200_config, &budget_ci->budget.i2c_adap);
1422         if (budget_ci->budget.dvb_frontend) {
1423             if (dvb_attach(stb6100_attach, budget_ci->budget.dvb_frontend, &tt3200_stb6100_config, &budget_ci->budget.i2c_adap)) {
1424                 if (!dvb_attach(lnbp21_attach, budget_ci->budget.dvb_frontend, &budget_ci->budget.i2c_adap, 0, 0)) {
1425                     printk("%s: No LNBP21 found!\n", __func__);
1426                     dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1427                     budget_ci->budget.dvb_frontend = NULL;
1428                 }
1429             } else {
1430                     dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1431                     budget_ci->budget.dvb_frontend = NULL;
1432             }
1433         }
1434         break;
1435 
1436     }
1437 
1438     if (budget_ci->budget.dvb_frontend == NULL) {
1439         printk("budget-ci: A frontend driver was not found for device [%04x:%04x] subsystem [%04x:%04x]\n",
1440                budget_ci->budget.dev->pci->vendor,
1441                budget_ci->budget.dev->pci->device,
1442                budget_ci->budget.dev->pci->subsystem_vendor,
1443                budget_ci->budget.dev->pci->subsystem_device);
1444     } else {
1445         if (dvb_register_frontend
1446             (&budget_ci->budget.dvb_adapter, budget_ci->budget.dvb_frontend)) {
1447             printk("budget-ci: Frontend registration failed!\n");
1448             dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1449             budget_ci->budget.dvb_frontend = NULL;
1450         }
1451     }
1452 }
1453 
1454 static int budget_ci_attach(struct saa7146_dev *dev, struct saa7146_pci_extension_data *info)
1455 {
1456     struct budget_ci *budget_ci;
1457     int err;
1458 
1459     budget_ci = kzalloc(sizeof(struct budget_ci), GFP_KERNEL);
1460     if (!budget_ci) {
1461         err = -ENOMEM;
1462         goto out1;
1463     }
1464 
1465     dprintk(2, "budget_ci: %p\n", budget_ci);
1466 
1467     dev->ext_priv = budget_ci;
1468 
1469     err = ttpci_budget_init(&budget_ci->budget, dev, info, THIS_MODULE,
1470                 adapter_nr);
1471     if (err)
1472         goto out2;
1473 
1474     err = msp430_ir_init(budget_ci);
1475     if (err)
1476         goto out3;
1477 
1478     ciintf_init(budget_ci);
1479 
1480     budget_ci->budget.dvb_adapter.priv = budget_ci;
1481     frontend_init(budget_ci);
1482 
1483     ttpci_budget_init_hooks(&budget_ci->budget);
1484 
1485     return 0;
1486 
1487 out3:
1488     ttpci_budget_deinit(&budget_ci->budget);
1489 out2:
1490     kfree(budget_ci);
1491 out1:
1492     return err;
1493 }
1494 
1495 static int budget_ci_detach(struct saa7146_dev *dev)
1496 {
1497     struct budget_ci *budget_ci = (struct budget_ci *) dev->ext_priv;
1498     struct saa7146_dev *saa = budget_ci->budget.dev;
1499     int err;
1500 
1501     if (budget_ci->budget.ci_present)
1502         ciintf_deinit(budget_ci);
1503     msp430_ir_deinit(budget_ci);
1504     if (budget_ci->budget.dvb_frontend) {
1505         dvb_unregister_frontend(budget_ci->budget.dvb_frontend);
1506         dvb_frontend_detach(budget_ci->budget.dvb_frontend);
1507     }
1508     err = ttpci_budget_deinit(&budget_ci->budget);
1509 
1510     // disable frontend and CI interface
1511     saa7146_setgpio(saa, 2, SAA7146_GPIO_INPUT);
1512 
1513     kfree(budget_ci);
1514 
1515     return err;
1516 }
1517 
1518 static struct saa7146_extension budget_extension;
1519 
1520 MAKE_BUDGET_INFO(ttbs2, "TT-Budget/S-1500 PCI", BUDGET_TT);
1521 MAKE_BUDGET_INFO(ttbci, "TT-Budget/WinTV-NOVA-CI PCI", BUDGET_TT_HW_DISEQC);
1522 MAKE_BUDGET_INFO(ttbt2, "TT-Budget/WinTV-NOVA-T  PCI", BUDGET_TT);
1523 MAKE_BUDGET_INFO(ttbtci, "TT-Budget-T-CI PCI", BUDGET_TT);
1524 MAKE_BUDGET_INFO(ttbcci, "TT-Budget-C-CI PCI", BUDGET_TT);
1525 MAKE_BUDGET_INFO(ttc1501, "TT-Budget C-1501 PCI", BUDGET_TT);
1526 MAKE_BUDGET_INFO(tt3200, "TT-Budget S2-3200 PCI", BUDGET_TT);
1527 MAKE_BUDGET_INFO(ttbs1500b, "TT-Budget S-1500B PCI", BUDGET_TT);
1528 
1529 static const struct pci_device_id pci_tbl[] = {
1530     MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100c),
1531     MAKE_EXTENSION_PCI(ttbci, 0x13c2, 0x100f),
1532     MAKE_EXTENSION_PCI(ttbcci, 0x13c2, 0x1010),
1533     MAKE_EXTENSION_PCI(ttbt2, 0x13c2, 0x1011),
1534     MAKE_EXTENSION_PCI(ttbtci, 0x13c2, 0x1012),
1535     MAKE_EXTENSION_PCI(ttbs2, 0x13c2, 0x1017),
1536     MAKE_EXTENSION_PCI(ttc1501, 0x13c2, 0x101a),
1537     MAKE_EXTENSION_PCI(tt3200, 0x13c2, 0x1019),
1538     MAKE_EXTENSION_PCI(ttbs1500b, 0x13c2, 0x101b),
1539     {
1540      .vendor = 0,
1541      }
1542 };
1543 
1544 MODULE_DEVICE_TABLE(pci, pci_tbl);
1545 
1546 static struct saa7146_extension budget_extension = {
1547     .name = "budget_ci dvb",
1548     .flags = SAA7146_USE_I2C_IRQ,
1549 
1550     .module = THIS_MODULE,
1551     .pci_tbl = &pci_tbl[0],
1552     .attach = budget_ci_attach,
1553     .detach = budget_ci_detach,
1554 
1555     .irq_mask = MASK_03 | MASK_06 | MASK_10,
1556     .irq_func = budget_ci_irq,
1557 };
1558 
1559 static int __init budget_ci_init(void)
1560 {
1561     return saa7146_register_extension(&budget_extension);
1562 }
1563 
1564 static void __exit budget_ci_exit(void)
1565 {
1566     saa7146_unregister_extension(&budget_extension);
1567 }
1568 
1569 module_init(budget_ci_init);
1570 module_exit(budget_ci_exit);
1571 
1572 MODULE_LICENSE("GPL");
1573 MODULE_AUTHOR("Michael Hunold, Jack Thomasson, Andrew de Quincey, others");
1574 MODULE_DESCRIPTION("driver for the SAA7146 based so-called budget PCI DVB cards w/ CI-module produced by Siemens, Technotrend, Hauppauge");
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