pci/solo6x10/solo6x10-p2m.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2010-2013 Bluecherry, LLC <https://www.bluecherrydvr.com>
0004  *
0005  * Original author:
0006  * Ben Collins <bcollins@ubuntu.com>
0007  *
0008  * Additional work by:
0009  * John Brooks <john.brooks@bluecherry.net>
0010  */
0011
0012 #include <linux/kernel.h>
0013 #include <linux/module.h>
0014 #include <linux/slab.h>
0015
0016 #include "solo6x10.h"
0017
0018 static int multi_p2m;
0019 module_param(multi_p2m, uint, 0644);
0020 MODULE_PARM_DESC(multi_p2m,
0021          "Use multiple P2M DMA channels (default: no, 6010-only)");
0022
0023 static int desc_mode;
0024 module_param(desc_mode, uint, 0644);
0025 MODULE_PARM_DESC(desc_mode,
0026          "Allow use of descriptor mode DMA (default: no, 6010-only)");
0027
0028 int solo_p2m_dma(struct solo_dev *solo_dev, int wr,
0029          void *sys_addr, u32 ext_addr, u32 size,
0030          int repeat, u32 ext_size)
0031 {
0032     dma_addr_t dma_addr;
0033     int ret;
0034
0035     if (WARN_ON_ONCE((unsigned long)sys_addr & 0x03))
0036         return -EINVAL;
0037     if (WARN_ON_ONCE(!size))
0038         return -EINVAL;
0039
0040     dma_addr = dma_map_single(&solo_dev->pdev->dev, sys_addr, size,
0041                   wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
0042     if (dma_mapping_error(&solo_dev->pdev->dev, dma_addr))
0043         return -ENOMEM;
0044
0045     ret = solo_p2m_dma_t(solo_dev, wr, dma_addr, ext_addr, size,
0046                  repeat, ext_size);
0047
0048     dma_unmap_single(&solo_dev->pdev->dev, dma_addr, size,
0049              wr ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
0050
0051     return ret;
0052 }
0053
0054 /* Mutex must be held for p2m_id before calling this!! */
0055 int solo_p2m_dma_desc(struct solo_dev *solo_dev,
0056               struct solo_p2m_desc *desc, dma_addr_t desc_dma,
0057               int desc_cnt)
0058 {
0059     struct solo_p2m_dev *p2m_dev;
0060     unsigned int timeout;
0061     unsigned int config = 0;
0062     int ret = 0;
0063     unsigned int p2m_id = 0;
0064
0065     /* Get next ID. According to Softlogic, 6110 has problems on !=0 P2M */
0066     if (solo_dev->type != SOLO_DEV_6110 && multi_p2m)
0067         p2m_id = atomic_inc_return(&solo_dev->p2m_count) % SOLO_NR_P2M;
0068
0069     p2m_dev = &solo_dev->p2m_dev[p2m_id];
0070
0071     if (mutex_lock_interruptible(&p2m_dev->mutex))
0072         return -EINTR;
0073
0074     reinit_completion(&p2m_dev->completion);
0075     p2m_dev->error = 0;
0076
0077     if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && desc_mode) {
0078         /* For 6010 with more than one desc, we can do a one-shot */
0079         p2m_dev->desc_count = p2m_dev->desc_idx = 0;
0080         config = solo_reg_read(solo_dev, SOLO_P2M_CONFIG(p2m_id));
0081
0082         solo_reg_write(solo_dev, SOLO_P2M_DES_ADR(p2m_id), desc_dma);
0083         solo_reg_write(solo_dev, SOLO_P2M_DESC_ID(p2m_id), desc_cnt);
0084         solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config |
0085                    SOLO_P2M_DESC_MODE);
0086     } else {
0087         /* For single descriptors and 6110, we need to run each desc */
0088         p2m_dev->desc_count = desc_cnt;
0089         p2m_dev->desc_idx = 1;
0090         p2m_dev->descs = desc;
0091
0092         solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(p2m_id),
0093                    desc[1].dma_addr);
0094         solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(p2m_id),
0095                    desc[1].ext_addr);
0096         solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(p2m_id),
0097                    desc[1].cfg);
0098         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id),
0099                    desc[1].ctrl);
0100     }
0101
0102     timeout = wait_for_completion_timeout(&p2m_dev->completion,
0103                           solo_dev->p2m_jiffies);
0104
0105     if (WARN_ON_ONCE(p2m_dev->error))
0106         ret = -EIO;
0107     else if (timeout == 0) {
0108         solo_dev->p2m_timeouts++;
0109         ret = -EAGAIN;
0110     }
0111
0112     solo_reg_write(solo_dev, SOLO_P2M_CONTROL(p2m_id), 0);
0113
0114     /* Don't write here for the no_desc_mode case, because config is 0.
0115      * We can't test no_desc_mode again, it might race. */
0116     if (desc_cnt > 1 && solo_dev->type != SOLO_DEV_6110 && config)
0117         solo_reg_write(solo_dev, SOLO_P2M_CONFIG(p2m_id), config);
0118
0119     mutex_unlock(&p2m_dev->mutex);
0120
0121     return ret;
0122 }
0123
0124 void solo_p2m_fill_desc(struct solo_p2m_desc *desc, int wr,
0125             dma_addr_t dma_addr, u32 ext_addr, u32 size,
0126             int repeat, u32 ext_size)
0127 {
0128     WARN_ON_ONCE(dma_addr & 0x03);
0129     WARN_ON_ONCE(!size);
0130
0131     desc->cfg = SOLO_P2M_COPY_SIZE(size >> 2);
0132     desc->ctrl = SOLO_P2M_BURST_SIZE(SOLO_P2M_BURST_256) |
0133         (wr ? SOLO_P2M_WRITE : 0) | SOLO_P2M_TRANS_ON;
0134
0135     if (repeat) {
0136         desc->cfg |= SOLO_P2M_EXT_INC(ext_size >> 2);
0137         desc->ctrl |=  SOLO_P2M_PCI_INC(size >> 2) |
0138              SOLO_P2M_REPEAT(repeat);
0139     }
0140
0141     desc->dma_addr = dma_addr;
0142     desc->ext_addr = ext_addr;
0143 }
0144
0145 int solo_p2m_dma_t(struct solo_dev *solo_dev, int wr,
0146            dma_addr_t dma_addr, u32 ext_addr, u32 size,
0147            int repeat, u32 ext_size)
0148 {
0149     struct solo_p2m_desc desc[2];
0150
0151     solo_p2m_fill_desc(&desc[1], wr, dma_addr, ext_addr, size, repeat,
0152                ext_size);
0153
0154     /* No need for desc_dma since we know it is a single-shot */
0155     return solo_p2m_dma_desc(solo_dev, desc, 0, 1);
0156 }
0157
0158 void solo_p2m_isr(struct solo_dev *solo_dev, int id)
0159 {
0160     struct solo_p2m_dev *p2m_dev = &solo_dev->p2m_dev[id];
0161     struct solo_p2m_desc *desc;
0162
0163     if (p2m_dev->desc_count <= p2m_dev->desc_idx) {
0164         complete(&p2m_dev->completion);
0165         return;
0166     }
0167
0168     /* Setup next descriptor */
0169     p2m_dev->desc_idx++;
0170     desc = &p2m_dev->descs[p2m_dev->desc_idx];
0171
0172     solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), 0);
0173     solo_reg_write(solo_dev, SOLO_P2M_TAR_ADR(id), desc->dma_addr);
0174     solo_reg_write(solo_dev, SOLO_P2M_EXT_ADR(id), desc->ext_addr);
0175     solo_reg_write(solo_dev, SOLO_P2M_EXT_CFG(id), desc->cfg);
0176     solo_reg_write(solo_dev, SOLO_P2M_CONTROL(id), desc->ctrl);
0177 }
0178
0179 void solo_p2m_error_isr(struct solo_dev *solo_dev)
0180 {
0181     unsigned int err = solo_reg_read(solo_dev, SOLO_PCI_ERR);
0182     struct solo_p2m_dev *p2m_dev;
0183     int i;
0184
0185     if (!(err & (SOLO_PCI_ERR_P2M | SOLO_PCI_ERR_P2M_DESC)))
0186         return;
0187
0188     for (i = 0; i < SOLO_NR_P2M; i++) {
0189         p2m_dev = &solo_dev->p2m_dev[i];
0190         p2m_dev->error = 1;
0191         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
0192         complete(&p2m_dev->completion);
0193     }
0194 }
0195
0196 void solo_p2m_exit(struct solo_dev *solo_dev)
0197 {
0198     int i;
0199
0200     for (i = 0; i < SOLO_NR_P2M; i++)
0201         solo_irq_off(solo_dev, SOLO_IRQ_P2M(i));
0202 }
0203
0204 static int solo_p2m_test(struct solo_dev *solo_dev, int base, int size)
0205 {
0206     u32 *wr_buf;
0207     u32 *rd_buf;
0208     int i;
0209     int ret = -EIO;
0210     int order = get_order(size);
0211
0212     wr_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
0213     if (wr_buf == NULL)
0214         return -1;
0215
0216     rd_buf = (u32 *)__get_free_pages(GFP_KERNEL, order);
0217     if (rd_buf == NULL) {
0218         free_pages((unsigned long)wr_buf, order);
0219         return -1;
0220     }
0221
0222     for (i = 0; i < (size >> 3); i++)
0223         *(wr_buf + i) = (i << 16) | (i + 1);
0224
0225     for (i = (size >> 3); i < (size >> 2); i++)
0226         *(wr_buf + i) = ~((i << 16) | (i + 1));
0227
0228     memset(rd_buf, 0x55, size);
0229
0230     if (solo_p2m_dma(solo_dev, 1, wr_buf, base, size, 0, 0))
0231         goto test_fail;
0232
0233     if (solo_p2m_dma(solo_dev, 0, rd_buf, base, size, 0, 0))
0234         goto test_fail;
0235
0236     for (i = 0; i < (size >> 2); i++) {
0237         if (*(wr_buf + i) != *(rd_buf + i))
0238             goto test_fail;
0239     }
0240
0241     ret = 0;
0242
0243 test_fail:
0244     free_pages((unsigned long)wr_buf, order);
0245     free_pages((unsigned long)rd_buf, order);
0246
0247     return ret;
0248 }
0249
0250 int solo_p2m_init(struct solo_dev *solo_dev)
0251 {
0252     struct solo_p2m_dev *p2m_dev;
0253     int i;
0254
0255     for (i = 0; i < SOLO_NR_P2M; i++) {
0256         p2m_dev = &solo_dev->p2m_dev[i];
0257
0258         mutex_init(&p2m_dev->mutex);
0259         init_completion(&p2m_dev->completion);
0260
0261         solo_reg_write(solo_dev, SOLO_P2M_CONTROL(i), 0);
0262         solo_reg_write(solo_dev, SOLO_P2M_CONFIG(i),
0263                    SOLO_P2M_CSC_16BIT_565 |
0264                    SOLO_P2M_DESC_INTR_OPT |
0265                    SOLO_P2M_DMA_INTERVAL(0) |
0266                    SOLO_P2M_PCI_MASTER_MODE);
0267         solo_irq_on(solo_dev, SOLO_IRQ_P2M(i));
0268     }
0269
0270     /* Find correct SDRAM size */
0271     for (solo_dev->sdram_size = 0, i = 2; i >= 0; i--) {
0272         solo_reg_write(solo_dev, SOLO_DMA_CTRL,
0273                    SOLO_DMA_CTRL_REFRESH_CYCLE(1) |
0274                    SOLO_DMA_CTRL_SDRAM_SIZE(i) |
0275                    SOLO_DMA_CTRL_SDRAM_CLK_INVERT |
0276                    SOLO_DMA_CTRL_READ_CLK_SELECT |
0277                    SOLO_DMA_CTRL_LATENCY(1));
0278
0279         solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config |
0280                    SOLO_SYS_CFG_RESET);
0281         solo_reg_write(solo_dev, SOLO_SYS_CFG, solo_dev->sys_config);
0282
0283         switch (i) {
0284         case 2:
0285             if (solo_p2m_test(solo_dev, 0x07ff0000, 0x00010000) ||
0286                 solo_p2m_test(solo_dev, 0x05ff0000, 0x00010000))
0287                 continue;
0288             break;
0289
0290         case 1:
0291             if (solo_p2m_test(solo_dev, 0x03ff0000, 0x00010000))
0292                 continue;
0293             break;
0294
0295         default:
0296             if (solo_p2m_test(solo_dev, 0x01ff0000, 0x00010000))
0297                 continue;
0298         }
0299
0300         solo_dev->sdram_size = (32 << 20) << i;
0301         break;
0302     }
0303
0304     if (!solo_dev->sdram_size) {
0305         dev_err(&solo_dev->pdev->dev, "Error detecting SDRAM size\n");
0306         return -EIO;
0307     }
0308
0309     if (SOLO_SDRAM_END(solo_dev) > solo_dev->sdram_size) {
0310         dev_err(&solo_dev->pdev->dev,
0311             "SDRAM is not large enough (%u < %u)\n",
0312             solo_dev->sdram_size, SOLO_SDRAM_END(solo_dev));
0313         return -EIO;
0314     }
0315
0316     return 0;
0317 }